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vv_gulyaev |
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Thu Jul 30 09:54:46 2020
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# Process ID: 28010
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# Current directory: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017
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# Command line: vivado
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# Log file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.log
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# Journal file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
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update_compile_order -fileset sources_1
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open_run impl_1
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write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v
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write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf
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report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
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close_design
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open_run synth_1 -name synth_1
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save_constraints
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reset_run synth_1
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launch_runs synth_1 -jobs 16
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wait_on_run synth_1
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refresh_design
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create_generated_clock -name clk_gen -source [get_pins clkgen/clk_in1_p] -divide_by 2 -add -master_clock [get_clocks CLK_IN_P] [get_pins clkgen/clk_out1]
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save_constraints
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set_input_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_rx]
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set_output_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_tx]
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save_constraints
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reset_run synth_1
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launch_runs synth_1 -jobs 16
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wait_on_run synth_1
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close_design
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open_run synth_1 -name synth_1
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launch_runs impl_1 -jobs 16
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wait_on_run impl_1
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close_design
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open_run impl_1
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report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
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write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v
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write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf
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close_design
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reset_run synth_1
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launch_runs impl_1 -jobs 16
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wait_on_run impl_1
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open_run impl_1
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report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
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write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v
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write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf
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