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vv_gulyaev |
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Thu Jul 30 12:59:24 2020
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# Process ID: 5806
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# Current directory: /home/user/aes128/fpga/aes128_ecb_2017
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# Command line: vivado
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# Log file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.log
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# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
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INFO: [Project 1-313] Project file moved from '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017' since last save.
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
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open_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 6028.020 ; gain = 32.262 ; free physical = 2166 ; free virtual = 8341
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update_compile_order -fileset sources_1
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reset_run impl_1
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launch_runs impl_1 -jobs 2
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[Thu Jul 30 13:01:29 2020] Launched clk_gen_synth_1, axi_uartlite_module_synth_1, synth_1...
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Run output will be captured here:
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clk_gen_synth_1: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/runme.log
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axi_uartlite_module_synth_1: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/runme.log
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synth_1: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
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[Thu Jul 30 13:01:29 2020] Launched impl_1...
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Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
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reset_run synth_1
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launch_runs synth_1 -jobs 2
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[Thu Jul 30 13:13:35 2020] Launched synth_1...
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Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
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launch_runs impl_1 -jobs 2
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[Thu Jul 30 13:18:19 2020] Launched impl_1...
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Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
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open_run impl_1
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INFO: [Netlist 29-17] Analyzing 920 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2017.4
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INFO: [Device 21-403] Loading part xc7k325tffg900-2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_board.xdc]
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_board.xdc]
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_early.xdc]
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INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 6947.934 ; gain = 551.656 ; free physical = 2456 ; free virtual = 7532
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_early.xdc]
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap.xdc]
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap.xdc]
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Reading XDEF placement.
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Reading placer database...
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Reading XDEF routing.
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Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6952.934 ; gain = 5.000 ; free physical = 2451 ; free virtual = 7528
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Restored from archive | CPU: 0.170000 secs | Memory: 4.383476 MB |
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Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6952.934 ; gain = 5.000 ; free physical = 2451 ; free virtual = 7528
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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open_run: Time (s): cpu = 00:00:28 ; elapsed = 00:00:42 . Memory (MB): peak = 7123.285 ; gain = 941.883 ; free physical = 2362 ; free virtual = 7436
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report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
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launch_runs impl_1 -to_step write_bitstream -jobs 2
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[Thu Jul 30 13:22:05 2020] Launched impl_1...
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Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
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open_hw
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connect_hw_server
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-2222] Launching hw_server...
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INFO: [Labtools 27-2221] Launch Output:
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****** Xilinx hw_server v2017.4
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**** Build date : Dec 15 2017-21:02:11
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** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
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Targets(s) ", jsn1" may be locked by another hw_server.
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disconnect_hw_server localhost:3121
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connect_hw_server
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
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Targets(s) ", jsn1jsn2jsn3jsn4" may be locked by another hw_server.
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refresh_hw_server {localhost:3121}
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WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121]
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Check to make sure the cable targets connected to this machine are properly connected
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and powered up, then use the refresh_hw_server command to re-register the hardware targets.
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refresh_hw_server {localhost:3121}
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WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121]
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Check to make sure the cable targets connected to this machine are properly connected
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and powered up, then use the refresh_hw_server command to re-register the hardware targets.
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refresh_hw_server {localhost:3121}
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WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121]
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Check to make sure the cable targets connected to this machine are properly connected
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and powered up, then use the refresh_hw_server command to re-register the hardware targets.
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exit
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INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:32:52 2020...
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