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URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [vivado_pid28010.str] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
/*
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Xilinx Vivado v2017.4 (64-bit) [Major: 2017, Minor: 4]
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SW Build: 2086221 on Fri Dec 15 20:54:30 MST 2017
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IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017
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Process ID: 28010
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License: Customer
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Current time:   Thu Jul 30 09:55:06 MSK 2020
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Time zone:      Moscow Standard Time (W-SU)
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OS: Red Hat Enterprise Linux Server release 6.9 (Santiago)
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OS Version: 2.6.32-696.el6.x86_64
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OS Architecture: amd64
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Available processors (cores): 32
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18 
Display: :3.0
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Screen size: 2500x1300
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Screen resolution (DPI): 96
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Available screens: 1
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Available disk space: 41 GB
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Default font: family=Dialog,name=Dialog,style=plain,size=12
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Java version:   1.8.0_112 64-bit
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Java home:      /opt/cad/xilinx/Vivado2017/Vivado/2017.4/tps/lnx64/jre
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JVM executable location:        /opt/cad/xilinx/Vivado2017/Vivado/2017.4/tps/lnx64/jre/bin/java
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User name:      v.gulyaev
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User home directory: /home/v.gulyaev
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User working directory: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017
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User country:   US
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User language:  en
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User locale:    en_US
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RDI_BASEROOT: /opt/cad/xilinx/Vivado2017/Vivado
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HDI_APPROOT: /opt/cad/xilinx/Vivado2017/Vivado/2017.4
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RDI_DATADIR: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data
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RDI_BINDIR: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/bin
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Vivado preferences file location: /home/v.gulyaev/.Xilinx/Vivado/2017.4/vivado.xml
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Vivado preferences directory: /home/v.gulyaev/.Xilinx/Vivado/2017.4/
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Vivado layouts directory: /home/v.gulyaev/.Xilinx/Vivado/2017.4/layouts
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PlanAhead jar file location:    /opt/cad/xilinx/Vivado2017/Vivado/2017.4/lib/classes/planAhead.jar
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Vivado log file location:       /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.log
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Vivado journal file location:   /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.jou
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Engine tmp dir:         ./.Xil/Vivado-28010-gigant.modulew.local
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GUI allocated memory:   167 MB
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GUI max memory:         3,052 MB
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Engine allocated memory: 5,046 MB
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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*/
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// TclEventType: START_GUI
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// Tcl Message: start_gui
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selectMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // U (q, cj)
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// [GUI Memory]: 59 MB (+59555kb) [00:00:06]
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// [Engine Memory]: 5,046 MB (+5139737kb) [00:00:06]
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dismissMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // U (q, cj)
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selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // U (q, cj)
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dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // U (q, cj)
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// HMemoryUtils.trashcanNow. Engine heap size: 5,056 MB. GUI used memory: 38 MB. Current time: 7/30/20 9:55:08 AM MSK
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// Elapsed time: 11 seconds
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selectList(PAResourceQtoS.SyntheticaGettingStartedView_RECENT_PROJECTS, "/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr", 0); // q (O, cj)
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// Opening Vivado Project: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr. Version: Vivado v2017.4
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// bs (cj):  Open Project : addNotify
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// TclEventType: DEBUG_PROBE_SET_CHANGE
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// Tcl Message: open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
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// TclEventType: MSGMGR_MOVEMSG
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// TclEventType: FILESET_TARGET_UCF_CHANGE
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// TclEventType: FILE_SET_NEW
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// TclEventType: RUN_COMPLETED
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// TclEventType: FILESET_TARGET_UCF_CHANGE
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// TclEventType: RUN_COMPLETED
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// TclEventType: FILESET_TARGET_UCF_CHANGE
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// TclEventType: RUN_CURRENT
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// TclEventType: FILE_SET_CHANGE
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// TclEventType: PROJECT_NEW
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// [GUI Memory]: 65 MB (+3169kb) [00:00:26]
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// [GUI Memory]: 71 MB (+2265kb) [00:00:27]
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// Tcl Message: open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
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// Tcl Message: Scanning sources... Finished scanning sources
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// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip'.
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// HMemoryUtils.trashcanNow. Engine heap size: 5,189 MB. GUI used memory: 50 MB. Current time: 7/30/20 9:55:26 AM MSK
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// Tcl Message: open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 6310.867 ; gain = 89.688 ; free physical = 59919 ; free virtual = 99507
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// Project name: aes128_ecb; location: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017; part: xc7k325tffg900-2
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dismissDialog("Open Project"); // bs (cj)
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// TclEventType: DG_ANALYSIS_MSG_RESET
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// TclEventType: DG_GRAPH_GENERATED
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// Tcl Message: update_compile_order -fileset sources_1
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// Elapsed time: 28 seconds
95 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 18, true); // u (O, cj) - Node
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// Run Command: PAResourceCommand.PACommandNames_GOTO_IMPLEMENTED_DESIGN
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// bs (cj):  Open Implemented Design : addNotify
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// Tcl Message: open_run impl_1
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// HMemoryUtils.trashcanNow. Engine heap size: 5,263 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:56:03 AM MSK
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// [Engine Memory]: 5,306 MB (+7522kb) [00:01:26]
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// HMemoryUtils.trashcanNow. Engine heap size: 5,339 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:56:28 AM MSK
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// TclEventType: READ_XDC_FILE_START
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: LOC_CONSTRAINT_REMOVE
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: READ_XDC_FILE_END
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// TclEventType: READ_XDC_FILE_START
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// TclEventType: POWER_CNS_STALE
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// TclEventType: POWER_REPORT_STALE
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// TclEventType: SDC_CONSTRAINT_ADD
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// HMemoryUtils.trashcanNow. Engine heap size: 5,557 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:56:48 AM MSK
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// [Engine Memory]: 5,585 MB (+14974kb) [00:01:55]
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// HMemoryUtils.trashcanNow. Engine heap size: 5,758 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:57:03 AM MSK
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// TclEventType: SDC_CONSTRAINT_ADD
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// TclEventType: LOC_CONSTRAINT_REMOVE
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: LOC_CONSTRAINT_REMOVE
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SIGNAL_MODIFY
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// TclEventType: LOC_CONSTRAINT_ADD
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// TclEventType: SDC_CONSTRAINT_ADD
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// TclEventType: READ_XDC_FILE_END
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// TclEventType: DESIGN_NEW
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// HMemoryUtils.trashcanNow. Engine heap size: 6,039 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:57:08 AM MSK
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// [Engine Memory]: 6,040 MB (+183600kb) [00:02:09]
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// TclEventType: DESIGN_NEW
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// [GUI Memory]: 81 MB (+6786kb) [00:02:10]
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// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
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// [GUI Memory]: 87 MB (+2249kb) [00:02:12]
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// Device: addNotify
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// [GUI Memory]: 91 MB (+133kb) [00:02:13]
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// DeviceView Instantiated
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// TclEventType: CURR_DESIGN_SET
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// Tcl Message: INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Project 1-570] Preparing netlist for logic optimization
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// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_board.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_board.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_early.xdc]
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// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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// Tcl Message: get_clocks: Time (s): cpu = 00:00:20 ; elapsed = 00:00:37 . Memory (MB): peak = 7178.695 ; gain = 594.926 ; free physical = 59179 ; free virtual = 98775
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// Tcl Message: Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_early.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing.
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// Tcl Message: Read XDEF File: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 7183.691 ; gain = 4.000 ; free physical = 59174 ; free virtual = 98770
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// Tcl Message: Restored from archive | CPU: 0.220000 secs | Memory: 4.244667 MB |
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// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 7183.691 ; gain = 4.000 ; free physical = 59174 ; free virtual = 98770
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// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
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// [GUI Memory]: 97 MB (+1637kb) [00:02:14]
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// Tcl Message: open_run: Time (s): cpu = 00:00:52 ; elapsed = 00:01:17 . Memory (MB): peak = 7467.965 ; gain = 1118.707 ; free physical = 59003 ; free virtual = 98593
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// ExpRunCommands.openImplResults elapsed time: 77s
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// TclEventType: DRC_ADDED
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// Device view-level: 0.0
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// [GUI Memory]: 107 MB (+4908kb) [00:02:15]
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// RouteApi: Init Delay Mediator Swing Worker Finished
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// TclEventType: DRC_ADDED
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// TclEventType: METHODOLOGY_ADDED
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// TclEventType: POWER_UPDATED
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// [GUI Memory]: 116 MB (+3705kb) [00:02:16]
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// [GUI Memory]: 123 MB (+1093kb) [00:02:16]
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// [GUI Memory]: 129 MB (+270kb) [00:02:16]
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// TclEventType: TIMING_SUMMARY_UPDATED
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// 'dO' command handler elapsed time: 81 seconds
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// Elapsed time: 81 seconds
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dismissDialog("Open Implemented Design"); // bs (cj)
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// [GUI Memory]: 137 MB (+1565kb) [00:02:18]
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// [GUI Memory]: 146 MB (+2271kb) [00:02:19]
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// Elapsed time: 36 seconds
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selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aF (Q, cj)
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// Elapsed time: 18 seconds
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selectTree(PAResourceItoN.NetlistTreeView_NETLIST_TREE, "[aes128_ecb_fpga_wrap]", 0, true); // aW (O, cj) - Node
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selectTree(PAResourceItoN.NetlistTreeView_NETLIST_TREE, "[aes128_ecb_fpga_wrap]", 0, true, false, false, false, false, true); // aW (O, cj) - Double Click - Node
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// Run Command: PAResourceCommand.PACommandNames_GOTO_DEFINITION
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// Tcl Command: 'rdi::info_commands {w*}'
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// Tcl Command: 'rdi::info_commands {wri*}'
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// Tcl Command: 'rdi::info_commands {write*}'
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// Tcl Command: 'rdi::info_commands {write_*}'
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// Tcl Command: 'rdi::info_commands {write_v*}'
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// Elapsed time: 14 seconds
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setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_v", true); // aF (ae, cj)
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// Tcl Command: 'rdi::match_options {write_verilog} {}'
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// Tcl Command: 'rdi::match_options {write_verilog} {fo}'
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// Tcl Command: 'rdi::match_options {write_verilog} {for}'
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setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -for", true); // aF (ae, cj)
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// Tcl Command: 'rdi::match_options {write_verilog} {}'
190 
// Tcl Command: 'rdi::match_options {write_verilog} {m}'
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// Tcl Command: 'rdi::match_options {write_verilog} {mo}'
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setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mo", true); // aF (ae, cj)
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// Tcl Command: 'rdi::info_commands bd::match_path'
194 
// Tcl Command: 'rdi::info_commands bd::match_path'
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// Tcl Command: 'rdi::info_commands bd::match_path'
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setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./ne", true); // aF (ae, cj)
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// Tcl Command: 'rdi::info_commands bd::match_path'
198 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/", true); // aF (ae, cj)
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applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v"); // aF (ae, cj)
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// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
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// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
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// Tcl Message: write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v
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// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.v
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// Tcl Command: 'rdi::info_commands {write_*}'
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// Tcl Command: 'rdi::info_commands {write_*}'
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// Tcl Command: 'rdi::info_commands {write_s*}'
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// Tcl Command: 'rdi::info_commands {write_sd*}'
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// Tcl Command: 'rdi::info_commands {write_sdf*}'
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// Tcl Command: 'rdi::info_commands bd::match_path'
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// Tcl Command: 'rdi::info_commands bd::match_path'
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// Elapsed time: 18 seconds
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setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.s", true); // aF (ae, cj)
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applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf"); // aF (ae, cj)
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// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
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// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
216 
// Tcl Message: write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf
217 
// bs (cj):  Tcl Command Line : addNotify
218 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.sdf
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dismissDialog("Tcl Command Line"); // bs (cj)
220 
// TclEventType: DG_GRAPH_STALE
221 
// TclEventType: FILE_SET_CHANGE
222 
// TclEventType: DG_ANALYSIS_MSG_RESET
223 
// TclEventType: DG_GRAPH_GENERATED
224 
// HMemoryUtils.trashcanNow. Engine heap size: 6,261 MB. GUI used memory: 101 MB. Current time: 7/30/20 10:27:08 AM MSK
225 
// Elapsed time: 2506 seconds
226 
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
227 
// Elapsed time: 33 seconds
228 
selectTab((HResource) null, (HResource) null, "Sources", 0); // aF (Q, cj)
229 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 4); // B (D, cj)
230 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 5); // B (D, cj)
231 
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i (N, cj)
232 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module]", 1, true); // B (D, cj) - Node
233 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module]", 1); // B (D, cj)
234 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, Synthesis]", 3); // B (D, cj)
235 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, axi_uartlite_module_sim_netlist.v]", 15, false); // B (D, cj)
236 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, axi_uartlite_module_sim_netlist.v]", 15, false, false, false, false, false, true); // B (D, cj) - Double Click
237 
// Elapsed time: 12 seconds
238 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
239 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
240 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 21, false); // u (O, cj)
241 
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
242 
// aF (cj): Report Timing Summary: addNotify
243 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (aF)
244 
dismissDialog("Report Timing Summary"); // aF (cj)
245 
// bs (cj):  Report Timing Summary : addNotify
246 
// TclEventType: TIMING_RESULTS_STALE
247 
// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
248 
// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
249 
// TclEventType: TIMING_SUMMARY_UPDATED
250 
// [GUI Memory]: 156 MB (+2909kb) [00:47:28]
251 
dismissDialog("Report Timing Summary"); // bs (cj)
252 
// Elapsed time: 18 seconds
253 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 5); // a (O, cj)
254 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 7); // a (O, cj)
255 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Setup 0.877 ns]", 8, false); // a (O, cj)
256 
selectTableHeader(PAResourceTtoZ.TimingItemFlatTablePanel_TABLE, "From", 4); // i (O, cj)
257 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Hold 0.094 ns]", 9, false); // a (O, cj)
258 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 7, true); // a (O, cj) - Node
259 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Setup 0.877 ns]", 8, false); // a (O, cj)
260 
collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
261 
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
262 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
263 
// Run Command: PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN
264 
// e (cj): Close Design: addNotify
265 
selectButton(PAResourceAtoD.ClosePlanner_YES, "Yes"); // a (e)
266 
// TclEventType: DESIGN_CLOSE
267 
// HMemoryUtils.trashcanNow. Engine heap size: 6,275 MB. GUI used memory: 86 MB. Current time: 7/30/20 10:43:21 AM MSK
268 
// TclEventType: TIMING_RESULTS_UNLOAD
269 
// Engine heap size: 6,275 MB. GUI used memory: 87 MB. Current time: 7/30/20 10:43:21 AM MSK
270 
// TclEventType: CURR_DESIGN_SET
271 
// TclEventType: DESIGN_CLOSE
272 
// bi (cj): Synthesis is Out-of-date: addNotify
273 
// Tcl Message: close_design
274 
dismissDialog("Close Design"); // e (cj)
275 
selectButton(PAResourceQtoS.StaleRunDialog_OPEN_DESIGN, "Open Design"); // a (bi)
276 
// bs (cj):  Open Synthesized Design : addNotify
277 
dismissDialog("Synthesis is Out-of-date"); // bi (cj)
278 
// Tcl Message: open_run synth_1 -name synth_1
279 
// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7k325tffg900-2
280 
// TclEventType: READ_XDC_FILE_START
281 
// TclEventType: LOC_CONSTRAINT_ADD
282 
// TclEventType: LOC_CONSTRAINT_REMOVE
283 
// TclEventType: LOC_CONSTRAINT_ADD
284 
// TclEventType: READ_XDC_FILE_END
285 
// TclEventType: READ_XDC_FILE_START
286 
// TclEventType: POWER_CNS_STALE
287 
// TclEventType: POWER_REPORT_STALE
288 
// TclEventType: SDC_CONSTRAINT_ADD
289 
// TclEventType: READ_XDC_FILE_END
290 
// TclEventType: READ_XDC_FILE_START
291 
// TclEventType: READ_XDC_FILE_END
292 
// TclEventType: READ_XDC_FILE_START
293 
// TclEventType: SDC_CONSTRAINT_ADD
294 
// TclEventType: READ_XDC_FILE_END
295 
// TclEventType: READ_XDC_FILE_START
296 
// TclEventType: LOC_CONSTRAINT_REMOVE
297 
// TclEventType: LOC_CONSTRAINT_ADD
298 
// TclEventType: LOC_CONSTRAINT_REMOVE
299 
// TclEventType: LOC_CONSTRAINT_ADD
300 
// TclEventType: SIGNAL_MODIFY
301 
// TclEventType: LOC_CONSTRAINT_ADD
302 
// TclEventType: SIGNAL_MODIFY
303 
// TclEventType: LOC_CONSTRAINT_ADD
304 
// TclEventType: SIGNAL_MODIFY
305 
// TclEventType: LOC_CONSTRAINT_ADD
306 
// TclEventType: SIGNAL_MODIFY
307 
// TclEventType: LOC_CONSTRAINT_ADD
308 
// TclEventType: SIGNAL_MODIFY
309 
// TclEventType: LOC_CONSTRAINT_ADD
310 
// TclEventType: READ_XDC_FILE_END
311 
// TclEventType: READ_XDC_FILE_START
312 
// TclEventType: SDC_CONSTRAINT_ADD
313 
// TclEventType: READ_XDC_FILE_END
314 
// TclEventType: FLOORPLAN_MODIFY
315 
// TclEventType: DESIGN_NEW
316 
// HMemoryUtils.trashcanNow. Engine heap size: 6,340 MB. GUI used memory: 60 MB. Current time: 7/30/20 10:43:29 AM MSK
317 
// TclEventType: DESIGN_NEW
318 
// [Engine Memory]: 6,345 MB (+3453kb) [00:48:30]
319 
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
320 
// Device: addNotify
321 
// DeviceView Instantiated
322 
// TclEventType: CURR_DESIGN_SET
323 
// Tcl Message: INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen' INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite' INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization
324 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
325 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
326 
// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
327 
// Device view-level: 0.0
328 
// RouteApi: Init Delay Mediator Swing Worker Finished
329 
// 'dO' command handler elapsed time: 19 seconds
330 
dismissDialog("Open Synthesized Design"); // bs (cj)
331 
// Elapsed time: 81 seconds
332 
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
333 
collapseTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation]", 8); // ah (O, cj)
334 
// Elapsed time: 11 seconds
335 
expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, synth_1, [Vivado 12-508] No pins matched 'clkgen/inst/mmcm_adv_inst/CLKOUT0'. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc:1]. ]", 6); // ah (O, cj)
336 
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, synth_1, [Vivado 12-508] No pins matched 'clkgen/inst/mmcm_adv_inst/CLKOUT0'. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc:1]. ]", 6, true); // ah (O, cj) - Node
337 
messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc;-;;-;16;-;line;-;1;-;;-;16;-;"); // ah (O, cj)
338 
// Elapsed time: 24 seconds
339 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design, Edit Timing Constraints]", 17, false); // u (O, cj)
340 
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Project Manager]", 0); // u (O, cj)
341 
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
342 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
343 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Inputs (1), Set Input Delay (1)]", 12, false); // bh (O, cj)
344 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "4 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 5.0 ; [get_ports uart_rx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
345 
selectButton(PAResourceEtoH.EditIODelayTablePanel_SPECIFY_CLOCK_PIN_OR_PORT, (String) null); // q (g, cj)
346 
// p (cj): Specify Clock: addNotify
347 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
348 
// bs (p):  Find Names : addNotify
349 
dismissDialog("Find Names"); // bs (p)
350 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1); // f (c, p)
351 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
352 
// Tcl Command: 'get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]'
353 
selectList(RDIResource.HDualList_FIND_RESULTS, "clkfbout_clk_gen", 1); // f (c, p)
354 
selectList(RDIResource.HDualList_SELECTED_NAMES, "clk_out1_clk_gen", 0); // f (c, p)
355 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_LEFT, "moveLeft"); // k (e, p)
356 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1); // f (c, p)
357 
selectList(RDIResource.HDualList_FIND_RESULTS, "clkfbout_clk_gen", 2, false, true, false, false, false); // f (c, p) - Control Key
358 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1, true, false, false, false, false); // f (c, p) - Shift Key
359 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
360 
// Tcl Command: 'get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]'
361 
// Elapsed time: 16 seconds
362 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
363 
editTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "[get_clocks [list  [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]]", 0, "   Clock   ", 1); // v (O, cj)
364 
dismissDialog("Specify Clock"); // p (cj)
365 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Outputs (1), Set Output Delay (1)]", 14, false); // bh (O, cj)
366 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "5 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 1.0 ; [get_ports uart_tx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
367 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "5 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 1.0 ; [get_ports uart_tx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1, false, false, false, false, true); // v (O, cj) - Double Click
368 
// bK (cj): Edit Set Output Delay: addNotify
369 
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT_TO_WHICH_OUTPUT, (String) null); // q (g, bK)
370 
// p (cj): Specify Clock: addNotify
371 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
372 
// bs (p):  Find Names : addNotify
373 
dismissDialog("Find Names"); // bs (p)
374 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1); // f (c, p)
375 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
376 
// Tcl Command: 'get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]'
377 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
378 
dismissDialog("Specify Clock"); // p (cj)
379 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bK)
380 
// bs (bK):  Validate XDC Command : addNotify
381 
// [GUI Memory]: 167 MB (+2393kb) [00:51:58]
382 
dismissDialog("Validate XDC Command"); // bs (bK)
383 
dismissDialog("Edit Set Output Delay"); // bK (cj)
384 
selectButton(PAResourceTtoZ.XdcEditorView_APPLY_ALL_CHANGES_TO_XDC_CONSTRAINTS, "Apply"); // a (a, cj)
385 
// bs (cj):  Apply All XDC Constraints : addNotify
386 
// TclEventType: SDC_CONSTR_MGR_CLEAR
387 
// TclEventType: POWER_REPORT_STALE
388 
// TclEventType: SDC_CONSTRAINT_ADD
389 
dismissDialog("Apply All XDC Constraints"); // bs (cj)
390 
selectButton(PAResourceCommand.PACommandNames_SAVE_DESIGN, "save_design"); // B (f, cj)
391 
// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
392 
// bs (cj):  Save Constraints : addNotify
393 
// TclEventType: DESIGN_STALE
394 
// TclEventType: FILE_SET_CHANGE
395 
// TclEventType: DESIGN_SAVE
396 
// Tcl Message: save_constraints
397 
dismissDialog("Save Constraints"); // bs (cj)
398 
closeView(PAResourceOtoP.PAViews_TIMING_CONSTRAINTS, "Timing Constraints"); // a
399 
// [GUI Memory]: 176 MB (+791kb) [00:52:14]
400 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // u (O, cj)
401 
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
402 
// x (cj): Run Synthesis: addNotify
403 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
404 
// bs (cj):  Resetting Runs : addNotify
405 
// TclEventType: RUN_MODIFY
406 
dismissDialog("Run Synthesis"); // x (cj)
407 
// TclEventType: RUN_RESET
408 
// TclEventType: DESIGN_STALE
409 
// TclEventType: RUN_RESET
410 
// HMemoryUtils.trashcanNow. Engine heap size: 6,352 MB. GUI used memory: 156 MB. Current time: 7/30/20 10:47:21 AM MSK
411 
// TclEventType: RUN_RESET
412 
// TclEventType: RUN_MODIFY
413 
// Tcl Message: reset_run synth_1
414 
// TclEventType: RUN_MODIFY
415 
// bs (cj):  Starting Design Runs : addNotify
416 
// TclEventType: FILESET_TARGET_UCF_CHANGE
417 
// TclEventType: DESIGN_STALE
418 
// TclEventType: RUN_LAUNCH
419 
// TclEventType: RUN_MODIFY
420 
// Tcl Message: launch_runs synth_1 -jobs 16
421 
// Tcl Message: [Thu Jul 30 10:47:22 2020] Launched synth_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
422 
// 'k' command handler elapsed time: 7 seconds
423 
dismissDialog("Starting Design Runs"); // bs (cj)
424 
// Elapsed time: 26 seconds
425 
selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // k (j, cj)
426 
// TclEventType: DESIGN_STALE
427 
// TclEventType: RUN_COMPLETED
428 
// Elapsed time: 353 seconds
429 
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, synth_1, [Vivado 12-508] No pins matched 'clkgen/inst/mmcm_adv_inst/CLKOUT0'. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc:1]. ]", 6, true); // ah (O, cj) - Node
430 
messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc;-;;-;16;-;line;-;1;-;;-;16;-;"); // ah (O, cj)
431 
// [GUI Memory]: 185 MB (+226kb) [01:00:28]
432 
// Elapsed time: 149 seconds
433 
selectCodeEditor("timings.xdc", 1047, 145); // cd (w, cj)
434 
// Elapsed time: 24 seconds
435 
selectTab((HResource) null, (HResource) null, "Sources", 1); // aF (Q, cj)
436 
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, Synthesis]", 3); // B (D, cj)
437 
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i (N, cj)
438 
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i (N, cj)
439 
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module]", 1); // B (D, cj)
440 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen]", 3); // B (D, cj)
441 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis]", 5); // B (D, cj)
442 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.xdc]", 14, false); // B (D, cj)
443 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.xdc]", 14, false, false, false, false, false, true); // B (D, cj) - Double Click
444 
// Elapsed time: 10 seconds
445 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen_ooc.xdc]", 15, false); // B (D, cj)
446 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen_ooc.xdc]", 15, false, false, false, false, false, true); // B (D, cj) - Double Click
447 
// [GUI Memory]: 198 MB (+4288kb) [01:02:07]
448 
// Elapsed time: 21 seconds
449 
selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "clk_gen.xdc", 3); // k (j, cj)
450 
// Elapsed time: 12 seconds
451 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.v]", 13, false); // B (D, cj)
452 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.v]", 13, false, false, false, false, false, true); // B (D, cj) - Double Click
453 
// HMemoryUtils.trashcanNow. Engine heap size: 6,389 MB. GUI used memory: 110 MB. Current time: 7/30/20 10:57:43 AM MSK
454 
// Elapsed time: 13 seconds
455 
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen]", 3); // B (D, cj)
456 
selectTab((HResource) null, (HResource) null, "Device Constraints", 2); // aF (Q, cj)
457 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
458 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
459 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
460 
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
461 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design, Edit Timing Constraints]", 17, false); // u (O, cj)
462 
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
463 
// Elapsed time: 16 seconds
464 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Clocks (2), Create Generated Clock (0)]", 2, false); // bh (O, cj)
465 
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
466 
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
467 
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0, false, false, false, false, true); // n (O, cj) - Double Click
468 
// Run Command: PAResourceCommand.PACommandNames_XDC_CREATE_GENERATED_CLOCK
469 
// cF (cj): Design Modified on Disk: addNotify
470 
selectButton(PAResourceOtoP.ProjectTab_RELOAD, "Reload"); // a (cF)
471 
// 'f' command handler elapsed time: 3 seconds
472 
// bs (cj):  Reloading : addNotify
473 
dismissDialog("Design Modified on Disk"); // cF (cj)
474 
// Tcl Message: refresh_design
475 
// TclEventType: DESIGN_REFRESH
476 
// HMemoryUtils.trashcanNow. Engine heap size: 6,364 MB. GUI used memory: 102 MB. Current time: 7/30/20 10:58:40 AM MSK
477 
// Engine heap size: 6,364 MB. GUI used memory: 103 MB. Current time: 7/30/20 10:58:40 AM MSK
478 
// Tcl Message: INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen' INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite'
479 
// TclEventType: READ_XDC_FILE_START
480 
// TclEventType: LOC_CONSTRAINT_ADD
481 
// TclEventType: LOC_CONSTRAINT_REMOVE
482 
// TclEventType: LOC_CONSTRAINT_ADD
483 
// TclEventType: READ_XDC_FILE_END
484 
// TclEventType: READ_XDC_FILE_START
485 
// TclEventType: POWER_CNS_STALE
486 
// TclEventType: POWER_REPORT_STALE
487 
// TclEventType: SDC_CONSTRAINT_ADD
488 
// TclEventType: READ_XDC_FILE_END
489 
// TclEventType: READ_XDC_FILE_START
490 
// TclEventType: READ_XDC_FILE_END
491 
// TclEventType: READ_XDC_FILE_START
492 
// TclEventType: SDC_CONSTRAINT_ADD
493 
// TclEventType: READ_XDC_FILE_END
494 
// TclEventType: READ_XDC_FILE_START
495 
// TclEventType: LOC_CONSTRAINT_REMOVE
496 
// TclEventType: LOC_CONSTRAINT_ADD
497 
// TclEventType: LOC_CONSTRAINT_REMOVE
498 
// TclEventType: LOC_CONSTRAINT_ADD
499 
// TclEventType: SIGNAL_MODIFY
500 
// TclEventType: LOC_CONSTRAINT_ADD
501 
// TclEventType: SIGNAL_MODIFY
502 
// TclEventType: LOC_CONSTRAINT_ADD
503 
// TclEventType: SIGNAL_MODIFY
504 
// TclEventType: LOC_CONSTRAINT_ADD
505 
// TclEventType: SIGNAL_MODIFY
506 
// TclEventType: LOC_CONSTRAINT_ADD
507 
// TclEventType: SIGNAL_MODIFY
508 
// TclEventType: LOC_CONSTRAINT_ADD
509 
// TclEventType: READ_XDC_FILE_END
510 
// TclEventType: READ_XDC_FILE_START
511 
// TclEventType: SDC_CONSTRAINT_ADD
512 
// TclEventType: READ_XDC_FILE_END
513 
// TclEventType: FLOORPLAN_MODIFY
514 
// TclEventType: DESIGN_REFRESH
515 
// HMemoryUtils.trashcanNow. Engine heap size: 6,359 MB. GUI used memory: 77 MB. Current time: 7/30/20 10:58:42 AM MSK
516 
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
517 
// Device: addNotify
518 
// DeviceView Instantiated
519 
// Tcl Message: INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization
520 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
521 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
522 
// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
523 
// Tcl Message: refresh_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 7555.016 ; gain = 14.008 ; free physical = 57616 ; free virtual = 97572
524 
// RouteApi: Init Delay Mediator Swing Worker Finished
525 
dismissDialog("Reloading"); // bs (cj)
526 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Clocks (2), Create Generated Clock (0)]", 2, false); // bh (O, cj)
527 
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
528 
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
529 
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0, false, false, false, false, true); // n (O, cj) - Double Click
530 
// Run Command: PAResourceCommand.PACommandNames_XDC_CREATE_GENERATED_CLOCK
531 
// bh (cj): Create Generated Clock: addNotify
532 
// Elapsed time: 10 seconds
533 
setText(PAResourceEtoH.GeneratedClockCreationPanel_CLOCK_NAME, "clk_gen"); // X (Z, bh)
534 
selectButton(PAResourceQtoS.SdcGetObjectsPanel_SPECIFY_MASTER_PIN, (String) null); // q (h, bh)
535 
// p (cj): Specify Master Pin: addNotify
536 
// Elapsed time: 13 seconds
537 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
538 
// bs (p):  Find Names : addNotify
539 
dismissDialog("Find Names"); // bs (p)
540 
// Elapsed time: 19 seconds
541 
selectList(RDIResource.HDualList_FIND_RESULTS, "clkgen/clk_in1_p", 18); // f (c, p)
542 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
543 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
544 
dismissDialog("Specify Master Pin"); // p (cj)
545 
// Elapsed time: 13 seconds
546 
selectButton(PAResourceQtoS.SdcGetObjectsPanel_SPECIFY_MASTER_CLOCK, (String) null); // q (g, bh)
547 
// p (cj): Specify Master Clock: addNotify
548 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
549 
// bs (p):  Find Names : addNotify
550 
dismissDialog("Find Names"); // bs (p)
551 
selectList(RDIResource.HDualList_FIND_RESULTS, "CLK_IN_P", 0); // f (c, p)
552 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
553 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
554 
dismissDialog("Specify Master Clock"); // p (cj)
555 
setSpinner(PAResourceEtoH.GeneratedClockCreationPanel_OPTIONAL_DIVIDE_FREQUENCY, "2"); // c (N, bh)
556 
selectButton(PAResourceQtoS.SdcGetObjectsPanel_SPECIFY_GENERATED_CLOCK_SOURCE_OBJECTS, (String) null); // q (h, bh)
557 
// p (cj): Specify Generated Clock Source Objects: addNotify
558 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
559 
// bs (p):  Find Names : addNotify
560 
dismissDialog("Find Names"); // bs (p)
561 
selectList(RDIResource.HDualList_FIND_RESULTS, "clkgen/clk_out1", 19); // f (c, p)
562 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
563 
selectButton(PAResourceEtoH.GetObjectsPanel_SET, "Set"); // a (p)
564 
dismissDialog("Specify Generated Clock Source Objects"); // p (cj)
565 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bh)
566 
// bs (bh):  Validate XDC Command : addNotify
567 
// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Vivado 12-672] Cannot specify -master_clock without specifying -add.
568 
// CommandFailedException: null
569 
// Tcl Message: ERROR: [Vivado 12-672] Cannot specify -master_clock without specifying -add.
570 
// e (cj): Validate XDC Command: addNotify
571 
// Elapsed time: 16 seconds
572 
selectButton(PAResourceAtoD.CmdMsgTreeDialog_OK, "OK"); // a (e)
573 
dismissDialog("Validate XDC Command"); // e (cj)
574 
// Elapsed time: 10 seconds
575 
selectCheckBox(PAResourceEtoH.GeneratedClockCreationPanel_DO_NOT_OVERRIDE_CLOCKS_ALREADY_DEFINED, "Do not override clocks already defined on the same Source objects (-add)", true); // g (Z, bh): TRUE
576 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bh)
577 
// bs (bh):  Validate XDC Command : addNotify
578 
// bs (cj):  Apply XDC Constraints : addNotify
579 
// TclEventType: SDC_CONSTRAINT_ADD
580 
// Tcl Message: create_generated_clock -name clk_gen -source [get_pins clkgen/clk_in1_p] -divide_by 2 -add -master_clock [get_clocks CLK_IN_P] [get_pins clkgen/clk_out1]
581 
// 'f' command handler elapsed time: 148 seconds
582 
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
583 
dismissDialog("Apply XDC Constraints"); // bs (cj)
584 
// Elapsed time: 16 seconds
585 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (6), Inputs (1), Set Input Delay (1)]", 12, false); // bh (O, cj)
586 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "4 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 5.0 ; [get_ports uart_rx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
587 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "4 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 5.0 ; [get_ports uart_rx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1, false, false, false, false, true); // v (O, cj) - Double Click
588 
// bE (cj): Edit Set Input Delay: addNotify
589 
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT, (String) null); // q (g, bE)
590 
// p (cj): Specify Clock: addNotify
591 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
592 
// bs (p):  Find Names : addNotify
593 
dismissDialog("Find Names"); // bs (p)
594 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
595 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
596 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
597 
dismissDialog("Specify Clock"); // p (cj)
598 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bE)
599 
// bs (bE):  Validate XDC Command : addNotify
600 
dismissDialog("Validate XDC Command"); // bs (bE)
601 
dismissDialog("Edit Set Input Delay"); // bE (cj)
602 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (6), Outputs (1), Set Output Delay (1)]", 14, false); // bh (O, cj)
603 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "5 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 1.0 ; [get_ports uart_tx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
604 
selectButton(PAResourceEtoH.EditIODelayTablePanel_SPECIFY_CLOCK_PIN_OR_PORT_TO_WHICH_OUTPUT, (String) null); // q (g, cj)
605 
// p (cj): Specify Clock: addNotify
606 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
607 
// bs (p):  Find Names : addNotify
608 
dismissDialog("Find Names"); // bs (p)
609 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
610 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
611 
// bs (p):  Find Names : addNotify
612 
dismissDialog("Find Names"); // bs (p)
613 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
614 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
615 
editTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "[get_clocks clk_gen]", 0, "   Clock   ", 1); // v (O, cj)
616 
dismissDialog("Specify Clock"); // p (cj)
617 
selectButton(PAResourceTtoZ.XdcEditorView_APPLY_ALL_CHANGES_TO_XDC_CONSTRAINTS, "Apply"); // a (a, cj)
618 
// bs (cj):  Apply All XDC Constraints : addNotify
619 
// TclEventType: SDC_CONSTR_MGR_CLEAR
620 
// TclEventType: POWER_REPORT_STALE
621 
// TclEventType: SDC_CONSTRAINT_ADD
622 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-2] Deriving generated clocks
623 
// Tcl Message: INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.
624 
// Tcl Message: ERROR: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks clk_gen]'. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
625 
// Tcl Message: INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.
626 
// Tcl Message: ERROR: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks clk_gen]'. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
627 
// TclEventType: SDC_CONSTRAINT_ADD
628 
// cg (cj): Apply All XDC Constraints: addNotify
629 
selectButton(PAResourceAtoD.CmdMsgTreeDialog_OK, "OK"); // a (cg)
630 
dismissDialog("Apply All XDC Constraints"); // cg (cj)
631 
selectButton(PAResourceCommand.PACommandNames_SAVE_DESIGN, "save_design"); // B (f, cj)
632 
// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
633 
// bs (cj):  Save Constraints : addNotify
634 
// TclEventType: DESIGN_STALE
635 
// TclEventType: FILE_SET_CHANGE
636 
// TclEventType: DESIGN_SAVE
637 
// Tcl Message: save_constraints
638 
dismissDialog("Save Constraints"); // bs (cj)
639 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (4), Inputs (0), Set Input Delay (0)]", 12, false); // bh (O, cj)
640 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (4), Inputs (0), Set Input Delay (0)]", 12, false); // bh (O, cj)
641 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (4), Inputs (0), Set Input Delay (0)]", 12, false, false, false, false, false, true); // bh (O, cj) - Double Click
642 
// Run Command: PAResourceCommand.PACommandNames_XDC_SET_INPUT_DELAY
643 
// bY (cj): Set Input Delay: addNotify
644 
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT, (String) null); // q (g, bY)
645 
// p (cj): Specify Clock: addNotify
646 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
647 
// bs (p):  Find Names : addNotify
648 
dismissDialog("Find Names"); // bs (p)
649 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
650 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
651 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
652 
dismissDialog("Specify Clock"); // p (cj)
653 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bY)
654 
// bs (bY):  Validate XDC Command : addNotify
655 
// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-163] Missing value for option 'objects', please type 'set_input_delay -help' for usage info.
656 
// CommandFailedException: null
657 
// Tcl Message: ERROR: [Common 17-163] Missing value for option 'objects', please type 'set_input_delay -help' for usage info.
658 
// e (cj): Validate XDC Command: addNotify
659 
selectButton(PAResourceAtoD.CmdMsgTreeDialog_OK, "OK"); // a (e)
660 
dismissDialog("Validate XDC Command"); // e (cj)
661 
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_LIST_OF_PORTS, (String) null); // q (h, bY)
662 
// p (cj): Specify Delay Objects: addNotify
663 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
664 
// bs (p):  Find Names : addNotify
665 
dismissDialog("Find Names"); // bs (p)
666 
selectList(RDIResource.HDualList_FIND_RESULTS, "uart_rx", 3); // f (c, p)
667 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
668 
selectButton(PAResourceEtoH.GetObjectsPanel_SET, "Set"); // a (p)
669 
dismissDialog("Specify Delay Objects"); // p (cj)
670 
setSpinner(PAResourceItoN.IODelayCreationPanel_DELAY_VALUE, "1.0"); // a (ay, bY)
671 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bY)
672 
// bs (bY):  Validate XDC Command : addNotify
673 
// bs (cj):  Apply XDC Constraints : addNotify
674 
// TclEventType: SDC_CONSTRAINT_ADD
675 
// Tcl Message: set_input_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_rx]
676 
// 'u' command handler elapsed time: 32 seconds
677 
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
678 
dismissDialog("Apply XDC Constraints"); // bs (cj)
679 
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Outputs (0), Set Output Delay (0)]", 14, false); // bh (O, cj)
680 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // v (O, cj)
681 
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0, false, false, false, false, true); // v (O, cj) - Double Click
682 
// Run Command: PAResourceCommand.PACommandNames_XDC_SET_OUTPUT_DELAY
683 
// ce (cj): Set Output Delay: addNotify
684 
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT_TO_WHICH_OUTPUT, (String) null); // q (g, ce)
685 
// p (cj): Specify Clock: addNotify
686 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
687 
// bs (p):  Find Names : addNotify
688 
dismissDialog("Find Names"); // bs (p)
689 
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
690 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
691 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
692 
dismissDialog("Specify Clock"); // p (cj)
693 
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_LIST_OF_PORTS, (String) null); // q (h, ce)
694 
// p (cj): Specify Delay Objects: addNotify
695 
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
696 
// bs (p):  Find Names : addNotify
697 
dismissDialog("Find Names"); // bs (p)
698 
selectList(RDIResource.HDualList_FIND_RESULTS, "uart_tx", 3); // f (c, p)
699 
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
700 
selectButton(PAResourceEtoH.GetObjectsPanel_SET, "Set"); // a (p)
701 
dismissDialog("Specify Delay Objects"); // p (cj)
702 
setSpinner(PAResourceItoN.IODelayCreationPanel_DELAY_VALUE, "1.0"); // a (aW, ce)
703 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (ce)
704 
// bs (ce):  Validate XDC Command : addNotify
705 
// bs (cj):  Apply XDC Constraints : addNotify
706 
// TclEventType: SDC_CONSTRAINT_ADD
707 
// Tcl Message: set_output_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_tx]
708 
// 'A' command handler elapsed time: 22 seconds
709 
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
710 
dismissDialog("Apply XDC Constraints"); // bs (cj)
711 
selectButton(PAResourceCommand.PACommandNames_SAVE_DESIGN, "save_design"); // B (f, cj)
712 
// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
713 
// bs (cj):  Save Constraints : addNotify
714 
// TclEventType: DESIGN_STALE
715 
// TclEventType: FILE_SET_CHANGE
716 
// TclEventType: DESIGN_SAVE
717 
// Tcl Message: save_constraints
718 
dismissDialog("Save Constraints"); // bs (cj)
719 
// Elapsed time: 11 seconds
720 
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
721 
collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
722 
closeView(PAResourceOtoP.PAViews_TIMING_CONSTRAINTS, "Timing Constraints"); // a
723 
// Device view-level: 0.0
724 
closeView(PAResourceOtoP.PAViews_DEVICE, "Device"); // Y
725 
// [GUI Memory]: 210 MB (+2480kb) [01:09:07]
726 
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i (N, cj)
727 
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 4); // B (D, cj)
728 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints]", 3); // B (D, cj)
729 
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1]", 4); // B (D, cj)
730 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, timings.xdc]", 6, false); // B (D, cj)
731 
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, timings.xdc]", 6, false, false, false, false, false, true); // B (D, cj) - Double Click
732 
// Elapsed time: 12 seconds
733 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // u (O, cj)
734 
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Project Manager]", 0); // u (O, cj)
735 
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
736 
// bs (cj):  Resetting Runs : addNotify
737 
// TclEventType: RUN_MODIFY
738 
// TclEventType: RUN_RESET
739 
// TclEventType: DESIGN_STALE
740 
// TclEventType: RUN_RESET
741 
// TclEventType: RUN_MODIFY
742 
// Tcl Message: reset_run synth_1
743 
// bs (cj):  Starting Design Runs : addNotify
744 
// TclEventType: FILESET_TARGET_UCF_CHANGE
745 
// TclEventType: DESIGN_STALE
746 
// TclEventType: RUN_LAUNCH
747 
// TclEventType: RUN_MODIFY
748 
// Tcl Message: launch_runs synth_1 -jobs 16
749 
// Tcl Message: [Thu Jul 30 11:04:30 2020] Launched synth_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
750 
dismissDialog("Starting Design Runs"); // bs (cj)
751 
// TclEventType: DESIGN_STALE
752 
// TclEventType: RUN_COMPLETED
753 
// Elapsed time: 257 seconds
754 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
755 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
756 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
757 
selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aB, cj)
758 
closeTask("Synthesis", "Synthesized Design", "DesignTask.NETLIST_PLANNING");
759 
// x (cj): Confirm Close: addNotify
760 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
761 
// TclEventType: DESIGN_CLOSE
762 
// HMemoryUtils.trashcanNow. Engine heap size: 6,359 MB. GUI used memory: 125 MB. Current time: 7/30/20 11:08:58 AM MSK
763 
// Engine heap size: 6,359 MB. GUI used memory: 126 MB. Current time: 7/30/20 11:08:58 AM MSK
764 
// TclEventType: CURR_DESIGN_SET
765 
// TclEventType: DESIGN_CLOSE
766 
// Tcl Message: close_design
767 
dismissDialog("Confirm Close"); // x (cj)
768 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
769 
// Run Command: PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN
770 
// bs (cj):  Open Synthesized Design : addNotify
771 
// Tcl Message: open_run synth_1 -name synth_1
772 
// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7k325tffg900-2
773 
// TclEventType: READ_XDC_FILE_START
774 
// TclEventType: LOC_CONSTRAINT_ADD
775 
// TclEventType: LOC_CONSTRAINT_REMOVE
776 
// TclEventType: LOC_CONSTRAINT_ADD
777 
// TclEventType: READ_XDC_FILE_END
778 
// TclEventType: READ_XDC_FILE_START
779 
// TclEventType: POWER_CNS_STALE
780 
// TclEventType: POWER_REPORT_STALE
781 
// TclEventType: SDC_CONSTRAINT_ADD
782 
// TclEventType: READ_XDC_FILE_END
783 
// TclEventType: READ_XDC_FILE_START
784 
// TclEventType: READ_XDC_FILE_END
785 
// TclEventType: READ_XDC_FILE_START
786 
// TclEventType: SDC_CONSTRAINT_ADD
787 
// TclEventType: READ_XDC_FILE_END
788 
// TclEventType: READ_XDC_FILE_START
789 
// TclEventType: LOC_CONSTRAINT_REMOVE
790 
// TclEventType: LOC_CONSTRAINT_ADD
791 
// TclEventType: LOC_CONSTRAINT_REMOVE
792 
// TclEventType: LOC_CONSTRAINT_ADD
793 
// TclEventType: SIGNAL_MODIFY
794 
// TclEventType: LOC_CONSTRAINT_ADD
795 
// TclEventType: SIGNAL_MODIFY
796 
// TclEventType: LOC_CONSTRAINT_ADD
797 
// TclEventType: SIGNAL_MODIFY
798 
// TclEventType: LOC_CONSTRAINT_ADD
799 
// TclEventType: SIGNAL_MODIFY
800 
// TclEventType: LOC_CONSTRAINT_ADD
801 
// TclEventType: SIGNAL_MODIFY
802 
// TclEventType: LOC_CONSTRAINT_ADD
803 
// TclEventType: READ_XDC_FILE_END
804 
// TclEventType: READ_XDC_FILE_START
805 
// TclEventType: SDC_CONSTRAINT_ADD
806 
// TclEventType: READ_XDC_FILE_END
807 
// TclEventType: FLOORPLAN_MODIFY
808 
// TclEventType: DESIGN_NEW
809 
// HMemoryUtils.trashcanNow. Engine heap size: 6,359 MB. GUI used memory: 99 MB. Current time: 7/30/20 11:09:05 AM MSK
810 
// TclEventType: DESIGN_NEW
811 
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
812 
// Device: addNotify
813 
// DeviceView Instantiated
814 
// TclEventType: CURR_DESIGN_SET
815 
// Tcl Message: INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen' INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite' INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization
816 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
817 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
818 
// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
819 
// Device view-level: 0.0
820 
// RouteApi: Init Delay Mediator Swing Worker Finished
821 
// 'dO' command handler elapsed time: 5 seconds
822 
dismissDialog("Open Synthesized Design"); // bs (cj)
823 
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
824 
// Elapsed time: 17 seconds
825 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Run Implementation]", 29, false); // u (O, cj)
826 
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
827 
// bs (cj):  Starting Design Runs : addNotify
828 
// TclEventType: FILESET_TARGET_UCF_CHANGE
829 
// Tcl Message: launch_runs impl_1 -jobs 16
830 
// Tcl Message: Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets.
831 
// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 7560.020 ; gain = 0.000 ; free physical = 57675 ; free virtual = 97641
832 
// TclEventType: RUN_LAUNCH
833 
// TclEventType: RUN_MODIFY
834 
// Tcl Message: [Thu Jul 30 11:09:28 2020] Launched impl_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
835 
dismissDialog("Starting Design Runs"); // bs (cj)
836 
// TclEventType: RUN_STEP_COMPLETED
837 
// TclEventType: RUN_COMPLETED
838 
// Elapsed time: 248 seconds
839 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 30, true); // u (O, cj) - Node
840 
// Run Command: PAResourceCommand.PACommandNames_GOTO_IMPLEMENTED_DESIGN
841 
// e (cj): Close Design: addNotify
842 
selectButton(PAResourceAtoD.ClosePlanner_YES, "Yes"); // a (e)
843 
// TclEventType: DESIGN_CLOSE
844 
// HMemoryUtils.trashcanNow. Engine heap size: 6,374 MB. GUI used memory: 127 MB. Current time: 7/30/20 11:13:43 AM MSK
845 
// Engine heap size: 6,374 MB. GUI used memory: 128 MB. Current time: 7/30/20 11:13:43 AM MSK
846 
// TclEventType: CURR_DESIGN_SET
847 
// TclEventType: DESIGN_CLOSE
848 
// bs (cj):  Open Implemented Design : addNotify
849 
// Tcl Message: close_design
850 
dismissDialog("Close Design"); // e (cj)
851 
// Tcl Message: open_run impl_1
852 
// TclEventType: READ_XDC_FILE_START
853 
// TclEventType: LOC_CONSTRAINT_ADD
854 
// TclEventType: SIGNAL_MODIFY
855 
// TclEventType: LOC_CONSTRAINT_REMOVE
856 
// TclEventType: LOC_CONSTRAINT_ADD
857 
// TclEventType: SIGNAL_MODIFY
858 
// TclEventType: READ_XDC_FILE_END
859 
// TclEventType: READ_XDC_FILE_START
860 
// TclEventType: POWER_CNS_STALE
861 
// TclEventType: POWER_REPORT_STALE
862 
// TclEventType: SDC_CONSTRAINT_ADD
863 
// TclEventType: LOC_CONSTRAINT_REMOVE
864 
// TclEventType: LOC_CONSTRAINT_ADD
865 
// TclEventType: LOC_CONSTRAINT_REMOVE
866 
// TclEventType: LOC_CONSTRAINT_ADD
867 
// TclEventType: SIGNAL_MODIFY
868 
// TclEventType: LOC_CONSTRAINT_ADD
869 
// TclEventType: SIGNAL_MODIFY
870 
// TclEventType: LOC_CONSTRAINT_ADD
871 
// TclEventType: SIGNAL_MODIFY
872 
// TclEventType: LOC_CONSTRAINT_ADD
873 
// TclEventType: SIGNAL_MODIFY
874 
// TclEventType: LOC_CONSTRAINT_ADD
875 
// TclEventType: SIGNAL_MODIFY
876 
// TclEventType: LOC_CONSTRAINT_ADD
877 
// TclEventType: SDC_CONSTRAINT_ADD
878 
// TclEventType: READ_XDC_FILE_END
879 
// TclEventType: DESIGN_NEW
880 
// HMemoryUtils.trashcanNow. Engine heap size: 6,369 MB. GUI used memory: 101 MB. Current time: 7/30/20 11:13:46 AM MSK
881 
// TclEventType: DESIGN_NEW
882 
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
883 
// Device: addNotify
884 
// DeviceView Instantiated
885 
// TclEventType: CURR_DESIGN_SET
886 
// Tcl Message: INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization
887 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_board.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_board.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_early.xdc]
888 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
889 
// Tcl Message: Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_early.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing.
890 
// Tcl Message: Read XDEF File: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 7560.020 ; gain = 0.000 ; free physical = 57677 ; free virtual = 97659
891 
// Tcl Message: Restored from archive | CPU: 0.250000 secs | Memory: 4.245201 MB |
892 
// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 7560.020 ; gain = 0.000 ; free physical = 57677 ; free virtual = 97659
893 
// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
894 
// TclEventType: DRC_ADDED
895 
// Device view-level: 0.0
896 
// RouteApi: Init Delay Mediator Swing Worker Finished
897 
// TclEventType: DRC_ADDED
898 
// TclEventType: METHODOLOGY_ADDED
899 
// TclEventType: POWER_UPDATED
900 
// TclEventType: TIMING_SUMMARY_UPDATED
901 
// 'dO' command handler elapsed time: 13 seconds
902 
dismissDialog("Open Implemented Design"); // bs (cj)
903 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 33, false); // u (O, cj)
904 
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
905 
// aF (cj): Report Timing Summary: addNotify
906 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (aF)
907 
dismissDialog("Report Timing Summary"); // aF (cj)
908 
// bs (cj):  Report Timing Summary : addNotify
909 
// TclEventType: TIMING_RESULTS_STALE
910 
// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
911 
// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
912 
// TclEventType: TIMING_SUMMARY_UPDATED
913 
dismissDialog("Report Timing Summary"); // bs (cj)
914 
// Elapsed time: 21 seconds
915 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 5); // a (O, cj)
916 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Check Timing]", 4); // a (O, cj)
917 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 20); // a (O, cj)
918 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19); // a (O, cj)
919 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Setup 3.098 ns]", 20, false); // a (O, cj)
920 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Hold 0.094 ns]", 21, false); // a (O, cj)
921 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Pulse Width 8.592 ns]", 24, false); // a (O, cj)
922 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clkfbout_clk_gen]", 25); // a (O, cj)
923 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Setup 3.098 ns]", 20, false); // a (O, cj)
924 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Hold 0.094 ns]", 21, false); // a (O, cj)
925 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19, true); // a (O, cj) - Node
926 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 17, true); // a (O, cj) - Node
927 
selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aF (Q, cj)
928 
// Tcl Command: 'rdi::info_commands {w*}'
929 
// Tcl Command: 'rdi::info_commands {wr*}'
930 
// Tcl Command: 'rdi::info_commands {wri*}'
931 
// Tcl Command: 'rdi::info_commands {write*}'
932 
// Tcl Command: 'rdi::info_commands {write_*}'
933 
// Tcl Command: 'rdi::info_commands {write_v*}'
934 
// Elapsed time: 11 seconds
935 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_v", true); // aF (ae, cj)
936 
// Tcl Command: 'rdi::match_options {write_verilog} {}'
937 
// Tcl Command: 'rdi::match_options {write_verilog} {fo}'
938 
// Tcl Command: 'rdi::match_options {write_verilog} {for}'
939 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -for", true); // aF (ae, cj)
940 
// Tcl Command: 'rdi::match_options {write_verilog} {}'
941 
// Tcl Command: 'rdi::match_options {write_verilog} {m}'
942 
// Tcl Command: 'rdi::match_options {write_verilog} {mo}'
943 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mo", true); // aF (ae, cj)
944 
// Tcl Command: 'rdi::info_commands bd::match_path'
945 
// Tcl Command: 'rdi::info_commands bd::match_path'
946 
// Tcl Command: 'rdi::info_commands bd::match_path'
947 
// Tcl Command: 'rdi::info_commands bd::match_path'
948 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./net", true); // aF (ae, cj)
949 
// Tcl Command: 'rdi::info_commands bd::match_path'
950 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/", true); // aF (ae, cj)
951 
applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v"); // aF (ae, cj)
952 
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
953 
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
954 
// Tcl Message: write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v
955 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.v
956 
// HMemoryUtils.trashcanNow. Engine heap size: 6,376 MB. GUI used memory: 158 MB. Current time: 7/30/20 11:15:32 AM MSK
957 
// Tcl Command: 'rdi::info_commands {write_*}'
958 
// Tcl Command: 'rdi::info_commands {write_*}'
959 
// Tcl Command: 'rdi::info_commands {write_s*}'
960 
// Tcl Command: 'rdi::info_commands {write_sd*}'
961 
// Elapsed time: 16 seconds
962 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sd -force -mode timesim ./netlist/aes128_ecb_wrap.v", true); // aF (ae, cj)
963 
// Tcl Command: 'rdi::info_commands bd::match_path'
964 
// Tcl Command: 'rdi::info_commands bd::match_path'
965 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.s", true); // aF (ae, cj)
966 
applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf"); // aF (ae, cj)
967 
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
968 
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
969 
// Tcl Message: write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf
970 
// bs (cj):  Tcl Command Line : addNotify
971 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.sdf
972 
dismissDialog("Tcl Command Line"); // bs (cj)
973 
// TclEventType: DG_GRAPH_STALE
974 
// TclEventType: FILE_SET_CHANGE
975 
// TclEventType: DG_ANALYSIS_MSG_RESET
976 
// TclEventType: DG_GRAPH_GENERATED
977 
// TclEventType: DG_GRAPH_STALE
978 
// TclEventType: FILE_SET_CHANGE
979 
// TclEventType: DG_ANALYSIS_MSG_RESET
980 
// TclEventType: DG_GRAPH_GENERATED
981 
// TclEventType: DG_GRAPH_STALE
982 
// TclEventType: FILE_SET_CHANGE
983 
// TclEventType: DG_ANALYSIS_MSG_RESET
984 
// TclEventType: DG_GRAPH_GENERATED
985 
// TclEventType: DG_GRAPH_STALE
986 
// TclEventType: FILE_SET_CHANGE
987 
// TclEventType: DG_ANALYSIS_MSG_RESET
988 
// HMemoryUtils.trashcanNow. Engine heap size: 6,431 MB. GUI used memory: 156 MB. Current time: 7/30/20 11:42:59 AM MSK
989 
// TclEventType: DG_GRAPH_GENERATED
990 
// Elapsed time: 1836 seconds
991 
selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aB, cj)
992 
closeTask("Implementation", "Implemented Design", "DesignTask.RESULTS_ANALYSIS");
993 
// x (cj): Confirm Close: addNotify
994 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
995 
// TclEventType: DESIGN_CLOSE
996 
// HMemoryUtils.trashcanNow. Engine heap size: 6,431 MB. GUI used memory: 130 MB. Current time: 7/30/20 11:46:39 AM MSK
997 
// TclEventType: TIMING_RESULTS_UNLOAD
998 
// Engine heap size: 6,431 MB. GUI used memory: 131 MB. Current time: 7/30/20 11:46:39 AM MSK
999 
// TclEventType: CURR_DESIGN_SET
1000 
// TclEventType: DESIGN_CLOSE
1001 
// Tcl Message: close_design
1002 
dismissDialog("Confirm Close"); // x (cj)
1003 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Run Implementation]", 28, false); // u (O, cj)
1004 
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
1005 
// bs (cj):  Resetting Runs : addNotify
1006 
// TclEventType: RUN_MODIFY
1007 
// TclEventType: RUN_RESET
1008 
// TclEventType: RUN_MODIFY
1009 
// Tcl Message: reset_run synth_1
1010 
// bs (cj):  Starting Design Runs : addNotify
1011 
// TclEventType: FILESET_TARGET_UCF_CHANGE
1012 
// TclEventType: RUN_LAUNCH
1013 
// TclEventType: FILESET_TARGET_UCF_CHANGE
1014 
// TclEventType: RUN_LAUNCH
1015 
// TclEventType: RUN_MODIFY
1016 
// Tcl Message: launch_runs impl_1 -jobs 16
1017 
// Tcl Message: [Thu Jul 30 11:46:45 2020] Launched synth_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log [Thu Jul 30 11:46:45 2020] Launched impl_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
1018 
dismissDialog("Starting Design Runs"); // bs (cj)
1019 
// TclEventType: RUN_COMPLETED
1020 
// TclEventType: RUN_STEP_COMPLETED
1021 
// TclEventType: RUN_COMPLETED
1022 
// Elapsed time: 407 seconds
1023 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 29, true); // u (O, cj) - Node
1024 
// Run Command: PAResourceCommand.PACommandNames_GOTO_IMPLEMENTED_DESIGN
1025 
// bs (cj):  Open Implemented Design : addNotify
1026 
// Tcl Message: open_run impl_1
1027 
// TclEventType: READ_XDC_FILE_START
1028 
// TclEventType: LOC_CONSTRAINT_ADD
1029 
// TclEventType: SIGNAL_MODIFY
1030 
// TclEventType: LOC_CONSTRAINT_REMOVE
1031 
// TclEventType: LOC_CONSTRAINT_ADD
1032 
// TclEventType: SIGNAL_MODIFY
1033 
// TclEventType: READ_XDC_FILE_END
1034 
// TclEventType: READ_XDC_FILE_START
1035 
// TclEventType: POWER_CNS_STALE
1036 
// TclEventType: POWER_REPORT_STALE
1037 
// TclEventType: SDC_CONSTRAINT_ADD
1038 
// TclEventType: LOC_CONSTRAINT_REMOVE
1039 
// TclEventType: LOC_CONSTRAINT_ADD
1040 
// TclEventType: LOC_CONSTRAINT_REMOVE
1041 
// TclEventType: LOC_CONSTRAINT_ADD
1042 
// TclEventType: SIGNAL_MODIFY
1043 
// TclEventType: LOC_CONSTRAINT_ADD
1044 
// TclEventType: SIGNAL_MODIFY
1045 
// TclEventType: LOC_CONSTRAINT_ADD
1046 
// TclEventType: SIGNAL_MODIFY
1047 
// TclEventType: LOC_CONSTRAINT_ADD
1048 
// TclEventType: SIGNAL_MODIFY
1049 
// TclEventType: LOC_CONSTRAINT_ADD
1050 
// TclEventType: SIGNAL_MODIFY
1051 
// TclEventType: LOC_CONSTRAINT_ADD
1052 
// TclEventType: SDC_CONSTRAINT_ADD
1053 
// TclEventType: READ_XDC_FILE_END
1054 
// TclEventType: DESIGN_NEW
1055 
// HMemoryUtils.trashcanNow. Engine heap size: 6,436 MB. GUI used memory: 104 MB. Current time: 7/30/20 11:53:37 AM MSK
1056 
// TclEventType: DESIGN_NEW
1057 
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
1058 
// Device: addNotify
1059 
// DeviceView Instantiated
1060 
// TclEventType: CURR_DESIGN_SET
1061 
// Tcl Message: INFO: [Netlist 29-17] Analyzing 920 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization
1062 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_board.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_board.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_early.xdc]
1063 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
1064 
// Tcl Message: Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_early.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing.
1065 
// Tcl Message: Read XDEF File: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 7605.039 ; gain = 0.000 ; free physical = 57798 ; free virtual = 97758
1066 
// Tcl Message: Restored from archive | CPU: 0.260000 secs | Memory: 4.378311 MB |
1067 
// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 7605.039 ; gain = 0.000 ; free physical = 57798 ; free virtual = 97758
1068 
// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
1069 
// Device view-level: 0.0
1070 
// TclEventType: DRC_ADDED
1071 
// RouteApi: Init Delay Mediator Swing Worker Finished
1072 
// TclEventType: DRC_ADDED
1073 
// TclEventType: METHODOLOGY_ADDED
1074 
// TclEventType: POWER_UPDATED
1075 
// TclEventType: TIMING_SUMMARY_UPDATED
1076 
// 'dO' command handler elapsed time: 7 seconds
1077 
dismissDialog("Open Implemented Design"); // bs (cj)
1078 
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 33, false); // u (O, cj)
1079 
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
1080 
// aF (cj): Report Timing Summary: addNotify
1081 
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (aF)
1082 
// [GUI Memory]: 222 MB (+1711kb) [01:58:50]
1083 
dismissDialog("Report Timing Summary"); // aF (cj)
1084 
// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
1085 
// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
1086 
// TclEventType: TIMING_RESULTS_STALE
1087 
// bs (cj):  Report Timing Summary : addNotify
1088 
// TclEventType: TIMING_SUMMARY_UPDATED
1089 
dismissDialog("Report Timing Summary"); // bs (cj)
1090 
// [GUI Memory]: 238 MB (+4100kb) [01:59:00]
1091 
// Elapsed time: 10 seconds
1092 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Check Timing]", 4); // a (O, cj)
1093 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 17); // a (O, cj)
1094 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19); // a (O, cj)
1095 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Setup 2.583 ns]", 20, false); // a (O, cj)
1096 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Hold 0.085 ns]", 21, false); // a (O, cj)
1097 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Pulse Width 4.358 ns]", 22, false); // a (O, cj)
1098 
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19, true); // a (O, cj) - Node
1099 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 23); // a (O, cj)
1100 
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clkfbout_clk_gen]", 25); // a (O, cj)
1101 
selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aF (Q, cj)
1102 
// Elapsed time: 13 seconds
1103 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v", true); // aF (ae, cj)
1104 
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
1105 
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
1106 
// Tcl Message: write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v
1107 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.v
1108 
// HMemoryUtils.trashcanNow. Engine heap size: 6,456 MB. GUI used memory: 160 MB. Current time: 7/30/20 11:54:46 AM MSK
1109 
// Elapsed time: 16 seconds
1110 
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf", true); // aF (ae, cj)
1111 
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
1112 
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
1113 
// Tcl Message: write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf
1114 
// bs (cj):  Tcl Command Line : addNotify
1115 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.sdf
1116 
dismissDialog("Tcl Command Line"); // bs (cj)

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