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URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [sim/] [fpga_wrap_files_rtl.lst] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
+INCDIR+$UNIT_HOME/rtl/aes128/src
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$UNIT_HOME/src/aes128_enc.sv
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$UNIT_HOME/src/wrap/axi_interface.sv
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$UNIT_HOME/src/wrap/system_manager.sv
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-f $XILINX_VIVADO//data/secureip/secureip_cell.list.f
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-y $XILINX_VIVADO/data/verilog/src/unisims +libext+.v
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-y $XILINX_VIVADO/data/verilog/src/unimacro +libext+.v
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-y $XILINX_VIVADO/data/verilog/src/retarget +libext+.v
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+INCDIR+$XILINX_VIVADO/data/verilog/src/unisims_dr
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$XILINX_VIVADO/data/verilog/src/glbl.v
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$UNIT_HOME/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.v
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$UNIT_HOME/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_sim_netlist.v
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$UNIT_HOME/src/wrap/aes128_ecb_fpga_wrap.sv
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$UNIT_HOME/tb/tb_fpga.sv
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