URL
https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk
[/] [aes-128-ecb-encoder/] [trunk/] [sim/] [fpga_wrap_files_translate.lst] - Blame information for rev 2
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
vv_gulyaev |
$UNIT_HOME/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v
|
2 |
|
|
|
3 |
|
|
-f $XILINX_VIVADO//data/secureip/secureip_cell.list.f
|
4 |
|
|
-y $XILINX_VIVADO/data/verilog/src/unisims +libext+.v
|
5 |
|
|
#-y $XILINX_VIVADO/data/verilog/src/unimacro +libext+.v
|
6 |
|
|
#-y $XILINX_VIVADO/data/verilog/src/retarget +libext+.v
|
7 |
|
|
#+INCDIR+$XILINX_VIVADO/data/verilog/src/unisims_dr
|
8 |
|
|
#$XILINX_VIVADO/data/verilog/src/glbl.v
|
9 |
|
|
|
10 |
|
|
#$UNIT_HOME/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.v
|
11 |
|
|
$UNIT_HOME/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim_sim_netlist.v
|
12 |
|
|
$UNIT_HOME/src/wrap/axi_interface.sv
|
13 |
|
|
$UNIT_HOME/tb/tb_fpga.sv
|
14 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.