OpenCores
URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [sim/] [run_sim_fpga_wrap_translate] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 vv_gulyaev
#!/bin/csh
2
 
3
setenv TOP_DESIGN ./..
4
# -- Set current directory for unit
5
setenv CURR_DIR $PWD
6
cd ../
7
setenv UNIT_HOME $PWD
8
cd $CURR_DIR
9
 
10
rm -rf ./XRUN_rtl_libs/
11
source $UNIT_HOME/tb/vipcat_env_xrun64.csh
12
 
13
setenv XILINX_VIVADO /opt/xilinx/Vivado2017/Vivado/2017.4/
14
 
15
setenv SDF_PATH      $UNIT_HOME/fpga/aes128_ecb/netlist/aes128_ecb_wrap.sdf
16
setenv SDF_PATH_UART $UNIT_HOME/fpga/aes128_ecb/netlist/uartlite.sdf
17
 
18
xrun \
19
+gui \
20
+libverbose \
21
+xmaccess+rwc\
22
-64bit\
23
-sv \
24
-uvm \
25
-smartorder \
26
-LOGfile xrun_fpga_tb.log \
27
-incdir ${TOP_DESIGN}/tb\
28
-define SDF_PATH='"'${SDF_PATH}'"'\
29
-define SDF_PATH_UART='"'${SDF_PATH_UART}'"'\
30
-top tb_fpga \
31
-top glbl \
32
+xmtimescale+1ps/1ps \
33
-xmlibdirname XRUN_fpga_wrap_translate_libs \
34
-f ../sim/fpga_wrap_files_translate.lst
35
 
36
#-loadvpi $UNIT_HOME/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver/inca.lnx8664.043.pak \

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.