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[/] [aes-128-ecb-encoder/] [trunk/] [src/] [wrap/] [system_manager.sv] - Blame information for rev 2

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/**
 *  Module system_manager.
 *    Functions:
 *        - Receive data(key and plainText) and commands from Xilinx IP UARTLITE
 *        - Send recieved data to aes-128-ecb encoder
 *        - Receive ciphered data from encoder
 *        - Send ciphered data to UARTLITE
 *
 *  Copyright 2020 by Vyacheslav Gulyaev 
 *
 *  Licensed under GNU General Public License 3.0 or later.
 *  Some rights reserved. See COPYING, AUTHORS.
 *
 * @license GPL-3.0+ 
 */
 
module system_manager(
                        input           clk_i,
                        input           rstn_i,
 
                        output logic  [127:0]   plain_text_data_o,
                        output logic            plain_text_data_valid_o,
                        output logic  [127:0]   key_o,
 
                        input         [127:0]   cipher_data_i,
                        input                   cipher_data_valid_i,
 
                        output logic            key_set_complete_o,
                        output logic            startup_pause_complete,
 
 
                        input                   interrupt_i,
 
                        axi_interface.master    m_axi
                   );
 
    `define __UART_DEFINES__
 
    `define CMD_SET_KEY    8'hF0
    `define CMD_ENC_DATA   8'hE1
    `define CMD_GET_STAT   8'hD2
 
    `define RxFIFO_ADDR    4'h0
    `define TxFIFO_ADDR    4'h4
    `define STAT_REG_ADDR  4'h8
    `define CTRL_REG_ADDR  4'hC
 
    `define STAT_REG_RxFifoValidDataBit        0
    `define STAT_REG_RxFifoFullBit             1
    `define STAT_REG_TxFifoEmptyBit            2
    `define STAT_REG_TxFifoFullBit             3
    `define STAT_REG_IntrEnabledBit            4
    `define STAT_REG_OverrunErrorBit           5
    `define STAT_REG_FrameErrorBit             6
    `define STAT_REG_ParityErrorBit            7
 
    `define CTRL_REG_RstTxFifoBit              0
    `define CTRL_REG_RstRxFifoBit              1
    `define CTRL_REG_EnableIntrBit             4
 
    `define AXI_RESP_OKAY                      2'b00
    `define AXI_RESP_EXOKAY                    2'b01
    `define AXI_RESP_SLVERR                    2'b10
    `define AXI_RESP_DECERR                    2'b11
 
    localparam STARTUP_PAUSE_DUTY =            100; //1us = 100 * 10ns(100MHz)
 
    logic          start_axi_wr;
    logic          start_axi_wr_reg;
    logic  [7:0]   axi_data_wr;
    logic  [7:0]   axi_data_wr_reg;
    logic  [3:0]   addr;
    logic  [3:0]   addr_reg;
    logic          start_axi_rd;
    logic          start_axi_rd_reg;
    logic          uart_init_complete;
    logic          uart_init_complete_reg;
    logic  [7:0]   rd_data;
    logic  [7:0]   rd_data_reg;
    logic          rx_fifo_valid_data;
    logic          rx_fifo_full;
    logic          tx_fifo_empty;
    logic          tx_fifo_full;
    logic          rx_fifo_valid_data_reg;
    logic          rx_fifo_full_reg;
    logic          tx_fifo_empty_reg;
    logic          tx_fifo_full_reg;
    logic          check_stat;
    logic          check_stat_reg;
    logic          key_set_complete;
    logic          key_set_complete_reg;
    logic          key_set_in_progress;
    logic          key_set_in_progress_reg;
    logic          plain_text_set_in_progress;
    logic          plain_text_set_in_progress_reg;
    logic  [3:0]   data_counter;
    logic  [3:0]   data_counter_reg;
    logic  [127:0] plain_text_data;
    logic          plain_text_data_valid;
    logic  [127:0] key;
 
    logic  [127:0] cipher_data;
    logic  [127:0] cipher_data_reg;
    logic          transmit_in_progress;
    logic          transmit_in_progress_reg;
    logic          wait_tx_fifo_empty;
    logic          wait_tx_fifo_empty_reg;
    logic          get_stat;
    logic          get_stat_reg;
    logic  [7:0]   cur_stat;
    logic  [7:0]   cur_stat_reg;
    logic          send_stat;
    logic          send_stat_reg;
 
    logic [31:0]  startup_pause_cnt;
//    logic         startup_pause_complete;
 
    typedef enum {  SYS_IDLE,
                    INIT_UART_CTRL_REG,
                    RD_UART_STAT_REG,
                    RD_RX_FIFO,
                    WR_TX_FIFO
                } sys_state_t;
    sys_state_t sys_state;
    sys_state_t sys_next_state;
 
 
    //write address channel
    logic  [3:0]   m_axi_awaddr;
    logic          m_axi_awvalid;
 
    //write data channel
    logic  [7:0]   m_axi_wdata;
    logic  [3:0]   m_axi_wstrb;
    logic          m_axi_wvalid;
 
    //write response channel
    logic          m_axi_bready;
 
    //read address channel
    logic  [3:0]   m_axi_araddr;
    logic          m_axi_arvalid;
 
    //read data channel
    logic          m_axi_rready;
 
    wire         axi_wr_ok;
    wire         axi_rd_ok;
 
    typedef enum {  AXI_IDLE,
                    AXI_WAIT_WREADY,
                    AXI_WAIT_BRESP,
                    AXI_WAIT_RREADY,
                    AXI_WAIT_RDATA
                  } axi_state_t;
    axi_state_t axi_state;
    axi_state_t axi_next_state;
 
    always @(posedge clk_i or negedge rstn_i) begin
        if (!rstn_i) begin
            startup_pause_cnt <= 32'h0;
        end else if (~startup_pause_complete) begin
            startup_pause_cnt <= startup_pause_cnt + 1;
        end
    end
    assign startup_pause_complete = (startup_pause_cnt==STARTUP_PAUSE_DUTY) ? 1'b1 : 1'b0;
 
 
    //sys manager registering
    always @(posedge clk_i or negedge rstn_i) begin
        if (~rstn_i) begin
            start_axi_wr_reg <= 1'b0;
            axi_data_wr_reg  <= 8'h0;
            addr_reg <= 4'h0;
            start_axi_rd_reg <= 1'b0;
            uart_init_complete_reg <= 1'b0;
            rd_data_reg <= 8'h0;
            rx_fifo_valid_data_reg <= 1'b0;
            rx_fifo_full_reg <= 1'b0;
            tx_fifo_empty_reg <= 1'b0;
            tx_fifo_full_reg <= 1'b0;
            check_stat_reg <= 1'b0;
            key_set_complete_reg <= 1'b0;
            key_set_in_progress_reg <= 1'b0;
            plain_text_set_in_progress_reg <= 1'b0;
            data_counter_reg <= 4'h0;
            plain_text_data_o <= 128'h0;
            plain_text_data_valid_o <= 1'b0;
            key_o <= 128'h0;
            cipher_data_reg <= 128'h0;
            transmit_in_progress_reg <= 1'b0;
            wait_tx_fifo_empty_reg <= 1'b0;
            get_stat_reg <= 1'b0;
            cur_stat_reg <= 8'h0;
            send_stat_reg <= 1'b0;
 
            sys_state <= SYS_IDLE;
        end else begin
            start_axi_wr_reg <= start_axi_wr;
            axi_data_wr_reg  <= axi_data_wr;
            addr_reg <= addr;
            start_axi_rd_reg <= start_axi_rd;
            uart_init_complete_reg <= uart_init_complete;
            rd_data_reg <= rd_data;
            rx_fifo_valid_data_reg <= rx_fifo_valid_data;
            rx_fifo_full_reg <= rx_fifo_full;
            tx_fifo_empty_reg <= tx_fifo_empty;
            tx_fifo_full_reg <= tx_fifo_full;
            check_stat_reg <= check_stat;
            key_set_complete_reg <= key_set_complete;
            key_set_in_progress_reg <= key_set_in_progress;
            plain_text_set_in_progress_reg <= plain_text_set_in_progress;
            data_counter_reg <= data_counter;
            plain_text_data_o <= plain_text_data;
            plain_text_data_valid_o <= plain_text_data_valid;
            key_o <= key;
            cipher_data_reg <= cipher_data;
            transmit_in_progress_reg <= transmit_in_progress;
            wait_tx_fifo_empty_reg <= wait_tx_fifo_empty;
            get_stat_reg <= get_stat;
            cur_stat_reg <= cur_stat;
            send_stat_reg <= send_stat;
 
            sys_state <= sys_next_state;
        end
    end
 
    //sys manager state handling
    always @(*) begin
        sys_next_state = sys_state;
        case (sys_state)
            SYS_IDLE: begin
                if (~uart_init_complete_reg & startup_pause_complete) begin
                    sys_next_state = INIT_UART_CTRL_REG;
                end else if (interrupt_i | check_stat_reg | get_stat_reg) begin
                    sys_next_state = RD_UART_STAT_REG;
                end else if (rx_fifo_valid_data_reg) begin
                    sys_next_state = RD_RX_FIFO;
                end else if (cipher_data_valid_i | transmit_in_progress_reg | send_stat_reg) begin
                    sys_next_state = WR_TX_FIFO;
                end
            end
 
            INIT_UART_CTRL_REG, WR_TX_FIFO: begin
                if (axi_wr_ok) begin
                    sys_next_state = SYS_IDLE;
                end
            end
 
            RD_UART_STAT_REG, RD_RX_FIFO: begin
                if (axi_rd_ok) begin
                    sys_next_state = SYS_IDLE;
                end
            end
        endcase
    end
 
    //sys manager fsm
    always @(*) begin
        start_axi_wr = start_axi_wr_reg;
        axi_data_wr = axi_data_wr_reg;
        addr = addr_reg;
        start_axi_rd = start_axi_rd_reg;
        uart_init_complete = uart_init_complete_reg;
        rd_data = rd_data_reg;
        rx_fifo_valid_data = rx_fifo_valid_data_reg;
        rx_fifo_full = rx_fifo_full_reg;
        tx_fifo_empty = tx_fifo_empty_reg;
        tx_fifo_full = tx_fifo_full_reg;
        check_stat = check_stat_reg;
        key_set_complete = key_set_complete_reg;
        key_set_in_progress = key_set_in_progress_reg;
        plain_text_set_in_progress = plain_text_set_in_progress_reg;
        data_counter = data_counter_reg;
        plain_text_data = plain_text_set_in_progress_reg ? plain_text_data_o : 128'h0;
        plain_text_data_valid = 1'b0;
        key = key_o;
        cipher_data = cipher_data_reg;
        transmit_in_progress = transmit_in_progress_reg;
        wait_tx_fifo_empty = wait_tx_fifo_empty_reg;
        get_stat = get_stat_reg;
        cur_stat = cur_stat_reg;
        send_stat = send_stat_reg;
 
        case (sys_state)
            SYS_IDLE: begin
                if (~uart_init_complete_reg & startup_pause_complete) begin
                    start_axi_wr = 1'b1;
                    axi_data_wr[`CTRL_REG_RstTxFifoBit] = 1'b1;
                    axi_data_wr[`CTRL_REG_RstRxFifoBit] = 1'b1;
                    axi_data_wr[`CTRL_REG_EnableIntrBit] = 1'b1;
                    addr = `CTRL_REG_ADDR;
                end else if (interrupt_i | check_stat_reg | get_stat_reg) begin
                    start_axi_rd = 1'b1;
                    addr = `STAT_REG_ADDR;
                end else if (rx_fifo_valid_data_reg & ~wait_tx_fifo_empty_reg) begin
                    start_axi_rd = 1'b1;
                    addr = `RxFIFO_ADDR;
                end else if (cipher_data_valid_i) begin
                    start_axi_wr = 1'b1;
                    axi_data_wr[7:0] = cipher_data_i[127:120];
                    addr = `TxFIFO_ADDR;
                    cipher_data[127:0] = cipher_data_i[127:0];
                    transmit_in_progress <= 1'b1;
                end else if (transmit_in_progress_reg) begin
                    start_axi_wr = 1'b1;
                    axi_data_wr[7:0] = cipher_data_reg[127:120];
                    addr = `TxFIFO_ADDR;
                end else if (send_stat_reg) begin
                    start_axi_wr = 1'b1;
                    axi_data_wr[7:0] = cur_stat;
                    addr = `TxFIFO_ADDR;
                end
            end
 
            INIT_UART_CTRL_REG: begin
                start_axi_wr = 1'b0;
                axi_data_wr = 8'h0;
                addr = 4'h0;
                if (axi_wr_ok) begin
                    uart_init_complete = 1'b1;
                end
            end
 
            RD_UART_STAT_REG: begin
                start_axi_rd = 1'b0;
                addr = 4'h0;
                check_stat = 1'b0;
                if (axi_rd_ok) begin
                    rx_fifo_valid_data = m_axi.rdata[`STAT_REG_RxFifoValidDataBit];
                    rx_fifo_full = m_axi.rdata[`STAT_REG_RxFifoFullBit];
                    tx_fifo_empty = m_axi.rdata[`STAT_REG_TxFifoEmptyBit];
                    tx_fifo_full = m_axi.rdata[`STAT_REG_TxFifoFullBit];
                    if (wait_tx_fifo_empty_reg) begin
                        wait_tx_fifo_empty = tx_fifo_empty ? 1'b0 : 1'b1;
                    end
                    cur_stat = m_axi.rdata[7:0];
                    if (get_stat_reg) begin
                        get_stat = 1'b0;
                        send_stat = 1'b1;
                    end
                end
            end
 
            RD_RX_FIFO: begin
                start_axi_rd = 1'b0;
                addr = 4'h0;
                check_stat = 1'b1;
                if (axi_rd_ok) begin
                    rd_data = m_axi.rdata[7:0];
                    if (~key_set_in_progress_reg & ~plain_text_set_in_progress_reg) begin
                        case (rd_data)
                            `CMD_SET_KEY: begin
                                key_set_complete = 1'b0;
                                key_set_in_progress = 1'b1;
                                data_counter = 4'h0;
                                key = 128'h0;
                            end
                            `CMD_ENC_DATA: begin
                                plain_text_set_in_progress = 1'b1;
                                data_counter = 4'h0;
                                plain_text_data = 128'h0;
                            end
                            `CMD_GET_STAT: begin
                                get_stat = 1'b1;
                            end
                        endcase
                    end else if (key_set_in_progress_reg) begin
                        key[127:0] = {key_o[120:0], rd_data};
                        if (data_counter==4'hF) begin
                            key_set_in_progress = 1'b0;
                            key_set_complete = 1'b1;
                            data_counter = 4'h0;
                        end else begin
                            data_counter = data_counter + 1;
                        end
                    end else if (plain_text_set_in_progress_reg) begin
                        plain_text_data[127:0] = {plain_text_data_o[120:0], rd_data};
                        if (data_counter==4'hF) begin
                            plain_text_set_in_progress = 1'b0;
                            plain_text_data_valid = 1'b1;
                            data_counter = 4'h0;
                        end else begin
                            data_counter = data_counter + 1;
                        end
                    end
                end
            end
 
            WR_TX_FIFO: begin
                start_axi_wr = 1'b0;
                axi_data_wr = 8'h0;
                addr = 4'h0;
                if (axi_wr_ok) begin
                    if (send_stat_reg) begin
                        send_stat = 1'b0;
                    end else if (data_counter==4'hF) begin
                        transmit_in_progress = 1'b0;
                        data_counter = 4'h0;
                        wait_tx_fifo_empty = 1'b1;
                    end else begin
                        cipher_data[127:0] = {cipher_data_reg[120:0], 8'h0};
                        data_counter = data_counter + 1;
                    end
                end
            end
 
        endcase
    end
 
    //axi-lite registering
    always @(posedge clk_i or negedge rstn_i) begin
        if (~rstn_i) begin
            m_axi.awaddr  <= 4'h0;
            m_axi.awvalid <= 1'b0;
            m_axi.wdata   <= 32'h0;
            m_axi.wstrb   <= 4'h0;
            m_axi.wvalid  <= 1'b0;
            m_axi.bready  <= 1'b0;
            m_axi.araddr  <= 4'h0;
            m_axi.arvalid <= 1'b0;
            m_axi.rready  <= 1'b0;
 
            axi_state <= axi_next_state;
        end else begin
            m_axi.awaddr  <= m_axi_awaddr;
            m_axi.awvalid <= m_axi_awvalid;
            m_axi.wdata   <= m_axi_wdata;
            m_axi.wstrb   <= m_axi_wstrb;
            m_axi.wvalid  <= m_axi_wvalid;
            m_axi.bready  <= m_axi_bready;
            m_axi.araddr  <= m_axi_araddr;
            m_axi.arvalid <= m_axi_arvalid;
            m_axi.rready  <= m_axi_rready;
 
            axi_state <= axi_next_state;
        end
    end
 
 
    assign axi_wr_ok = (m_axi.bvalid && (m_axi.bresp==`AXI_RESP_OKAY));
    assign axi_rd_ok = (m_axi.rvalid && (m_axi.rresp==`AXI_RESP_OKAY));
 
    //axi-lite master fsm next state driving
    always @(*) begin
        axi_next_state = axi_state;
        case (axi_state)
 
            AXI_IDLE: begin
                if (start_axi_wr_reg) begin
                    axi_next_state = AXI_WAIT_WREADY;
                end
                if (start_axi_rd_reg) begin
                    axi_next_state = AXI_WAIT_RREADY;
                end
            end
 
            AXI_WAIT_WREADY: begin
                if (m_axi.awready & m_axi.wready) begin
                    axi_next_state = AXI_WAIT_BRESP;
                end
            end
 
            AXI_WAIT_BRESP: begin
                if (axi_wr_ok) begin
                    axi_next_state = AXI_IDLE;
                end
            end
 
            AXI_WAIT_RREADY: begin
                if (m_axi.arready) begin
                    axi_next_state = AXI_WAIT_RDATA;
                end
            end
 
            AXI_WAIT_RDATA: begin
                if (axi_rd_ok) begin
                    axi_next_state = AXI_IDLE;
                end
            end
        endcase
    end
 
    //axi-lite fsm axi signal driving
    always @(*) begin
        m_axi_awaddr  = m_axi.awaddr ;
        m_axi_awvalid = m_axi.awvalid;
        m_axi_wdata   = m_axi.wdata  ;
        m_axi_wstrb   = m_axi.wstrb  ;
        m_axi_wvalid  = m_axi.wvalid ;
        m_axi_bready  = m_axi.bready ;
        m_axi_araddr  = m_axi.araddr ;
        m_axi_arvalid = m_axi.arvalid;
        m_axi_rready  = m_axi.rready ;
 
        case (axi_state)
 
            AXI_IDLE: begin
                if (start_axi_wr_reg) begin
                    m_axi_awaddr = addr_reg;
                    m_axi_awvalid = 1'b1;
                    m_axi_wdata   = {24'h0, axi_data_wr_reg};
                    m_axi_wstrb   = 4'hF;
                    m_axi_wvalid  = 1'b1;
                    m_axi_bready  = 1'b1;
                end
                if (start_axi_rd_reg) begin
                    m_axi_araddr  <= addr_reg;
                    m_axi_arvalid <= 1'b1;
                    m_axi_rready  <= 1'b1;
                end
            end
 
            AXI_WAIT_WREADY: begin
                if (m_axi.awready & m_axi.wready) begin
                    m_axi_awaddr  = 4'h0;
                    m_axi_awvalid = 1'b0;
                    m_axi_wdata   = 32'h0;
                    m_axi_wstrb   = 4'h0;
                    m_axi_wvalid  = 1'b0;
                end
            end
 
            AXI_WAIT_BRESP: begin
                if (axi_wr_ok) begin
                    m_axi_bready  = 1'b0;
                end
            end
 
            AXI_WAIT_RREADY: begin
                if (m_axi.arready) begin
                    m_axi_araddr  <= 4'h0;
                    m_axi_arvalid <= 1'b0;
                end
            end
 
            AXI_WAIT_RDATA: begin
                if (axi_rd_ok) begin
                    m_axi_rready  <= 1'b0;
                end
            end
        endcase
    end
 
    assign key_set_complete_o = key_set_complete_reg;
 
endmodule

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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [src/] [wrap/] [system_manager.sv] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	vv_gulyaev	`/**`
2			`* Module system_manager.`
3			`* Functions:`
4			`* - Receive data(key and plainText) and commands from Xilinx IP UARTLITE`
5			`* - Send recieved data to aes-128-ecb encoder`
6			`* - Receive ciphered data from encoder`
7			`* - Send ciphered data to UARTLITE`
8			`*`
9			`* Copyright 2020 by Vyacheslav Gulyaev`
10			`*`
11			`* Licensed under GNU General Public License 3.0 or later.`
12			`* Some rights reserved. See COPYING, AUTHORS.`
13			`*`
14			`* @license GPL-3.0+`
15			`*/`
16
17			`module system_manager(`
18			`input clk_i,`
19			`input rstn_i,`
20
21			`output logic [127:0] plain_text_data_o,`
22			`output logic plain_text_data_valid_o,`
23			`output logic [127:0] key_o,`
24
25			`input [127:0] cipher_data_i,`
26			`input cipher_data_valid_i,`
27
28			`output logic key_set_complete_o,`
29			`output logic startup_pause_complete,`
30
31
32			`input interrupt_i,`
33
34			`axi_interface.master m_axi`
35			`);`
36
37			`define __UART_DEFINES__
38
39			`define CMD_SET_KEY 8'hF0
40			`define CMD_ENC_DATA 8'hE1
41			`define CMD_GET_STAT 8'hD2
42
43			`define RxFIFO_ADDR 4'h0
44			`define TxFIFO_ADDR 4'h4
45			`define STAT_REG_ADDR 4'h8
46			`define CTRL_REG_ADDR 4'hC
47
48			`define STAT_REG_RxFifoValidDataBit 0
49			`define STAT_REG_RxFifoFullBit 1
50			`define STAT_REG_TxFifoEmptyBit 2
51			`define STAT_REG_TxFifoFullBit 3
52			`define STAT_REG_IntrEnabledBit 4
53			`define STAT_REG_OverrunErrorBit 5
54			`define STAT_REG_FrameErrorBit 6
55			`define STAT_REG_ParityErrorBit 7
56
57			`define CTRL_REG_RstTxFifoBit 0
58			`define CTRL_REG_RstRxFifoBit 1
59			`define CTRL_REG_EnableIntrBit 4
60
61			`define AXI_RESP_OKAY 2'b00
62			`define AXI_RESP_EXOKAY 2'b01
63			`define AXI_RESP_SLVERR 2'b10
64			`define AXI_RESP_DECERR 2'b11
65
66			`localparam STARTUP_PAUSE_DUTY = 100; //1us = 100 * 10ns(100MHz)`
67
68			`logic start_axi_wr;`
69			`logic start_axi_wr_reg;`
70			`logic [7:0] axi_data_wr;`
71			`logic [7:0] axi_data_wr_reg;`
72			`logic [3:0] addr;`
73			`logic [3:0] addr_reg;`
74			`logic start_axi_rd;`
75			`logic start_axi_rd_reg;`
76			`logic uart_init_complete;`
77			`logic uart_init_complete_reg;`
78			`logic [7:0] rd_data;`
79			`logic [7:0] rd_data_reg;`
80			`logic rx_fifo_valid_data;`
81			`logic rx_fifo_full;`
82			`logic tx_fifo_empty;`
83			`logic tx_fifo_full;`
84			`logic rx_fifo_valid_data_reg;`
85			`logic rx_fifo_full_reg;`
86			`logic tx_fifo_empty_reg;`
87			`logic tx_fifo_full_reg;`
88			`logic check_stat;`
89			`logic check_stat_reg;`
90			`logic key_set_complete;`
91			`logic key_set_complete_reg;`
92			`logic key_set_in_progress;`
93			`logic key_set_in_progress_reg;`
94			`logic plain_text_set_in_progress;`
95			`logic plain_text_set_in_progress_reg;`
96			`logic [3:0] data_counter;`
97			`logic [3:0] data_counter_reg;`
98			`logic [127:0] plain_text_data;`
99			`logic plain_text_data_valid;`
100			`logic [127:0] key;`
101
102			`logic [127:0] cipher_data;`
103			`logic [127:0] cipher_data_reg;`
104			`logic transmit_in_progress;`
105			`logic transmit_in_progress_reg;`
106			`logic wait_tx_fifo_empty;`
107			`logic wait_tx_fifo_empty_reg;`
108			`logic get_stat;`
109			`logic get_stat_reg;`
110			`logic [7:0] cur_stat;`
111			`logic [7:0] cur_stat_reg;`
112			`logic send_stat;`
113			`logic send_stat_reg;`
114
115			`logic [31:0] startup_pause_cnt;`
116			`// logic startup_pause_complete;`
117
118			`typedef enum { SYS_IDLE,`
119			`INIT_UART_CTRL_REG,`
120			`RD_UART_STAT_REG,`
121			`RD_RX_FIFO,`
122			`WR_TX_FIFO`
123			`} sys_state_t;`
124			`sys_state_t sys_state;`
125			`sys_state_t sys_next_state;`
126
127
128			`//write address channel`
129			`logic [3:0] m_axi_awaddr;`
130			`logic m_axi_awvalid;`
131
132			`//write data channel`
133			`logic [7:0] m_axi_wdata;`
134			`logic [3:0] m_axi_wstrb;`
135			`logic m_axi_wvalid;`
136
137			`//write response channel`
138			`logic m_axi_bready;`
139
140			`//read address channel`
141			`logic [3:0] m_axi_araddr;`
142			`logic m_axi_arvalid;`
143
144			`//read data channel`
145			`logic m_axi_rready;`
146
147			`wire axi_wr_ok;`
148			`wire axi_rd_ok;`
149
150			`typedef enum { AXI_IDLE,`
151			`AXI_WAIT_WREADY,`
152			`AXI_WAIT_BRESP,`
153			`AXI_WAIT_RREADY,`
154			`AXI_WAIT_RDATA`
155			`} axi_state_t;`
156			`axi_state_t axi_state;`
157			`axi_state_t axi_next_state;`
158
159			`always @(posedge clk_i or negedge rstn_i) begin`
160			`if (!rstn_i) begin`
161			`startup_pause_cnt <= 32'h0;`
162			`end else if (~startup_pause_complete) begin`
163			`startup_pause_cnt <= startup_pause_cnt + 1;`
164			`end`
165			`end`
166			`assign startup_pause_complete = (startup_pause_cnt==STARTUP_PAUSE_DUTY) ? 1'b1 : 1'b0;`
167
168
169			`//sys manager registering`
170			`always @(posedge clk_i or negedge rstn_i) begin`
171			`if (~rstn_i) begin`
172			`start_axi_wr_reg <= 1'b0;`
173			`axi_data_wr_reg <= 8'h0;`
174			`addr_reg <= 4'h0;`
175			`start_axi_rd_reg <= 1'b0;`
176			`uart_init_complete_reg <= 1'b0;`
177			`rd_data_reg <= 8'h0;`
178			`rx_fifo_valid_data_reg <= 1'b0;`
179			`rx_fifo_full_reg <= 1'b0;`
180			`tx_fifo_empty_reg <= 1'b0;`
181			`tx_fifo_full_reg <= 1'b0;`
182			`check_stat_reg <= 1'b0;`
183			`key_set_complete_reg <= 1'b0;`
184			`key_set_in_progress_reg <= 1'b0;`
185			`plain_text_set_in_progress_reg <= 1'b0;`
186			`data_counter_reg <= 4'h0;`
187			`plain_text_data_o <= 128'h0;`
188			`plain_text_data_valid_o <= 1'b0;`
189			`key_o <= 128'h0;`
190			`cipher_data_reg <= 128'h0;`
191			`transmit_in_progress_reg <= 1'b0;`
192			`wait_tx_fifo_empty_reg <= 1'b0;`
193			`get_stat_reg <= 1'b0;`
194			`cur_stat_reg <= 8'h0;`
195			`send_stat_reg <= 1'b0;`
196
197			`sys_state <= SYS_IDLE;`
198			`end else begin`
199			`start_axi_wr_reg <= start_axi_wr;`
200			`axi_data_wr_reg <= axi_data_wr;`
201			`addr_reg <= addr;`
202			`start_axi_rd_reg <= start_axi_rd;`
203			`uart_init_complete_reg <= uart_init_complete;`
204			`rd_data_reg <= rd_data;`
205			`rx_fifo_valid_data_reg <= rx_fifo_valid_data;`
206			`rx_fifo_full_reg <= rx_fifo_full;`
207			`tx_fifo_empty_reg <= tx_fifo_empty;`
208			`tx_fifo_full_reg <= tx_fifo_full;`
209			`check_stat_reg <= check_stat;`
210			`key_set_complete_reg <= key_set_complete;`
211			`key_set_in_progress_reg <= key_set_in_progress;`
212			`plain_text_set_in_progress_reg <= plain_text_set_in_progress;`
213			`data_counter_reg <= data_counter;`
214			`plain_text_data_o <= plain_text_data;`
215			`plain_text_data_valid_o <= plain_text_data_valid;`
216			`key_o <= key;`
217			`cipher_data_reg <= cipher_data;`
218			`transmit_in_progress_reg <= transmit_in_progress;`
219			`wait_tx_fifo_empty_reg <= wait_tx_fifo_empty;`
220			`get_stat_reg <= get_stat;`
221			`cur_stat_reg <= cur_stat;`
222			`send_stat_reg <= send_stat;`
223
224			`sys_state <= sys_next_state;`
225			`end`
226			`end`
227
228			`//sys manager state handling`
229			`always @(*) begin`
230			`sys_next_state = sys_state;`
231			`case (sys_state)`
232			`SYS_IDLE: begin`
233			`if (~uart_init_complete_reg & startup_pause_complete) begin`
234			`sys_next_state = INIT_UART_CTRL_REG;`
235			`end else if (interrupt_i \| check_stat_reg \| get_stat_reg) begin`
236			`sys_next_state = RD_UART_STAT_REG;`
237			`end else if (rx_fifo_valid_data_reg) begin`
238			`sys_next_state = RD_RX_FIFO;`
239			`end else if (cipher_data_valid_i \| transmit_in_progress_reg \| send_stat_reg) begin`
240			`sys_next_state = WR_TX_FIFO;`
241			`end`
242			`end`
243
244			`INIT_UART_CTRL_REG, WR_TX_FIFO: begin`
245			`if (axi_wr_ok) begin`
246			`sys_next_state = SYS_IDLE;`
247			`end`
248			`end`
249
250			`RD_UART_STAT_REG, RD_RX_FIFO: begin`
251			`if (axi_rd_ok) begin`
252			`sys_next_state = SYS_IDLE;`
253			`end`
254			`end`
255			`endcase`
256			`end`
257
258			`//sys manager fsm`
259			`always @(*) begin`
260			`start_axi_wr = start_axi_wr_reg;`
261			`axi_data_wr = axi_data_wr_reg;`
262			`addr = addr_reg;`
263			`start_axi_rd = start_axi_rd_reg;`
264			`uart_init_complete = uart_init_complete_reg;`
265			`rd_data = rd_data_reg;`
266			`rx_fifo_valid_data = rx_fifo_valid_data_reg;`
267			`rx_fifo_full = rx_fifo_full_reg;`
268			`tx_fifo_empty = tx_fifo_empty_reg;`
269			`tx_fifo_full = tx_fifo_full_reg;`
270			`check_stat = check_stat_reg;`
271			`key_set_complete = key_set_complete_reg;`
272			`key_set_in_progress = key_set_in_progress_reg;`
273			`plain_text_set_in_progress = plain_text_set_in_progress_reg;`
274			`data_counter = data_counter_reg;`
275			`plain_text_data = plain_text_set_in_progress_reg ? plain_text_data_o : 128'h0;`
276			`plain_text_data_valid = 1'b0;`
277			`key = key_o;`
278			`cipher_data = cipher_data_reg;`
279			`transmit_in_progress = transmit_in_progress_reg;`
280			`wait_tx_fifo_empty = wait_tx_fifo_empty_reg;`
281			`get_stat = get_stat_reg;`
282			`cur_stat = cur_stat_reg;`
283			`send_stat = send_stat_reg;`
284
285			`case (sys_state)`
286			`SYS_IDLE: begin`
287			`if (~uart_init_complete_reg & startup_pause_complete) begin`
288			`start_axi_wr = 1'b1;`
289			axi_data_wr[`CTRL_REG_RstTxFifoBit] = 1'b1;
290			axi_data_wr[`CTRL_REG_RstRxFifoBit] = 1'b1;
291			axi_data_wr[`CTRL_REG_EnableIntrBit] = 1'b1;
292			addr = `CTRL_REG_ADDR;
293			`end else if (interrupt_i \| check_stat_reg \| get_stat_reg) begin`
294			`start_axi_rd = 1'b1;`
295			addr = `STAT_REG_ADDR;
296			`end else if (rx_fifo_valid_data_reg & ~wait_tx_fifo_empty_reg) begin`
297			`start_axi_rd = 1'b1;`
298			addr = `RxFIFO_ADDR;
299			`end else if (cipher_data_valid_i) begin`
300			`start_axi_wr = 1'b1;`
301			`axi_data_wr[7:0] = cipher_data_i[127:120];`
302			addr = `TxFIFO_ADDR;
303			`cipher_data[127:0] = cipher_data_i[127:0];`
304			`transmit_in_progress <= 1'b1;`
305			`end else if (transmit_in_progress_reg) begin`
306			`start_axi_wr = 1'b1;`
307			`axi_data_wr[7:0] = cipher_data_reg[127:120];`
308			addr = `TxFIFO_ADDR;
309			`end else if (send_stat_reg) begin`
310			`start_axi_wr = 1'b1;`
311			`axi_data_wr[7:0] = cur_stat;`
312			addr = `TxFIFO_ADDR;
313			`end`
314			`end`
315
316			`INIT_UART_CTRL_REG: begin`
317			`start_axi_wr = 1'b0;`
318			`axi_data_wr = 8'h0;`
319			`addr = 4'h0;`
320			`if (axi_wr_ok) begin`
321			`uart_init_complete = 1'b1;`
322			`end`
323			`end`
324
325			`RD_UART_STAT_REG: begin`
326			`start_axi_rd = 1'b0;`
327			`addr = 4'h0;`
328			`check_stat = 1'b0;`
329			`if (axi_rd_ok) begin`
330			rx_fifo_valid_data = m_axi.rdata[`STAT_REG_RxFifoValidDataBit];
331			rx_fifo_full = m_axi.rdata[`STAT_REG_RxFifoFullBit];
332			tx_fifo_empty = m_axi.rdata[`STAT_REG_TxFifoEmptyBit];
333			tx_fifo_full = m_axi.rdata[`STAT_REG_TxFifoFullBit];
334			`if (wait_tx_fifo_empty_reg) begin`
335			`wait_tx_fifo_empty = tx_fifo_empty ? 1'b0 : 1'b1;`
336			`end`
337			`cur_stat = m_axi.rdata[7:0];`
338			`if (get_stat_reg) begin`
339			`get_stat = 1'b0;`
340			`send_stat = 1'b1;`
341			`end`
342			`end`
343			`end`
344
345			`RD_RX_FIFO: begin`
346			`start_axi_rd = 1'b0;`
347			`addr = 4'h0;`
348			`check_stat = 1'b1;`
349			`if (axi_rd_ok) begin`
350			`rd_data = m_axi.rdata[7:0];`
351			`if (~key_set_in_progress_reg & ~plain_text_set_in_progress_reg) begin`
352			`case (rd_data)`
353			`CMD_SET_KEY: begin
354			`key_set_complete = 1'b0;`
355			`key_set_in_progress = 1'b1;`
356			`data_counter = 4'h0;`
357			`key = 128'h0;`
358			`end`
359			`CMD_ENC_DATA: begin
360			`plain_text_set_in_progress = 1'b1;`
361			`data_counter = 4'h0;`
362			`plain_text_data = 128'h0;`
363			`end`
364			`CMD_GET_STAT: begin
365			`get_stat = 1'b1;`
366			`end`
367			`endcase`
368			`end else if (key_set_in_progress_reg) begin`
369			`key[127:0] = {key_o[120:0], rd_data};`
370			`if (data_counter==4'hF) begin`
371			`key_set_in_progress = 1'b0;`
372			`key_set_complete = 1'b1;`
373			`data_counter = 4'h0;`
374			`end else begin`
375			`data_counter = data_counter + 1;`
376			`end`
377			`end else if (plain_text_set_in_progress_reg) begin`
378			`plain_text_data[127:0] = {plain_text_data_o[120:0], rd_data};`
379			`if (data_counter==4'hF) begin`
380			`plain_text_set_in_progress = 1'b0;`
381			`plain_text_data_valid = 1'b1;`
382			`data_counter = 4'h0;`
383			`end else begin`
384			`data_counter = data_counter + 1;`
385			`end`
386			`end`
387			`end`
388			`end`
389
390			`WR_TX_FIFO: begin`
391			`start_axi_wr = 1'b0;`
392			`axi_data_wr = 8'h0;`
393			`addr = 4'h0;`
394			`if (axi_wr_ok) begin`
395			`if (send_stat_reg) begin`
396			`send_stat = 1'b0;`
397			`end else if (data_counter==4'hF) begin`
398			`transmit_in_progress = 1'b0;`
399			`data_counter = 4'h0;`
400			`wait_tx_fifo_empty = 1'b1;`
401			`end else begin`
402			`cipher_data[127:0] = {cipher_data_reg[120:0], 8'h0};`
403			`data_counter = data_counter + 1;`
404			`end`
405			`end`
406			`end`
407
408			`endcase`
409			`end`
410
411			`//axi-lite registering`
412			`always @(posedge clk_i or negedge rstn_i) begin`
413			`if (~rstn_i) begin`
414			`m_axi.awaddr <= 4'h0;`
415			`m_axi.awvalid <= 1'b0;`
416			`m_axi.wdata <= 32'h0;`
417			`m_axi.wstrb <= 4'h0;`
418			`m_axi.wvalid <= 1'b0;`
419			`m_axi.bready <= 1'b0;`
420			`m_axi.araddr <= 4'h0;`
421			`m_axi.arvalid <= 1'b0;`
422			`m_axi.rready <= 1'b0;`
423
424			`axi_state <= axi_next_state;`
425			`end else begin`
426			`m_axi.awaddr <= m_axi_awaddr;`
427			`m_axi.awvalid <= m_axi_awvalid;`
428			`m_axi.wdata <= m_axi_wdata;`
429			`m_axi.wstrb <= m_axi_wstrb;`
430			`m_axi.wvalid <= m_axi_wvalid;`
431			`m_axi.bready <= m_axi_bready;`
432			`m_axi.araddr <= m_axi_araddr;`
433			`m_axi.arvalid <= m_axi_arvalid;`
434			`m_axi.rready <= m_axi_rready;`
435
436			`axi_state <= axi_next_state;`
437			`end`
438			`end`
439
440
441			assign axi_wr_ok = (m_axi.bvalid && (m_axi.bresp==`AXI_RESP_OKAY));
442			assign axi_rd_ok = (m_axi.rvalid && (m_axi.rresp==`AXI_RESP_OKAY));
443
444			`//axi-lite master fsm next state driving`
445			`always @(*) begin`
446			`axi_next_state = axi_state;`
447			`case (axi_state)`
448
449			`AXI_IDLE: begin`
450			`if (start_axi_wr_reg) begin`
451			`axi_next_state = AXI_WAIT_WREADY;`
452			`end`
453			`if (start_axi_rd_reg) begin`
454			`axi_next_state = AXI_WAIT_RREADY;`
455			`end`
456			`end`
457
458			`AXI_WAIT_WREADY: begin`
459			`if (m_axi.awready & m_axi.wready) begin`
460			`axi_next_state = AXI_WAIT_BRESP;`
461			`end`
462			`end`
463
464			`AXI_WAIT_BRESP: begin`
465			`if (axi_wr_ok) begin`
466			`axi_next_state = AXI_IDLE;`
467			`end`
468			`end`
469
470			`AXI_WAIT_RREADY: begin`
471			`if (m_axi.arready) begin`
472			`axi_next_state = AXI_WAIT_RDATA;`
473			`end`
474			`end`
475
476			`AXI_WAIT_RDATA: begin`
477			`if (axi_rd_ok) begin`
478			`axi_next_state = AXI_IDLE;`
479			`end`
480			`end`
481			`endcase`
482			`end`
483
484			`//axi-lite fsm axi signal driving`
485			`always @(*) begin`
486			`m_axi_awaddr = m_axi.awaddr ;`
487			`m_axi_awvalid = m_axi.awvalid;`
488			`m_axi_wdata = m_axi.wdata ;`
489			`m_axi_wstrb = m_axi.wstrb ;`
490			`m_axi_wvalid = m_axi.wvalid ;`
491			`m_axi_bready = m_axi.bready ;`
492			`m_axi_araddr = m_axi.araddr ;`
493			`m_axi_arvalid = m_axi.arvalid;`
494			`m_axi_rready = m_axi.rready ;`
495
496			`case (axi_state)`
497
498			`AXI_IDLE: begin`
499			`if (start_axi_wr_reg) begin`
500			`m_axi_awaddr = addr_reg;`
501			`m_axi_awvalid = 1'b1;`
502			`m_axi_wdata = {24'h0, axi_data_wr_reg};`
503			`m_axi_wstrb = 4'hF;`
504			`m_axi_wvalid = 1'b1;`
505			`m_axi_bready = 1'b1;`
506			`end`
507			`if (start_axi_rd_reg) begin`
508			`m_axi_araddr <= addr_reg;`
509			`m_axi_arvalid <= 1'b1;`
510			`m_axi_rready <= 1'b1;`
511			`end`
512			`end`
513
514			`AXI_WAIT_WREADY: begin`
515			`if (m_axi.awready & m_axi.wready) begin`
516			`m_axi_awaddr = 4'h0;`
517			`m_axi_awvalid = 1'b0;`
518			`m_axi_wdata = 32'h0;`
519			`m_axi_wstrb = 4'h0;`
520			`m_axi_wvalid = 1'b0;`
521			`end`
522			`end`
523
524			`AXI_WAIT_BRESP: begin`
525			`if (axi_wr_ok) begin`
526			`m_axi_bready = 1'b0;`
527			`end`
528			`end`
529
530			`AXI_WAIT_RREADY: begin`
531			`if (m_axi.arready) begin`
532			`m_axi_araddr <= 4'h0;`
533			`m_axi_arvalid <= 1'b0;`
534			`end`
535			`end`
536
537			`AXI_WAIT_RDATA: begin`
538			`if (axi_rd_ok) begin`
539			`m_axi_rready <= 1'b0;`
540			`end`
541			`end`
542			`endcase`
543			`end`
544
545			`assign key_set_complete_o = key_set_complete_reg;`
546
547			`endmodule`