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[/] [aes-128_pipelined_encryption/] [tags/] [R0/] [reports/] [Top_PipelinedCipher.syr] - Blame information for rev 2

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Release 12.1 - xst M.53d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.15 secs
 
--> Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.15 secs
 
--> Reading design: Top_PipelinedCipher.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Top_PipelinedCipher.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "Top_PipelinedCipher"
Output Format                      : NGC
Target Device                      : xc6vcx240t-2-ff784
 
---- Source Options
Top Module Name                    : Top_PipelinedCipher
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : auto
Automatic Register Balancing       : No
 
---- Target Options
LUT Combining                      : auto
Reduce Control Sets                : auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Library Search Order               : Top_PipelinedCipher.lso
Keep Hierarchy                     : NO
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing Verilog file "E:\AES\AES\SBox.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\SubBytes.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\ShiftRows.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\RoundKeyGen.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\MixColumns.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\AddRoundKey.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\Round.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\KeyExpantion.v" into library work
Parsing module .
Parsing Verilog file "E:\AES\AES\Top_PipelinedCipher.v" into library work
Parsing module .
 
=========================================================================
*                            HDL Elaboration                            *
=========================================================================
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
Elaborating module .
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/top_pipelinedcipher.v".
        DATA_W = 128
        KEY_L = 128
        NO_ROUNDS = 10
    Found 128-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred 129 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/keyexpantion.v".
        DATA_W = 128
        KEY_L = 128
        NO_ROUNDS = 10
    Summary:
        no macro.
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/roundkeygen.v".
        KEY_L = 128
        WORD = 32
    Found 128-bit register for signal .
    Found 128-bit register for signal .
    Found 128-bit register for signal .
    Found 128-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred 515 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/subbytes.v".
        DATA_W = 32
        NO_BYTES = 4
    Found 1-bit register for signal .
    Summary:
        inferred   1 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/sbox.v".
    Found 8-bit register for signal .
    Found 256x8-bit Read Only RAM for signal 
    Summary:
        inferred   1 RAM(s).
        inferred   8 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/addroundkey.v".
        DATA_W = 128
    Found 128-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred 129 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/round.v".
        DATA_W = 128
    Summary:
        no macro.
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/subbytes.v".
        DATA_W = 128
        NO_BYTES = 16
    Found 1-bit register for signal .
    Summary:
        inferred   1 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/shiftrows.v".
        DATA_W = 128
    Found 128-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred 129 D-type flip-flop(s).
Unit  synthesized.
 
Synthesizing Unit .
    Related source file is "e:/aes/aes/mixcolumns.v".
        DATA_W = 128
    Found 128-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred 129 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit  synthesized.
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# RAMs                                                 : 200
 256x8-bit single-port Read Only RAM                   : 200
# Registers                                            : 352
 1-bit register                                        : 81
 128-bit register                                      : 71
 8-bit register                                        : 200
# Multiplexers                                         : 144
 8-bit 2-to-1 multiplexer                              : 144
# Xors                                                 : 349
 128-bit xor2                                          : 11
 32-bit xor2                                           : 50
 8-bit xor2                                            : 144
 8-bit xor5                                            : 144
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
 
Synthesizing (advanced) Unit .
INFO:Xst:3030 - HDL ADVISOR - Register  currently described with an asynchronous reset, could be combined with distributed RAM  for implementation on block RAM resources if you made this reset synchronous instead.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 8-bit                    |          |
    |     weA            | connected to signal            | high     |
    |     addrA          | connected to signal           |          |
    |     diA            | connected to signal            |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3031 - HDL ADVISOR - The RAM  will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
Unit  synthesized (advanced).
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# RAMs                                                 : 200
 256x8-bit single-port distributed Read Only RAM       : 200
# Registers                                            : 10769
 Flip-Flops                                            : 10769
# Multiplexers                                         : 144
 8-bit 2-to-1 multiplexer                              : 144
# Xors                                                 : 349
 128-bit xor2                                          : 11
 32-bit xor2                                           : 50
 8-bit xor2                                            : 144
 8-bit xor5                                            : 144
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Top_PipelinedCipher, actual ratio is 12.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 10769
 Flip-Flops                                            : 10769
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Design Summary                             *
=========================================================================
 
Top Level Output File Name         : Top_PipelinedCipher.ngc
 
Primitive and Black Box Usage:
------------------------------
# BELS                             : 15403
#      INV                         : 1
#      LUT2                        : 810
#      LUT3                        : 320
#      LUT4                        : 1600
#      LUT5                        : 1040
#      LUT6                        : 6832
#      MUXF7                       : 3200
#      MUXF8                       : 1600
# FlipFlops/Latches                : 10769
#      FDC                         : 81
#      FDCE                        : 10688
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 388
#      IBUF                        : 259
#      OBUF                        : 129
 
Device utilization summary:
---------------------------
 
Selected Device : 6vcx240tff784-2
 
 
Slice Logic Utilization:
 Number of Slice Registers:           10769  out of  301440     3%
 Number of Slice LUTs:                10603  out of  150720     7%
    Number used as Logic:             10603  out of  150720     7%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:  15921
   Number with an unused Flip Flop:    5152  out of  15921    32%
   Number with an unused LUT:          5318  out of  15921    33%
   Number of fully used LUT-FF pairs:  5451  out of  15921    34%
   Number of unique control sets:        82
 
IO Utilization:
 Number of IOs:                         389
 Number of bonded IOBs:                 389  out of    400    97%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     32     6%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
Timing Report
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 10769 |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -2
 
   Minimum period: 1.564ns (Maximum Frequency: 639.391MHz)
   Minimum input arrival time before clock: 1.252ns
   Maximum output required time after clock: 0.664ns
   Maximum combinational path delay: No path found
 
Timing Details:
---------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 1.564ns (frequency: 639.391MHz)
  Total number of paths / destination ports: 75065 / 20943
-------------------------------------------------------------------------
Delay:               1.564ns (Levels of Logic = 3)
  Source:            U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (FF)
  Destination:       U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising
 
  Data Path: U_KEYEXP/RKGEN_U0/Key_FirstStage_24 to U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            33   0.317   0.826  U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (U_KEYEXP/RKGEN_U0/Key_FirstStage_24)
     LUT6:I0->O            1   0.061   0.000  U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23)
     MUXF7:I1->O           1   0.211   0.000  U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f7_0 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f71)
     MUXF8:I0->O           1   0.149   0.000  U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f8 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/addr[7]_GND_5_o_wide_mux_0_OUT<1>)
     FDCE:D                   -0.002          U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_1
    ----------------------------------------
    Total                      1.564ns (0.738ns logic, 0.826ns route)
                                       (47.2% logic, 52.8% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 771 / 514
-------------------------------------------------------------------------
Offset:              1.252ns (Levels of Logic = 2)
  Source:            cipherkey_valid_in (PAD)
  Destination:       U0_ARK/data_out_127 (FF)
  Destination Clock: clk rising
 
  Data Path: cipherkey_valid_in to U0_ARK/data_out_127
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           130   0.003   0.505  cipherkey_valid_in_IBUF (cipherkey_valid_in_IBUF)
     LUT2:I1->O          129   0.061   0.487  U0_ARK/data_valid_in_key_valid_in_AND_2_o1 (U0_ARK/data_valid_in_key_valid_in_AND_2_o)
     FDCE:CE                   0.196          U0_ARK/data_out_0
    ----------------------------------------
    Total                      1.252ns (0.260ns logic, 0.992ns route)
                                       (20.8% logic, 79.2% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 129 / 129
-------------------------------------------------------------------------
Offset:              0.664ns (Levels of Logic = 1)
  Source:            U_KEY/data_out_127 (FF)
  Destination:       cipher_text<127> (PAD)
  Source Clock:      clk rising
 
  Data Path: U_KEY/data_out_127 to cipher_text<127>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.317   0.344  U_KEY/data_out_127 (U_KEY/data_out_127)
     OBUF:I->O                 0.003          cipher_text_127_OBUF (cipher_text<127>)
    ----------------------------------------
    Total                      0.664ns (0.320ns logic, 0.344ns route)
                                       (48.2% logic, 51.8% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 106.00 secs
Total CPU time to Xst completion: 105.60 secs
 
-->
 
Total memory usage is 397192 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)
 

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Subversion Repositories aes-128_pipelined_encryption

[/] [aes-128_pipelined_encryption/] [tags/] [R0/] [reports/] [Top_PipelinedCipher.syr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	Amr_Salah	`Release 12.1 - xst M.53d (nt64)`
2			`Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.`
3			`--> Parameter TMPDIR set to xst/projnav.tmp`
4
5
6			`Total REAL time to Xst completion: 1.00 secs`
7			`Total CPU time to Xst completion: 0.15 secs`
8
9			`--> Parameter xsthdpdir set to xst`
10
11
12			`Total REAL time to Xst completion: 1.00 secs`
13			`Total CPU time to Xst completion: 0.15 secs`
14
15			`--> Reading design: Top_PipelinedCipher.prj`
16
17			`TABLE OF CONTENTS`
18			`1) Synthesis Options Summary`
19			`2) HDL Parsing`
20			`3) HDL Elaboration`
21			`4) HDL Synthesis`
22			`4.1) HDL Synthesis Report`
23			`5) Advanced HDL Synthesis`
24			`5.1) Advanced HDL Synthesis Report`
25			`6) Low Level Synthesis`
26			`7) Partition Report`
27			`8) Design Summary`
28			`8.1) Primitive and Black Box Usage`
29			`8.2) Device utilization summary`
30			`8.3) Partition Resource Summary`
31			`8.4) Timing Report`
32			`8.4.1) Clock Information`
33			`8.4.2) Asynchronous Control Signals Information`
34			`8.4.3) Timing Summary`
35			`8.4.4) Timing Details`
36
37
38			`=========================================================================`
39			`* Synthesis Options Summary *`
40			`=========================================================================`
41			`---- Source Parameters`
42			`Input File Name : "Top_PipelinedCipher.prj"`
43			`Input Format : mixed`
44			`Ignore Synthesis Constraint File : NO`
45
46			`---- Target Parameters`
47			`Output File Name : "Top_PipelinedCipher"`
48			`Output Format : NGC`
49			`Target Device : xc6vcx240t-2-ff784`
50
51			`---- Source Options`
52			`Top Module Name : Top_PipelinedCipher`
53			`Automatic FSM Extraction : YES`
54			`FSM Encoding Algorithm : Auto`
55			`Safe Implementation : No`
56			`FSM Style : lut`
57			`RAM Extraction : Yes`
58			`RAM Style : Auto`
59			`ROM Extraction : Yes`
60			`Shift Register Extraction : YES`
61			`ROM Style : Auto`
62			`Resource Sharing : YES`
63			`Asynchronous To Synchronous : NO`
64			`Shift Register Minimum Size : 2`
65			`Use DSP Block : auto`
66			`Automatic Register Balancing : No`
67
68			`---- Target Options`
69			`LUT Combining : auto`
70			`Reduce Control Sets : auto`
71			`Add IO Buffers : YES`
72			`Global Maximum Fanout : 100000`
73			`Add Generic Clock Buffer(BUFG) : 32`
74			`Register Duplication : YES`
75			`Optimize Instantiated Primitives : NO`
76			`Use Clock Enable : Auto`
77			`Use Synchronous Set : Auto`
78			`Use Synchronous Reset : Auto`
79			`Pack IO Registers into IOBs : auto`
80			`Equivalent register Removal : YES`
81
82			`---- General Options`
83			`Optimization Goal : Speed`
84			`Optimization Effort : 1`
85			`Power Reduction : NO`
86			`Library Search Order : Top_PipelinedCipher.lso`
87			`Keep Hierarchy : NO`
88			`Netlist Hierarchy : as_optimized`
89			`RTL Output : Yes`
90			`Global Optimization : AllClockNets`
91			`Read Cores : YES`
92			`Write Timing Constraints : NO`
93			`Cross Clock Analysis : NO`
94			`Hierarchy Separator : /`
95			`Bus Delimiter : <>`
96			`Case Specifier : maintain`
97			`Slice Utilization Ratio : 100`
98			`BRAM Utilization Ratio : 100`
99			`DSP48 Utilization Ratio : 100`
100			`Auto BRAM Packing : NO`
101			`Slice Utilization Ratio Delta : 5`
102
103			`=========================================================================`
104
105
106			`=========================================================================`
107			`* HDL Parsing *`
108			`=========================================================================`
109			`Parsing Verilog file "E:\AES\AES\SBox.v" into library work`
110			`Parsing module .`
111			`Parsing Verilog file "E:\AES\AES\SubBytes.v" into library work`
112			`Parsing module .`
113			`Parsing Verilog file "E:\AES\AES\ShiftRows.v" into library work`
114			`Parsing module .`
115			`Parsing Verilog file "E:\AES\AES\RoundKeyGen.v" into library work`
116			`Parsing module .`
117			`Parsing Verilog file "E:\AES\AES\MixColumns.v" into library work`
118			`Parsing module .`
119			`Parsing Verilog file "E:\AES\AES\AddRoundKey.v" into library work`
120			`Parsing module .`
121			`Parsing Verilog file "E:\AES\AES\Round.v" into library work`
122			`Parsing module .`
123			`Parsing Verilog file "E:\AES\AES\KeyExpantion.v" into library work`
124			`Parsing module .`
125			`Parsing Verilog file "E:\AES\AES\Top_PipelinedCipher.v" into library work`
126			`Parsing module .`
127
128			`=========================================================================`
129			`* HDL Elaboration *`
130			`=========================================================================`
131
132			`Elaborating module .`
133
134			`Elaborating module .`
135
136			`Elaborating module .`
137
138			`Elaborating module .`
139
140			`Elaborating module .`
141
142			`Elaborating module .`
143
144			`Elaborating module .`
145
146			`Elaborating module .`
147
148			`Elaborating module .`
149
150			`Elaborating module .`
151
152			`=========================================================================`
153			`* HDL Synthesis *`
154			`=========================================================================`
155
156			`Synthesizing Unit .`
157			`Related source file is "e:/aes/aes/top_pipelinedcipher.v".`
158			`DATA_W = 128`
159			`KEY_L = 128`
160			`NO_ROUNDS = 10`
161			`Found 128-bit register for signal .`
162			`Found 1-bit register for signal .`
163			`Summary:`
164			`inferred 129 D-type flip-flop(s).`
165			`Unit synthesized.`
166
167			`Synthesizing Unit .`
168			`Related source file is "e:/aes/aes/keyexpantion.v".`
169			`DATA_W = 128`
170			`KEY_L = 128`
171			`NO_ROUNDS = 10`
172			`Summary:`
173			`no macro.`
174			`Unit synthesized.`
175
176			`Synthesizing Unit .`
177			`Related source file is "e:/aes/aes/roundkeygen.v".`
178			`KEY_L = 128`
179			`WORD = 32`
180			`Found 128-bit register for signal .`
181			`Found 128-bit register for signal .`
182			`Found 128-bit register for signal .`
183			`Found 128-bit register for signal .`
184			`Found 1-bit register for signal .`
185			`Found 1-bit register for signal .`
186			`Found 1-bit register for signal .`
187			`Summary:`
188			`inferred 515 D-type flip-flop(s).`
189			`Unit synthesized.`
190
191			`Synthesizing Unit .`
192			`Related source file is "e:/aes/aes/subbytes.v".`
193			`DATA_W = 32`
194			`NO_BYTES = 4`
195			`Found 1-bit register for signal .`
196			`Summary:`
197			`inferred 1 D-type flip-flop(s).`
198			`Unit synthesized.`
199
200			`Synthesizing Unit .`
201			`Related source file is "e:/aes/aes/sbox.v".`
202			`Found 8-bit register for signal .`
203			`Found 256x8-bit Read Only RAM for signal`
204			`Summary:`
205			`inferred 1 RAM(s).`
206			`inferred 8 D-type flip-flop(s).`
207			`Unit synthesized.`
208
209			`Synthesizing Unit .`
210			`Related source file is "e:/aes/aes/addroundkey.v".`
211			`DATA_W = 128`
212			`Found 128-bit register for signal .`
213			`Found 1-bit register for signal .`
214			`Summary:`
215			`inferred 129 D-type flip-flop(s).`
216			`Unit synthesized.`
217
218			`Synthesizing Unit .`
219			`Related source file is "e:/aes/aes/round.v".`
220			`DATA_W = 128`
221			`Summary:`
222			`no macro.`
223			`Unit synthesized.`
224
225			`Synthesizing Unit .`
226			`Related source file is "e:/aes/aes/subbytes.v".`
227			`DATA_W = 128`
228			`NO_BYTES = 16`
229			`Found 1-bit register for signal .`
230			`Summary:`
231			`inferred 1 D-type flip-flop(s).`
232			`Unit synthesized.`
233
234			`Synthesizing Unit .`
235			`Related source file is "e:/aes/aes/shiftrows.v".`
236			`DATA_W = 128`
237			`Found 128-bit register for signal .`
238			`Found 1-bit register for signal .`
239			`Summary:`
240			`inferred 129 D-type flip-flop(s).`
241			`Unit synthesized.`
242
243			`Synthesizing Unit .`
244			`Related source file is "e:/aes/aes/mixcolumns.v".`
245			`DATA_W = 128`
246			`Found 128-bit register for signal .`
247			`Found 1-bit register for signal .`
248			`Summary:`
249			`inferred 129 D-type flip-flop(s).`
250			`inferred 16 Multiplexer(s).`
251			`Unit synthesized.`
252
253			`=========================================================================`
254			`HDL Synthesis Report`
255
256			`Macro Statistics`
257			`# RAMs : 200`
258			`256x8-bit single-port Read Only RAM : 200`
259			`# Registers : 352`
260			`1-bit register : 81`
261			`128-bit register : 71`
262			`8-bit register : 200`
263			`# Multiplexers : 144`
264			`8-bit 2-to-1 multiplexer : 144`
265			`# Xors : 349`
266			`128-bit xor2 : 11`
267			`32-bit xor2 : 50`
268			`8-bit xor2 : 144`
269			`8-bit xor5 : 144`
270
271			`=========================================================================`
272
273			`=========================================================================`
274			`* Advanced HDL Synthesis *`
275			`=========================================================================`
276
277
278			`Synthesizing (advanced) Unit .`
279			`INFO:Xst:3030 - HDL ADVISOR - Register currently described with an asynchronous reset, could be combined with distributed RAM for implementation on block RAM resources if you made this reset synchronous instead.`
280			`-----------------------------------------------------------------------`
281			`\| ram_type \| Distributed \| \|`
282			`-----------------------------------------------------------------------`
283			`\| Port A \|`
284			`\| aspect ratio \| 256-word x 8-bit \| \|`
285			`\| weA \| connected to signal \| high \|`
286			`\| addrA \| connected to signal \| \|`
287			`\| diA \| connected to signal \| \|`
288			`\| doA \| connected to internal node \| \|`
289			`-----------------------------------------------------------------------`
290			`INFO:Xst:3031 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.`
291			`Unit synthesized (advanced).`
292
293			`=========================================================================`
294			`Advanced HDL Synthesis Report`
295
296			`Macro Statistics`
297			`# RAMs : 200`
298			`256x8-bit single-port distributed Read Only RAM : 200`
299			`# Registers : 10769`
300			`Flip-Flops : 10769`
301			`# Multiplexers : 144`
302			`8-bit 2-to-1 multiplexer : 144`
303			`# Xors : 349`
304			`128-bit xor2 : 11`
305			`32-bit xor2 : 50`
306			`8-bit xor2 : 144`
307			`8-bit xor5 : 144`
308
309			`=========================================================================`
310
311			`=========================================================================`
312			`* Low Level Synthesis *`
313			`=========================================================================`
314
315			`Optimizing unit ...`
316
317			`Optimizing unit ...`
318
319			`Optimizing unit ...`
320
321			`Optimizing unit ...`
322
323			`Optimizing unit ...`
324
325			`Optimizing unit ...`
326
327			`Optimizing unit ...`
328
329			`Mapping all equations...`
330			`Building and optimizing final netlist ...`
331			`Found area constraint ratio of 100 (+ 5) on block Top_PipelinedCipher, actual ratio is 12.`
332
333			`Final Macro Processing ...`
334
335			`=========================================================================`
336			`Final Register Report`
337
338			`Macro Statistics`
339			`# Registers : 10769`
340			`Flip-Flops : 10769`
341
342			`=========================================================================`
343
344			`=========================================================================`
345			`* Partition Report *`
346			`=========================================================================`
347
348			`Partition Implementation Status`
349			`-------------------------------`
350
351			`No Partitions were found in this design.`
352
353			`-------------------------------`
354
355			`=========================================================================`
356			`* Design Summary *`
357			`=========================================================================`
358
359			`Top Level Output File Name : Top_PipelinedCipher.ngc`
360
361			`Primitive and Black Box Usage:`
362			`------------------------------`
363			`# BELS : 15403`
364			`# INV : 1`
365			`# LUT2 : 810`
366			`# LUT3 : 320`
367			`# LUT4 : 1600`
368			`# LUT5 : 1040`
369			`# LUT6 : 6832`
370			`# MUXF7 : 3200`
371			`# MUXF8 : 1600`
372			`# FlipFlops/Latches : 10769`
373			`# FDC : 81`
374			`# FDCE : 10688`
375			`# Clock Buffers : 2`
376			`# BUFG : 1`
377			`# BUFGP : 1`
378			`# IO Buffers : 388`
379			`# IBUF : 259`
380			`# OBUF : 129`
381
382			`Device utilization summary:`
383			`---------------------------`
384
385			`Selected Device : 6vcx240tff784-2`
386
387
388			`Slice Logic Utilization:`
389			`Number of Slice Registers: 10769 out of 301440 3%`
390			`Number of Slice LUTs: 10603 out of 150720 7%`
391			`Number used as Logic: 10603 out of 150720 7%`
392
393			`Slice Logic Distribution:`
394			`Number of LUT Flip Flop pairs used: 15921`
395			`Number with an unused Flip Flop: 5152 out of 15921 32%`
396			`Number with an unused LUT: 5318 out of 15921 33%`
397			`Number of fully used LUT-FF pairs: 5451 out of 15921 34%`
398			`Number of unique control sets: 82`
399
400			`IO Utilization:`
401			`Number of IOs: 389`
402			`Number of bonded IOBs: 389 out of 400 97%`
403
404			`Specific Feature Utilization:`
405			`Number of BUFG/BUFGCTRLs: 2 out of 32 6%`
406
407			`---------------------------`
408			`Partition Resource Summary:`
409			`---------------------------`
410
411			`No Partitions were found in this design.`
412
413			`---------------------------`
414
415
416			`=========================================================================`
417			`Timing Report`
418
419			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
420			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
421			`GENERATED AFTER PLACE-and-ROUTE.`
422
423			`Clock Information:`
424			`------------------`
425			`-----------------------------------+------------------------+-------+`
426			`Clock Signal \| Clock buffer(FF name) \| Load \|`
427			`-----------------------------------+------------------------+-------+`
428			`clk \| BUFGP \| 10769 \|`
429			`-----------------------------------+------------------------+-------+`
430
431			`Asynchronous Control Signals Information:`
432			`----------------------------------------`
433			`No asynchronous control signals found in this design`
434
435			`Timing Summary:`
436			`---------------`
437			`Speed Grade: -2`
438
439			`Minimum period: 1.564ns (Maximum Frequency: 639.391MHz)`
440			`Minimum input arrival time before clock: 1.252ns`
441			`Maximum output required time after clock: 0.664ns`
442			`Maximum combinational path delay: No path found`
443
444			`Timing Details:`
445			`---------------`
446			`All values displayed in nanoseconds (ns)`
447
448			`=========================================================================`
449			`Timing constraint: Default period analysis for Clock 'clk'`
450			`Clock period: 1.564ns (frequency: 639.391MHz)`
451			`Total number of paths / destination ports: 75065 / 20943`
452			`-------------------------------------------------------------------------`
453			`Delay: 1.564ns (Levels of Logic = 3)`
454			`Source: U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (FF)`
455			`Destination: U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7 (FF)`
456			`Source Clock: clk rising`
457			`Destination Clock: clk rising`
458
459			`Data Path: U_KEYEXP/RKGEN_U0/Key_FirstStage_24 to U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7`
460			`Gate Net`
461			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
462			`---------------------------------------- ------------`
463			`FDCE:C->Q 33 0.317 0.826 U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (U_KEYEXP/RKGEN_U0/Key_FirstStage_24)`
464			`LUT6:I0->O 1 0.061 0.000 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23)`
465			`MUXF7:I1->O 1 0.211 0.000 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f7_0 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f71)`
466			`MUXF8:I0->O 1 0.149 0.000 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f8 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/addr[7]_GND_5_o_wide_mux_0_OUT<1>)`
467			`FDCE:D -0.002 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_1`
468			`----------------------------------------`
469			`Total 1.564ns (0.738ns logic, 0.826ns route)`
470			`(47.2% logic, 52.8% route)`
471
472			`=========================================================================`
473			`Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'`
474			`Total number of paths / destination ports: 771 / 514`
475			`-------------------------------------------------------------------------`
476			`Offset: 1.252ns (Levels of Logic = 2)`
477			`Source: cipherkey_valid_in (PAD)`
478			`Destination: U0_ARK/data_out_127 (FF)`
479			`Destination Clock: clk rising`
480
481			`Data Path: cipherkey_valid_in to U0_ARK/data_out_127`
482			`Gate Net`
483			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
484			`---------------------------------------- ------------`
485			`IBUF:I->O 130 0.003 0.505 cipherkey_valid_in_IBUF (cipherkey_valid_in_IBUF)`
486			`LUT2:I1->O 129 0.061 0.487 U0_ARK/data_valid_in_key_valid_in_AND_2_o1 (U0_ARK/data_valid_in_key_valid_in_AND_2_o)`
487			`FDCE:CE 0.196 U0_ARK/data_out_0`
488			`----------------------------------------`
489			`Total 1.252ns (0.260ns logic, 0.992ns route)`
490			`(20.8% logic, 79.2% route)`
491
492			`=========================================================================`
493			`Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'`
494			`Total number of paths / destination ports: 129 / 129`
495			`-------------------------------------------------------------------------`
496			`Offset: 0.664ns (Levels of Logic = 1)`
497			`Source: U_KEY/data_out_127 (FF)`
498			`Destination: cipher_text<127> (PAD)`
499			`Source Clock: clk rising`
500
501			`Data Path: U_KEY/data_out_127 to cipher_text<127>`
502			`Gate Net`
503			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
504			`---------------------------------------- ------------`
505			`FDCE:C->Q 2 0.317 0.344 U_KEY/data_out_127 (U_KEY/data_out_127)`
506			`OBUF:I->O 0.003 cipher_text_127_OBUF (cipher_text<127>)`
507			`----------------------------------------`
508			`Total 0.664ns (0.320ns logic, 0.344ns route)`
509			`(48.2% logic, 51.8% route)`
510
511			`=========================================================================`
512
513
514			`Total REAL time to Xst completion: 106.00 secs`
515			`Total CPU time to Xst completion: 105.60 secs`
516
517			`-->`
518
519			`Total memory usage is 397192 kilobytes`
520
521			`Number of errors : 0 ( 0 filtered)`
522			`Number of warnings : 0 ( 0 filtered)`
523			`Number of infos : 2 ( 0 filtered)`
524