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[/] [aes-128_pipelined_encryption/] [trunk/] [rtl/] [ShiftRows.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Amr_Salah
/*
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Project         : AES
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Standard doc.   : FIPS 197
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Module name     : ShiftRows block
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Dependancy      :
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Design doc.     :
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References      :
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Description     : this module is used to arrange data in the state array
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                  and shifting rows of this array as declared on the standard document
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Owner           : Amr Salah
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*/
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`timescale 1 ns/1 ps
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module ShiftRows
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#
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(
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parameter DATA_W = 128       //data width
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)
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(
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input clk,                  //system clock
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input reset,                //asynch active low reset
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input valid_in,             //input valid signal   
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input [DATA_W-1:0] data_in,  //input data
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output reg valid_out,         //output valid signal
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output reg [DATA_W-1:0] data_out //output data
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)
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;
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wire [7:0] State [0:15];   //array of wires to form state array     
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genvar i ;
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generate
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// filling state array as each row represents one byte ex: state[0] means first byte and so on
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for(i=0;i<=15;i=i+1) begin :STATE
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 assign State[i]= data_in[(((15-i)*8)+7):((15-i)*8)];
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end
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endgenerate
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always @(posedge clk or negedge reset)
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if(!reset)begin
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    valid_out <= 1'b0;
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    data_out <= 'b0;
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end else begin
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 if(valid_in)begin   //shifting state rows as delared in fips197 standard document
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    data_out[(15*8)+7:(12*8)] <= {State[0],State[5],State[10],State[15]};
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    data_out[(11*8)+7:(8*8)] <= {State[4],State[9],State[14],State[3]};
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    data_out[(7*8)+7:(4*8)]  <= {State[8],State[13],State[2],State[7]};
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    data_out[(3*8)+7:(0*8)]  <=  {State[12],State[1],State[6],State[11]};
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 end
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    valid_out <= valid_in;
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end
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endmodule
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