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-- Organization: www.opendsp.pl
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-- Engineer: Jerzy Gbur
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--
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-- Create Date: 2006-06-18 18:44:02
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-- Design Name: AES_128_192_256
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-- Module Name: aes_dec
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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-- State Table index
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-- ---------------------
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-- | 0 | 4 | 8 | 12 |
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-- ---------------------
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-- | 1 | 5 | 9 | 13 |
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-- ---------------------
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-- | 2 | 6 | 10 | 14 |
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-- ---------------------
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-- | 3 | 7 | 11 | 15 |
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-- ---------------------
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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-- http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library WORK;
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use WORK.aes_pkg.ALL;
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entity aes_dec is
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generic
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(
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KEY_SIZE : in integer range 0 to 2 := 2 -- 0-128; 1-192; 2-256
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);
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port
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(
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DATA_I : in std_logic_vector(7 downto 0);
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VALID_DATA_I : in std_logic;
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KEY_I : in std_logic_vector(7 downto 0);
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VALID_KEY_I : in std_logic;
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RESET_I : in std_logic;
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CLK_I : in std_logic;
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CE_I : in std_logic;
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KEY_READY_O : out std_logic;
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VALID_O : out std_logic;
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DATA_O : out std_logic_vector(7 downto 0)
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);
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end aes_dec;
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architecture Behavioral of aes_dec is
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signal rom_INV_SBOX : type_SBOX;
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signal v_CNT4 : std_logic_vector(1 downto 0);
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signal STATE_TABLE1 : type_STATE_TABLE;
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signal t_STATE_RAM0 : type_STATE_RAM;
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signal v_KEY_COLUMN : std_logic_vector(31 downto 0);
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signal v_DATA_COLUMN : std_logic_vector(31 downto 0);
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signal FF_VALID_DATA : std_logic;
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signal v_KEY_NUMB : std_logic_vector(5 downto 0);
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signal v_INV_KEY_NUMB : std_logic_vector(5 downto 0);
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signal i_MAX_ROUND : integer range 0 to 14;
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signal i_ROUND : integer range 0 to 14;
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signal SRAM_WREN0 : std_logic;
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signal GET_KEY : std_logic;
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signal FF_GET_KEY : std_logic;
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signal CALCULATION : std_logic;
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signal LAST_ROUND : std_logic;
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signal i_RAM_ADDR_RD0 : integer range 0 to 3;
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signal i_RAM_ADDR_WR0 : integer range 0 to 3;
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signal v_RAM_OUT0 : std_logic_vector(31 downto 0);
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signal v_RAM_IN0 : std_logic_vector(31 downto 0);
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signal v_CALCULATION_CNTR : std_logic_vector(7 downto 0);
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type type_temp is array (0 to 15) of std_logic_vector(7 downto 0);
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signal SC_2 : type_temp;
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signal SC_4 : type_temp;
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signal SC_8 : type_temp;
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signal TMP_STATE : type_temp;
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begin
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i_MAX_ROUND <= 8 when KEY_SIZE = 0 else
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10 when KEY_SIZE = 1 else
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12 when KEY_SIZE = 2 else
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8;
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--****************************************************************************--
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--* Key production *--
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--****************************************************************************--
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KEXP0:
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key_expansion
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GENERIC MAP
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(
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KEY_SIZE => KEY_SIZE
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)
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PORT MAP (
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KEY_I => KEY_I,
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VALID_KEY_I => VALID_KEY_I,
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CLK_I => CLK_I,
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RESET_I => RESET_I,
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CE_I => CE_I,
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DONE_O => KEY_READY_O,
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GET_KEY_I => GET_KEY,
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KEY_NUMB_I => v_INV_KEY_NUMB,
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KEY_EXP_O => v_KEY_COLUMN
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);
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v_INV_KEY_NUMB <= v_KEY_NUMB(5 downto 2) & not v_KEY_NUMB(1) & not v_KEY_NUMB(0);
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--****************************************************************************--
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--* Incomming data *--
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--****************************************************************************--
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P0001:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if VALID_DATA_I = '1' then
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if v_CNT4 = "00" then
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v_DATA_COLUMN(7 downto 0) <= DATA_I;
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elsif v_CNT4 = "01" then
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v_DATA_COLUMN(15 downto 8) <= DATA_I;
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elsif v_CNT4 = "10" then
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v_DATA_COLUMN(23 downto 16) <= DATA_I;
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elsif v_CNT4 = "11" then
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v_DATA_COLUMN(31 downto 24) <= DATA_I;
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end if;
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end if;
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end if;
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end process;
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P0002:
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process (CLK_I)
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begin
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if rising_edge(CLK_I) then
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if CE_I = '1' then
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if VALID_DATA_I = '1' then
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v_CNT4 <= v_CNT4 + 1;
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else
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v_CNT4 <= "00";
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* Get Key *--
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--****************************************************************************--
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P0003:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if VALID_DATA_I = '1' and v_CNT4 = "10" then
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GET_KEY <= '1';
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elsif v_CALCULATION_CNTR = x"04" or v_CALCULATION_CNTR = x"05" or v_CALCULATION_CNTR = x"06" or v_CALCULATION_CNTR = x"07" then
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GET_KEY <= '1';
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else
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GET_KEY <= '0';
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* Address for 32bit words of KEY *--
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--****************************************************************************--
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P0004:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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if KEY_SIZE = 0 then
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v_KEY_NUMB <= "101011";
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elsif KEY_SIZE = 1 then
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v_KEY_NUMB <= "110011";
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elsif KEY_SIZE = 2 then
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v_KEY_NUMB <= "111011";
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end if;
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elsif CE_I = '1' then
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if VALID_DATA_I = '1' and FF_VALID_DATA = '0' then
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if KEY_SIZE = 0 then
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v_KEY_NUMB <= "101011";
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elsif KEY_SIZE = 1 then
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v_KEY_NUMB <= "110011";
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elsif KEY_SIZE = 2 then
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v_KEY_NUMB <= "111011";
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end if;
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elsif GET_KEY = '1' then
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v_KEY_NUMB <= v_KEY_NUMB - 1;
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* Rom - invert TABLE *--
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--****************************************************************************--
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rom_INV_SBOX <= c_SBOX_INV;
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--****************************************************************************--
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--* State RAM *--
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--****************************************************************************--
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ST_RAM0:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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-- WRITTING ADDERSS
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if RESET_I = '1' then
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i_RAM_ADDR_WR0 <= 0;
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i_RAM_ADDR_RD0 <= 0;
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elsif CE_I = '1' then
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if VALID_DATA_I = '1' and FF_VALID_DATA = '0' then
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i_RAM_ADDR_WR0 <= 0;
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elsif SRAM_WREN0 = '1' then
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if i_RAM_ADDR_WR0 = 3 then
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i_RAM_ADDR_WR0 <= 0;
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else
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i_RAM_ADDR_WR0 <= i_RAM_ADDR_WR0 + 1;
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end if;
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end if;
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end if;
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-- RAM
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if CE_I = '1' then
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if SRAM_WREN0 = '1' then
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t_STATE_RAM0(i_RAM_ADDR_WR0) <= v_RAM_IN0;
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end if;
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v_RAM_OUT0 <= t_STATE_RAM0(i_RAM_ADDR_RD0);
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end if;
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if CE_I = '1' then
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FF_GET_KEY <= GET_KEY;
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SRAM_WREN0 <= FF_GET_KEY;
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end if;
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-- READING ADDRESS
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if CE_I = '1' then
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if v_CALCULATION_CNTR = x"01" or v_CALCULATION_CNTR = x"02" or v_CALCULATION_CNTR = x"03" then
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i_RAM_ADDR_RD0 <= i_RAM_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"00" then
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i_RAM_ADDR_RD0 <= 0;
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* v_RAM_IN0 *--
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--****************************************************************************--
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P0005:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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v_RAM_IN0 <= (others => '0');
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elsif CE_I = '1' then
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FF_VALID_DATA <= VALID_DATA_I;
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if FF_VALID_DATA = '1' and v_CNT4 = "00" then
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v_RAM_IN0 <= v_KEY_COLUMN xor v_DATA_COLUMN;
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elsif LAST_ROUND = '0' then
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if v_CALCULATION_CNTR = x"06" then
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v_RAM_IN0(7 downto 0) <= SC_2(0) xor SC_4(0) xor SC_8(0) --E
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xor SC_2(1) xor SC_8(1) xor TMP_STATE(1) --B
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xor SC_4(2) xor SC_8(2) xor TMP_STATE(2) --D
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xor SC_8(3) xor TMP_STATE(3); --9
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v_RAM_IN0(15 downto 8) <= SC_8(0) xor TMP_STATE(0) --9
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xor SC_8(1) xor SC_4(1) xor SC_2(1) --E
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xor SC_8(2) xor SC_2(2) xor TMP_STATE(2) --B
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xor SC_8(3) xor SC_4(3) xor TMP_STATE(3); --D
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v_RAM_IN0(23 downto 16) <= SC_8(0) xor SC_4(0) xor TMP_STATE(0) --D
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xor SC_8(1) xor TMP_STATE(1) --9
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xor SC_8(2) xor SC_4(2) xor SC_2(2) --E
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xor SC_8(3) xor SC_2(3) xor TMP_STATE(3); --B
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v_RAM_IN0(31 downto 24) <= SC_8(0) xor SC_2(0) xor TMP_STATE(0) --B
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xor SC_8(1) xor SC_4(1) xor TMP_STATE(1) --D
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xor SC_8(2) xor TMP_STATE(2) --9
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xor SC_8(3) xor SC_4(3) xor SC_2(3); --E
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elsif v_CALCULATION_CNTR = x"07" then
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v_RAM_IN0(7 downto 0) <= SC_2(4) xor SC_4(4) xor SC_8(4) --E
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xor SC_2(5) xor SC_8(5) xor TMP_STATE(5) --B
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xor SC_4(6) xor SC_8(6) xor TMP_STATE(6) --D
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xor SC_8(7) xor TMP_STATE(7); --9
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v_RAM_IN0(15 downto 8) <= SC_8(4) xor TMP_STATE(4) --9
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xor SC_8(5) xor SC_4(5) xor SC_2(5) --E
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xor SC_8(6) xor SC_2(6) xor TMP_STATE(6) --B
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xor SC_8(7) xor SC_4(7) xor TMP_STATE(7); --D
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v_RAM_IN0(23 downto 16) <= SC_8(4) xor SC_4(4) xor TMP_STATE(4) --D
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xor SC_8(5) xor TMP_STATE(5) --9
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xor SC_8(6) xor SC_4(6) xor SC_2(6) --E
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xor SC_8(7) xor SC_2(7) xor TMP_STATE(7); --B
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v_RAM_IN0(31 downto 24) <= SC_8(4) xor SC_2(4) xor TMP_STATE(4) --B
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xor SC_8(5) xor SC_4(5) xor TMP_STATE(5) --D
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xor SC_8(6) xor TMP_STATE(6) --9
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|
|
xor SC_8(7) xor SC_4(7) xor SC_2(7); --E
|
| 326 |
|
|
elsif v_CALCULATION_CNTR = x"08" then
|
| 327 |
|
|
v_RAM_IN0(7 downto 0) <= SC_2(8) xor SC_4(8) xor SC_8(8) --E
|
| 328 |
|
|
xor SC_2(9) xor SC_8(9) xor TMP_STATE(9) --B
|
| 329 |
|
|
xor SC_4(10) xor SC_8(10) xor TMP_STATE(10) --D
|
| 330 |
|
|
xor SC_8(11) xor TMP_STATE(11); --9
|
| 331 |
|
|
v_RAM_IN0(15 downto 8) <= SC_8(8) xor TMP_STATE(8) --9
|
| 332 |
|
|
xor SC_8(9) xor SC_4(9) xor SC_2(9) --E
|
| 333 |
|
|
xor SC_8(10) xor SC_2(10) xor TMP_STATE(10) --B
|
| 334 |
|
|
xor SC_8(11) xor SC_4(11) xor TMP_STATE(11); --D
|
| 335 |
|
|
v_RAM_IN0(23 downto 16) <= SC_8(8) xor SC_4(8) xor TMP_STATE(8) --D
|
| 336 |
|
|
xor SC_8(9) xor TMP_STATE(9) --9
|
| 337 |
|
|
xor SC_8(10) xor SC_4(10) xor SC_2(10) --E
|
| 338 |
|
|
xor SC_8(11) xor SC_2(11) xor TMP_STATE(11); --B
|
| 339 |
|
|
v_RAM_IN0(31 downto 24) <= SC_8(8) xor SC_2(8) xor TMP_STATE(8) --B
|
| 340 |
|
|
xor SC_8(9) xor SC_4(9) xor TMP_STATE(9) --D
|
| 341 |
|
|
xor SC_8(10) xor TMP_STATE(10) --9
|
| 342 |
|
|
xor SC_8(11) xor SC_4(11) xor SC_2(11); --E
|
| 343 |
|
|
elsif v_CALCULATION_CNTR = x"09" then
|
| 344 |
|
|
v_RAM_IN0(7 downto 0) <= SC_2(12) xor SC_4(12) xor SC_8(12) --E
|
| 345 |
|
|
xor SC_2(13) xor SC_8(13) xor TMP_STATE(13) --B
|
| 346 |
|
|
xor SC_4(14) xor SC_8(14) xor TMP_STATE(14) --D
|
| 347 |
|
|
xor SC_8(15) xor TMP_STATE(15); --9
|
| 348 |
|
|
v_RAM_IN0(15 downto 8) <= SC_8(12) xor TMP_STATE(12) --9
|
| 349 |
|
|
xor SC_8(13) xor SC_4(13) xor SC_2(13) --E
|
| 350 |
|
|
xor SC_8(14) xor SC_2(14) xor TMP_STATE(14) --B
|
| 351 |
|
|
xor SC_8(15) xor SC_4(15) xor TMP_STATE(15); --D
|
| 352 |
|
|
v_RAM_IN0(23 downto 16) <= SC_8(12) xor SC_4(12) xor TMP_STATE(12) --D
|
| 353 |
|
|
xor SC_8(13) xor TMP_STATE(13) --9
|
| 354 |
|
|
xor SC_8(14) xor SC_4(14) xor SC_2(14) --E
|
| 355 |
|
|
xor SC_8(15) xor SC_2(15) xor TMP_STATE(15); --B
|
| 356 |
|
|
v_RAM_IN0(31 downto 24) <= SC_8(12) xor SC_2(12) xor TMP_STATE(12) --B
|
| 357 |
|
|
xor SC_8(13) xor SC_4(13) xor TMP_STATE(13) --D
|
| 358 |
|
|
xor SC_8(14) xor TMP_STATE(14) --9
|
| 359 |
|
|
xor SC_8(15) xor SC_4(15) xor SC_2(15); --E
|
| 360 |
|
|
end if;
|
| 361 |
|
|
|
| 362 |
|
|
end if;
|
| 363 |
|
|
end if;
|
| 364 |
|
|
end if;
|
| 365 |
|
|
end process;
|
| 366 |
|
|
|
| 367 |
|
|
G0001:
|
| 368 |
|
|
for i in 0 to 3 generate
|
| 369 |
|
|
G0002:
|
| 370 |
|
|
for j in 0 to 3 generate
|
| 371 |
|
|
TMP_STATE(i*4+j) <= STATE_TABLE1(i*4+j) xor v_KEY_COLUMN(j*8+7 downto j*8);
|
| 372 |
|
|
end generate;
|
| 373 |
|
|
end generate;
|
| 374 |
|
|
|
| 375 |
|
|
-- TMP_STATE(0) <= STATE_TABLE1(0) xor v_KEY_COLUMN(7 downto 0);
|
| 376 |
|
|
-- TMP_STATE(1) <= STATE_TABLE1(1) xor v_KEY_COLUMN(15 downto 8);
|
| 377 |
|
|
-- TMP_STATE(2) <= STATE_TABLE1(2) xor v_KEY_COLUMN(23 downto 16);
|
| 378 |
|
|
-- TMP_STATE(3) <= STATE_TABLE1(3) xor v_KEY_COLUMN(31 downto 24);
|
| 379 |
|
|
-- TMP_STATE(4) <= STATE_TABLE1(4) xor v_KEY_COLUMN(7 downto 0);
|
| 380 |
|
|
-- TMP_STATE(5) <= STATE_TABLE1(5) xor v_KEY_COLUMN(15 downto 8);
|
| 381 |
|
|
-- TMP_STATE(6) <= STATE_TABLE1(6) xor v_KEY_COLUMN(23 downto 16);
|
| 382 |
|
|
-- TMP_STATE(7) <= STATE_TABLE1(7) xor v_KEY_COLUMN(31 downto 24);
|
| 383 |
|
|
-- TMP_STATE(8) <= STATE_TABLE1(8) xor v_KEY_COLUMN(7 downto 0);
|
| 384 |
|
|
-- TMP_STATE(9) <= STATE_TABLE1(9) xor v_KEY_COLUMN(15 downto 8);
|
| 385 |
|
|
-- TMP_STATE(10) <= STATE_TABLE1(10) xor v_KEY_COLUMN(23 downto 16);
|
| 386 |
|
|
-- TMP_STATE(11) <= STATE_TABLE1(11) xor v_KEY_COLUMN(31 downto 24);
|
| 387 |
|
|
-- TMP_STATE(12) <= STATE_TABLE1(12) xor v_KEY_COLUMN(7 downto 0);
|
| 388 |
|
|
-- TMP_STATE(13) <= STATE_TABLE1(13) xor v_KEY_COLUMN(15 downto 8);
|
| 389 |
|
|
-- TMP_STATE(14) <= STATE_TABLE1(14) xor v_KEY_COLUMN(23 downto 16);
|
| 390 |
|
|
-- TMP_STATE(15) <= STATE_TABLE1(15) xor v_KEY_COLUMN(31 downto 24);
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
G0000:
|
| 394 |
|
|
for i in 0 to 15 generate
|
| 395 |
|
|
|
| 396 |
|
|
SC_2(i) <= (x"1B" xor (TMP_STATE(i)(6 downto 0) & "0")) when TMP_STATE(i)(7) = '1' else (TMP_STATE(i)(6 downto 0) & "0");
|
| 397 |
|
|
SC_4(i) <= (x"1B" xor (SC_2(i)(6 downto 0) & "0")) when SC_2(i)(7) = '1' else (SC_2(i)(6 downto 0) & "0");
|
| 398 |
|
|
SC_8(i) <= (x"1B" xor (SC_4(i)(6 downto 0) & "0")) when SC_4(i)(7) = '1' else (SC_4(i)(6 downto 0) & "0");
|
| 399 |
|
|
|
| 400 |
|
|
end generate;
|
| 401 |
|
|
|
| 402 |
|
|
--****************************************************************************--
|
| 403 |
|
|
--* CALCULATION *--
|
| 404 |
|
|
--****************************************************************************--
|
| 405 |
|
|
|
| 406 |
|
|
P0006:
|
| 407 |
|
|
process(CLK_I)
|
| 408 |
|
|
begin
|
| 409 |
|
|
if rising_edge(CLK_I) then
|
| 410 |
|
|
if RESET_I = '1' then
|
| 411 |
|
|
CALCULATION <= '0';
|
| 412 |
|
|
elsif CE_I = '1' then
|
| 413 |
|
|
|
| 414 |
|
|
if FF_VALID_DATA = '1' and VALID_DATA_I = '0' then
|
| 415 |
|
|
CALCULATION <= '1';
|
| 416 |
|
|
elsif LAST_ROUND = '1' and v_CALCULATION_CNTR = x"16" then
|
| 417 |
|
|
CALCULATION <= '0';
|
| 418 |
|
|
end if;
|
| 419 |
|
|
|
| 420 |
|
|
end if;
|
| 421 |
|
|
end if;
|
| 422 |
|
|
end process;
|
| 423 |
|
|
|
| 424 |
|
|
P0007:
|
| 425 |
|
|
process(CLK_I)
|
| 426 |
|
|
begin
|
| 427 |
|
|
if rising_edge(CLK_I) then
|
| 428 |
|
|
if RESET_I = '1' then
|
| 429 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 430 |
|
|
LAST_ROUND <= '0';
|
| 431 |
|
|
i_ROUND <= 0;
|
| 432 |
|
|
elsif CE_I = '1' then
|
| 433 |
|
|
if CALCULATION = '1' then
|
| 434 |
|
|
if v_CALCULATION_CNTR = x"09" and LAST_ROUND = '0' then
|
| 435 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 436 |
|
|
i_ROUND <= i_ROUND + 1;
|
| 437 |
|
|
|
| 438 |
|
|
if i_ROUND = i_MAX_ROUND then
|
| 439 |
|
|
LAST_ROUND <= '1';
|
| 440 |
|
|
end if;
|
| 441 |
|
|
elsif v_CALCULATION_CNTR = x"16" and LAST_ROUND = '1' then
|
| 442 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 443 |
|
|
i_ROUND <= i_ROUND + 1;
|
| 444 |
|
|
|
| 445 |
|
|
else
|
| 446 |
|
|
v_CALCULATION_CNTR <= v_CALCULATION_CNTR + 1;
|
| 447 |
|
|
end if;
|
| 448 |
|
|
else
|
| 449 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 450 |
|
|
i_ROUND <= 0;
|
| 451 |
|
|
LAST_ROUND <= '0';
|
| 452 |
|
|
end if;
|
| 453 |
|
|
end if;
|
| 454 |
|
|
end if;
|
| 455 |
|
|
end process;
|
| 456 |
|
|
|
| 457 |
|
|
--****************************************************************************--
|
| 458 |
|
|
--* STATE_TABLE1 *--
|
| 459 |
|
|
--****************************************************************************--
|
| 460 |
|
|
|
| 461 |
|
|
P0008:
|
| 462 |
|
|
process (CLK_I)
|
| 463 |
|
|
begin
|
| 464 |
|
|
if rising_edge(CLK_I) then
|
| 465 |
|
|
-- InvShiftRows
|
| 466 |
|
|
if v_CALCULATION_CNTR = x"02" then
|
| 467 |
|
|
STATE_TABLE1(0) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 468 |
|
|
STATE_TABLE1(5) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 469 |
|
|
STATE_TABLE1(10) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 470 |
|
|
STATE_TABLE1(15) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 471 |
|
|
elsif v_CALCULATION_CNTR = x"03" then
|
| 472 |
|
|
STATE_TABLE1(4) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 473 |
|
|
STATE_TABLE1(9) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 474 |
|
|
STATE_TABLE1(14) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 475 |
|
|
STATE_TABLE1(3) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 476 |
|
|
elsif v_CALCULATION_CNTR = x"04" then
|
| 477 |
|
|
STATE_TABLE1(8) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 478 |
|
|
STATE_TABLE1(13) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 479 |
|
|
STATE_TABLE1(2) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 480 |
|
|
STATE_TABLE1(7) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 481 |
|
|
elsif v_CALCULATION_CNTR = x"05" then
|
| 482 |
|
|
STATE_TABLE1(12) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 483 |
|
|
STATE_TABLE1(1) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 484 |
|
|
STATE_TABLE1(6) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 485 |
|
|
STATE_TABLE1(11) <= rom_INV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 486 |
|
|
end if;
|
| 487 |
|
|
|
| 488 |
|
|
if LAST_ROUND = '1' then
|
| 489 |
|
|
|
| 490 |
|
|
if v_CALCULATION_CNTR = x"06" then
|
| 491 |
|
|
|
| 492 |
|
|
STATE_TABLE1(0) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(0);
|
| 493 |
|
|
STATE_TABLE1(1) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(1);
|
| 494 |
|
|
STATE_TABLE1(2) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(2);
|
| 495 |
|
|
STATE_TABLE1(3) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(3);
|
| 496 |
|
|
elsif v_CALCULATION_CNTR = x"07" then
|
| 497 |
|
|
DATA_O <= STATE_TABLE1(0);
|
| 498 |
|
|
VALID_O <= '1';
|
| 499 |
|
|
|
| 500 |
|
|
STATE_TABLE1(4) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(4);
|
| 501 |
|
|
STATE_TABLE1(5) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(5);
|
| 502 |
|
|
STATE_TABLE1(6) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(6);
|
| 503 |
|
|
STATE_TABLE1(7) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(7);
|
| 504 |
|
|
elsif v_CALCULATION_CNTR = x"08" then
|
| 505 |
|
|
DATA_O <= STATE_TABLE1(1);
|
| 506 |
|
|
VALID_O <= '1';
|
| 507 |
|
|
|
| 508 |
|
|
STATE_TABLE1(8) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(8);
|
| 509 |
|
|
STATE_TABLE1(9) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(9);
|
| 510 |
|
|
STATE_TABLE1(10) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(10);
|
| 511 |
|
|
STATE_TABLE1(11) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(11);
|
| 512 |
|
|
elsif v_CALCULATION_CNTR = x"09" then
|
| 513 |
|
|
DATA_O <= STATE_TABLE1(2);
|
| 514 |
|
|
VALID_O <= '1';
|
| 515 |
|
|
|
| 516 |
|
|
STATE_TABLE1(12) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(12);
|
| 517 |
|
|
STATE_TABLE1(13) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(13);
|
| 518 |
|
|
STATE_TABLE1(14) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(14);
|
| 519 |
|
|
STATE_TABLE1(15) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(15);
|
| 520 |
|
|
elsif v_CALCULATION_CNTR = x"0A" then
|
| 521 |
|
|
DATA_O <= STATE_TABLE1(3);
|
| 522 |
|
|
VALID_O <= '1';
|
| 523 |
|
|
elsif v_CALCULATION_CNTR = x"0B" then
|
| 524 |
|
|
DATA_O <= STATE_TABLE1(4);
|
| 525 |
|
|
VALID_O <= '1';
|
| 526 |
|
|
elsif v_CALCULATION_CNTR = x"0C" then
|
| 527 |
|
|
DATA_O <= STATE_TABLE1(5);
|
| 528 |
|
|
VALID_O <= '1';
|
| 529 |
|
|
elsif v_CALCULATION_CNTR = x"0D" then
|
| 530 |
|
|
DATA_O <= STATE_TABLE1(6);
|
| 531 |
|
|
VALID_O <= '1';
|
| 532 |
|
|
elsif v_CALCULATION_CNTR = x"0E" then
|
| 533 |
|
|
DATA_O <= STATE_TABLE1(7);
|
| 534 |
|
|
VALID_O <= '1';
|
| 535 |
|
|
elsif v_CALCULATION_CNTR = x"0F" then
|
| 536 |
|
|
DATA_O <= STATE_TABLE1(8);
|
| 537 |
|
|
VALID_O <= '1';
|
| 538 |
|
|
elsif v_CALCULATION_CNTR = x"10" then
|
| 539 |
|
|
DATA_O <= STATE_TABLE1(9);
|
| 540 |
|
|
VALID_O <= '1';
|
| 541 |
|
|
elsif v_CALCULATION_CNTR = x"11" then
|
| 542 |
|
|
DATA_O <= STATE_TABLE1(10);
|
| 543 |
|
|
VALID_O <= '1';
|
| 544 |
|
|
elsif v_CALCULATION_CNTR = x"12" then
|
| 545 |
|
|
DATA_O <= STATE_TABLE1(11);
|
| 546 |
|
|
VALID_O <= '1';
|
| 547 |
|
|
elsif v_CALCULATION_CNTR = x"13" then
|
| 548 |
|
|
DATA_O <= STATE_TABLE1(12);
|
| 549 |
|
|
VALID_O <= '1';
|
| 550 |
|
|
elsif v_CALCULATION_CNTR = x"14" then
|
| 551 |
|
|
DATA_O <= STATE_TABLE1(13);
|
| 552 |
|
|
VALID_O <= '1';
|
| 553 |
|
|
elsif v_CALCULATION_CNTR = x"15" then
|
| 554 |
|
|
DATA_O <= STATE_TABLE1(14);
|
| 555 |
|
|
VALID_O <= '1';
|
| 556 |
|
|
elsif v_CALCULATION_CNTR = x"16" then
|
| 557 |
|
|
DATA_O <= STATE_TABLE1(15);
|
| 558 |
|
|
VALID_O <= '1';
|
| 559 |
|
|
else
|
| 560 |
|
|
DATA_O <= x"00";
|
| 561 |
|
|
VALID_O <= '0';
|
| 562 |
|
|
end if;
|
| 563 |
|
|
else
|
| 564 |
|
|
VALID_O <= '0';
|
| 565 |
|
|
end if;
|
| 566 |
|
|
|
| 567 |
|
|
end if;
|
| 568 |
|
|
end process;
|
| 569 |
|
|
|
| 570 |
|
|
end Behavioral;
|
