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-- Organization: www.opendsp.pl
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-- Engineer: Jerzy Gbur
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--
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-- Create Date: 2006-05-15 20:05:12
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-- Design Name: AES_128_192_256
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-- Module Name: aes
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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-- State Table index
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-- ---------------------
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-- | 0 | 4 | 8 | 12 |
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-- ---------------------
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-- | 1 | 5 | 9 | 13 |
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-- ---------------------
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-- | 2 | 6 | 10 | 14 |
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-- ---------------------
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-- | 3 | 7 | 11 | 15 |
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-- ---------------------
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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-- http://www.csrc.nist.gov/pki/CSOR/algorithms.html
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library WORK;
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use WORK.aes_pkg.ALL;
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entity aes_enc is
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generic
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(
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KEY_SIZE : in integer range 0 to 2 := 0 -- 0-128; 1-192; 2-256
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);
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port
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(
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DATA_I : in std_logic_vector(7 downto 0);
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VALID_DATA_I : in std_logic;
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KEY_I : in std_logic_vector(7 downto 0);
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VALID_KEY_I : in std_logic;
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RESET_I : in std_logic;
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CLK_I : in std_logic;
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CE_I : in std_logic;
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KEY_READY_O : out std_logic;
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VALID_O : out std_logic;
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DATA_O : out std_logic_vector(7 downto 0)
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);
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end aes_enc;
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architecture Behavioral of aes_enc is
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signal rom_FRV_SBOX : type_SBOX;
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signal v_CNT4 : std_logic_vector(1 downto 0);
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signal STATE_TABLE1 : type_STATE_TABLE;
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signal t_STATE_RAM0 : type_STATE_RAM;
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signal v_KEY_COLUMN : std_logic_vector(31 downto 0);
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signal v_DATA_COLUMN : std_logic_vector(31 downto 0);
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signal FF_VALID_DATA : std_logic;
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signal v_KEY_NUMB : std_logic_vector(5 downto 0);
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signal v_C : std_logic_vector(15 downto 0);
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signal i_MAX_ROUND : integer range 0 to 14;
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signal i_ROUND : integer range 0 to 14;
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signal SRAM_WREN0 : std_logic;
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signal GET_KEY : std_logic;
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signal FF_GET_KEY : std_logic;
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signal CALCULATION : std_logic;
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signal LAST_ROUND : std_logic;
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signal i_RAM_ADDR_RD0 : integer range 0 to 3;
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signal i_RAM_ADDR_WR0 : integer range 0 to 3;
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signal v_RAM_OUT0 : std_logic_vector(31 downto 0);
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signal v_RAM_IN0 : std_logic_vector(31 downto 0);
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signal v_CALCULATION_CNTR : std_logic_vector(7 downto 0);
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begin
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i_MAX_ROUND <= 8 when KEY_SIZE = 0 else
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10 when KEY_SIZE = 1 else
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12 when KEY_SIZE = 2 else
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8;
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--****************************************************************************--
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--* Key production *--
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--****************************************************************************--
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KEXP0:
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key_expansion
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GENERIC MAP
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(
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KEY_SIZE => KEY_SIZE
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)
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PORT MAP (
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KEY_I => KEY_I,
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VALID_KEY_I => VALID_KEY_I,
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CLK_I => CLK_I,
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RESET_I => RESET_I,
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CE_I => CE_I,
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DONE_O => KEY_READY_O,
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GET_KEY_I => GET_KEY,
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KEY_NUMB_I => v_KEY_NUMB,
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KEY_EXP_O => v_KEY_COLUMN
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);
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--****************************************************************************--
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--* Incomming data *--
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--****************************************************************************--
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P0001:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if VALID_DATA_I = '1' then
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if v_CNT4 = "00" then
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v_DATA_COLUMN(7 downto 0) <= DATA_I;
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elsif v_CNT4 = "01" then
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v_DATA_COLUMN(15 downto 8) <= DATA_I;
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elsif v_CNT4 = "10" then
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v_DATA_COLUMN(23 downto 16) <= DATA_I;
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elsif v_CNT4 = "11" then
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v_DATA_COLUMN(31 downto 24) <= DATA_I;
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end if;
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end if;
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end if;
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end process;
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P0002:
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process (CLK_I)
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begin
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if rising_edge(CLK_I) then
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if CE_I = '1' then
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if VALID_DATA_I = '1' then
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v_CNT4 <= v_CNT4 + 1;
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else
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v_CNT4 <= "00";
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* Get Key *--
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--****************************************************************************--
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P0003:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if VALID_DATA_I = '1' and v_CNT4 = "10" then
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GET_KEY <= '1';
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elsif v_CALCULATION_CNTR = x"04" or v_CALCULATION_CNTR = x"05" or v_CALCULATION_CNTR = x"06" or v_CALCULATION_CNTR = x"07" then
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GET_KEY <= '1';
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else
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GET_KEY <= '0';
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* Address for 32bit words of KEY *--
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--****************************************************************************--
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P0004:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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v_KEY_NUMB <= (others => '0');
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elsif CE_I = '1' then
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if VALID_DATA_I = '1' and FF_VALID_DATA = '0' then
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v_KEY_NUMB <= (others => '0');
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elsif GET_KEY = '1' then
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v_KEY_NUMB <= v_KEY_NUMB + 1;
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* Rom - forward TABLE *--
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--****************************************************************************--
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rom_FRV_SBOX <= c_SBOX_FRV;
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--****************************************************************************--
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--* State RAM *--
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--****************************************************************************--
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ST_RAM0:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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-- WRITTING ADDERSS
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if RESET_I = '1' then
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i_RAM_ADDR_WR0 <= 0;
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i_RAM_ADDR_RD0 <= 0;
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elsif CE_I = '1' then
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if VALID_DATA_I = '1' and FF_VALID_DATA = '0' then
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i_RAM_ADDR_WR0 <= 0;
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elsif SRAM_WREN0 = '1' then
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if i_RAM_ADDR_WR0 = 3 then
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i_RAM_ADDR_WR0 <= 0;
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else
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i_RAM_ADDR_WR0 <= i_RAM_ADDR_WR0 + 1;
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end if;
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end if;
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end if;
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-- RAM
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if CE_I = '1' then
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if SRAM_WREN0 = '1' then
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t_STATE_RAM0(i_RAM_ADDR_WR0) <= v_RAM_IN0;
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end if;
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v_RAM_OUT0 <= t_STATE_RAM0(i_RAM_ADDR_RD0);
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end if;
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if CE_I = '1' then
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FF_GET_KEY <= GET_KEY;
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SRAM_WREN0 <= FF_GET_KEY;
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end if;
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-- READING ADDRESS
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if CE_I = '1' then
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if v_CALCULATION_CNTR = x"01" or v_CALCULATION_CNTR = x"02" or v_CALCULATION_CNTR = x"03" then
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i_RAM_ADDR_RD0 <= i_RAM_ADDR_RD0 + 1;
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elsif v_CALCULATION_CNTR = x"00" then
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i_RAM_ADDR_RD0 <= 0;
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end if;
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end if;
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end if;
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end process;
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--****************************************************************************--
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--* v_RAM_IN0 *--
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--****************************************************************************--
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P0005:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RESET_I = '1' then
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v_RAM_IN0 <= (others => '0');
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elsif CE_I = '1' then
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FF_VALID_DATA <= VALID_DATA_I;
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if FF_VALID_DATA = '1' and v_CNT4 = "00" then
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v_RAM_IN0 <= v_KEY_COLUMN xor v_DATA_COLUMN;
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elsif LAST_ROUND = '0' then
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if v_CALCULATION_CNTR = x"06" then
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v_RAM_IN0(7 downto 0) <= v_KEY_COLUMN(7 downto 0) xor (STATE_TABLE1(0)(6 downto 0) & "0") xor ((STATE_TABLE1(1)(6 downto 0) & "0") xor STATE_TABLE1(1)) xor STATE_TABLE1(2) xor STATE_TABLE1(3) xor ("000" & v_C(0) & v_C(0) & "0" & v_C(0) & v_C(0));
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v_RAM_IN0(15 downto 8) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(0) xor (STATE_TABLE1(1)(6 downto 0) & "0") xor ((STATE_TABLE1(2)(6 downto 0) & "0") xor STATE_TABLE1(2)) xor STATE_TABLE1(3) xor ("000" & v_C(1) & v_C(1) & "0" & v_C(1) & v_C(1));
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v_RAM_IN0(23 downto 16) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(0) xor STATE_TABLE1(1) xor (STATE_TABLE1(2)(6 downto 0) & "0") xor ((STATE_TABLE1(3)(6 downto 0) & "0") xor STATE_TABLE1(3)) xor ("000" & v_C(2) & v_C(2) & "0" & v_C(2) & v_C(2));
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v_RAM_IN0(31 downto 24) <= v_KEY_COLUMN(31 downto 24) xor ((STATE_TABLE1(0)(6 downto 0) & "0") xor STATE_TABLE1(0)) xor STATE_TABLE1(1) xor STATE_TABLE1(2) xor (STATE_TABLE1(3)(6 downto 0) & "0") xor ("000" & v_C(3) & v_C(3) & "0" & v_C(3) & v_C(3));
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elsif v_CALCULATION_CNTR = x"07" then
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v_RAM_IN0(7 downto 0) <= v_KEY_COLUMN(7 downto 0) xor (STATE_TABLE1(4)(6 downto 0) & "0") xor ((STATE_TABLE1(5)(6 downto 0) & "0") xor STATE_TABLE1(5)) xor STATE_TABLE1(6) xor STATE_TABLE1(7) xor ("000" & v_C(4) & v_C(4) & "0" & v_C(4) & v_C(4));
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v_RAM_IN0(15 downto 8) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(4) xor (STATE_TABLE1(5)(6 downto 0) & "0") xor ((STATE_TABLE1(6)(6 downto 0) & "0") xor STATE_TABLE1(6)) xor STATE_TABLE1(7) xor ("000" & v_C(5) & v_C(5) & "0" & v_C(5) & v_C(5));
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v_RAM_IN0(23 downto 16) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(4) xor STATE_TABLE1(5) xor (STATE_TABLE1(6)(6 downto 0) & "0") xor ((STATE_TABLE1(7)(6 downto 0) & "0") xor STATE_TABLE1(7)) xor ("000" & v_C(6) & v_C(6) & "0" & v_C(6) & v_C(6));
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v_RAM_IN0(31 downto 24) <= v_KEY_COLUMN(31 downto 24) xor ((STATE_TABLE1(4)(6 downto 0) & "0") xor STATE_TABLE1(4)) xor STATE_TABLE1(5) xor STATE_TABLE1(6) xor (STATE_TABLE1(7)(6 downto 0) & "0") xor ("000" & v_C(7) & v_C(7) & "0" & v_C(7) & v_C(7));
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elsif v_CALCULATION_CNTR = x"08" then
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v_RAM_IN0(7 downto 0) <= v_KEY_COLUMN(7 downto 0) xor (STATE_TABLE1(8)(6 downto 0) & "0") xor ((STATE_TABLE1(9)(6 downto 0) & "0") xor STATE_TABLE1(9)) xor STATE_TABLE1(10) xor STATE_TABLE1(11) xor ("000" & v_C(8) & v_C(8) & "0" & v_C(8) & v_C(8));
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v_RAM_IN0(15 downto 8) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(8) xor (STATE_TABLE1(9)(6 downto 0) & "0") xor ((STATE_TABLE1(10)(6 downto 0) & "0") xor STATE_TABLE1(10)) xor STATE_TABLE1(11) xor ("000" & v_C(9) & v_C(9) & "0" & v_C(9) & v_C(9));
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v_RAM_IN0(23 downto 16) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(8) xor STATE_TABLE1(9) xor (STATE_TABLE1(10)(6 downto 0) & "0") xor ((STATE_TABLE1(11)(6 downto 0) & "0") xor STATE_TABLE1(11)) xor ("000" & v_C(10) & v_C(10) & "0" & v_C(10) & v_C(10));
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v_RAM_IN0(31 downto 24) <= v_KEY_COLUMN(31 downto 24) xor ((STATE_TABLE1(8)(6 downto 0) & "0") xor STATE_TABLE1(8)) xor STATE_TABLE1(9) xor STATE_TABLE1(10) xor (STATE_TABLE1(11)(6 downto 0) & "0") xor ("000" & v_C(11) & v_C(11) & "0" & v_C(11) & v_C(11));
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elsif v_CALCULATION_CNTR = x"09" then
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|
|
v_RAM_IN0(7 downto 0) <= v_KEY_COLUMN(7 downto 0) xor (STATE_TABLE1(12)(6 downto 0) & "0") xor ((STATE_TABLE1(13)(6 downto 0) & "0") xor STATE_TABLE1(13))xor STATE_TABLE1(14) xor STATE_TABLE1(15) xor ("000" & v_C(12) & v_C(12) & "0" & v_C(12) & v_C(12));
|
| 289 |
|
|
v_RAM_IN0(15 downto 8) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(12) xor (STATE_TABLE1(13)(6 downto 0) & "0") xor ((STATE_TABLE1(14)(6 downto 0) & "0") xor STATE_TABLE1(14)) xor STATE_TABLE1(15) xor ("000" & v_C(13) & v_C(13) & "0" & v_C(13) & v_C(13));
|
| 290 |
|
|
v_RAM_IN0(23 downto 16) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(12) xor STATE_TABLE1(13) xor (STATE_TABLE1(14)(6 downto 0) & "0") xor ((STATE_TABLE1(15)(6 downto 0) & "0") xor STATE_TABLE1(15)) xor ("000" & v_C(14) & v_C(14) & "0" & v_C(14) & v_C(14));
|
| 291 |
|
|
v_RAM_IN0(31 downto 24) <= v_KEY_COLUMN(31 downto 24) xor ((STATE_TABLE1(12)(6 downto 0) & "0") xor STATE_TABLE1(12)) xor STATE_TABLE1(13) xor STATE_TABLE1(14) xor (STATE_TABLE1(15)(6 downto 0) & "0") xor ("000" & v_C(15) & v_C(15) & "0" & v_C(15) & v_C(15));
|
| 292 |
|
|
end if;
|
| 293 |
|
|
|
| 294 |
|
|
end if;
|
| 295 |
|
|
end if;
|
| 296 |
|
|
end if;
|
| 297 |
|
|
end process;
|
| 298 |
|
|
|
| 299 |
|
|
v_C(0) <= STATE_TABLE1(0)(7) xor STATE_TABLE1(1)(7);
|
| 300 |
|
|
v_C(1) <= STATE_TABLE1(1)(7) xor STATE_TABLE1(2)(7);
|
| 301 |
|
|
v_C(2) <= STATE_TABLE1(2)(7) xor STATE_TABLE1(3)(7);
|
| 302 |
|
|
v_C(3) <= STATE_TABLE1(3)(7) xor STATE_TABLE1(0)(7);
|
| 303 |
|
|
v_C(4) <= STATE_TABLE1(4)(7) xor STATE_TABLE1(5)(7);
|
| 304 |
|
|
v_C(5) <= STATE_TABLE1(5)(7) xor STATE_TABLE1(6)(7);
|
| 305 |
|
|
v_C(6) <= STATE_TABLE1(6)(7) xor STATE_TABLE1(7)(7);
|
| 306 |
|
|
v_C(7) <= STATE_TABLE1(7)(7) xor STATE_TABLE1(4)(7);
|
| 307 |
|
|
v_C(8) <= STATE_TABLE1(8)(7) xor STATE_TABLE1(9)(7);
|
| 308 |
|
|
v_C(9) <= STATE_TABLE1(9)(7) xor STATE_TABLE1(10)(7);
|
| 309 |
|
|
v_C(10) <= STATE_TABLE1(10)(7) xor STATE_TABLE1(11)(7);
|
| 310 |
|
|
v_C(11) <= STATE_TABLE1(11)(7) xor STATE_TABLE1(8)(7);
|
| 311 |
|
|
v_C(12) <= STATE_TABLE1(12)(7) xor STATE_TABLE1(13)(7);
|
| 312 |
|
|
v_C(13) <= STATE_TABLE1(13)(7) xor STATE_TABLE1(14)(7);
|
| 313 |
|
|
v_C(14) <= STATE_TABLE1(14)(7) xor STATE_TABLE1(15)(7);
|
| 314 |
|
|
v_C(15) <= STATE_TABLE1(15)(7) xor STATE_TABLE1(12)(7);
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
|
| 318 |
|
|
--****************************************************************************--
|
| 319 |
|
|
--* CALCULATION *--
|
| 320 |
|
|
--****************************************************************************--
|
| 321 |
|
|
|
| 322 |
|
|
P0006:
|
| 323 |
|
|
process(CLK_I)
|
| 324 |
|
|
begin
|
| 325 |
|
|
if rising_edge(CLK_I) then
|
| 326 |
|
|
if RESET_I = '1' then
|
| 327 |
|
|
CALCULATION <= '0';
|
| 328 |
|
|
elsif CE_I = '1' then
|
| 329 |
|
|
|
| 330 |
|
|
if FF_VALID_DATA = '1' and VALID_DATA_I = '0' then
|
| 331 |
|
|
CALCULATION <= '1';
|
| 332 |
|
|
elsif LAST_ROUND = '1' and v_CALCULATION_CNTR = x"16" then
|
| 333 |
|
|
CALCULATION <= '0';
|
| 334 |
|
|
end if;
|
| 335 |
|
|
|
| 336 |
|
|
end if;
|
| 337 |
|
|
end if;
|
| 338 |
|
|
end process;
|
| 339 |
|
|
|
| 340 |
|
|
P0007:
|
| 341 |
|
|
process(CLK_I)
|
| 342 |
|
|
begin
|
| 343 |
|
|
if rising_edge(CLK_I) then
|
| 344 |
|
|
if RESET_I = '1' then
|
| 345 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 346 |
|
|
LAST_ROUND <= '0';
|
| 347 |
|
|
i_ROUND <= 0;
|
| 348 |
|
|
elsif CE_I = '1' then
|
| 349 |
|
|
if CALCULATION = '1' then
|
| 350 |
|
|
if v_CALCULATION_CNTR = x"09" and LAST_ROUND = '0' then
|
| 351 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 352 |
|
|
i_ROUND <= i_ROUND + 1;
|
| 353 |
|
|
|
| 354 |
|
|
if i_ROUND = i_MAX_ROUND then
|
| 355 |
|
|
LAST_ROUND <= '1';
|
| 356 |
|
|
end if;
|
| 357 |
|
|
elsif v_CALCULATION_CNTR = x"16" and LAST_ROUND = '1' then
|
| 358 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 359 |
|
|
i_ROUND <= i_ROUND + 1;
|
| 360 |
|
|
|
| 361 |
|
|
else
|
| 362 |
|
|
v_CALCULATION_CNTR <= v_CALCULATION_CNTR + 1;
|
| 363 |
|
|
end if;
|
| 364 |
|
|
else
|
| 365 |
|
|
v_CALCULATION_CNTR <= (others => '0');
|
| 366 |
|
|
i_ROUND <= 0;
|
| 367 |
|
|
LAST_ROUND <= '0';
|
| 368 |
|
|
end if;
|
| 369 |
|
|
end if;
|
| 370 |
|
|
end if;
|
| 371 |
|
|
end process;
|
| 372 |
|
|
|
| 373 |
|
|
--****************************************************************************--
|
| 374 |
|
|
--* STATE_TABLE1 *--
|
| 375 |
|
|
--****************************************************************************--
|
| 376 |
|
|
|
| 377 |
|
|
P0008:
|
| 378 |
|
|
process (CLK_I)
|
| 379 |
|
|
begin
|
| 380 |
|
|
if rising_edge(CLK_I) then
|
| 381 |
|
|
if v_CALCULATION_CNTR = x"02" then
|
| 382 |
|
|
STATE_TABLE1(0) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 383 |
|
|
STATE_TABLE1(13) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 384 |
|
|
STATE_TABLE1(10) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 385 |
|
|
STATE_TABLE1(7) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 386 |
|
|
elsif v_CALCULATION_CNTR = x"03" then
|
| 387 |
|
|
STATE_TABLE1(4) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 388 |
|
|
STATE_TABLE1(1) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 389 |
|
|
STATE_TABLE1(14) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 390 |
|
|
STATE_TABLE1(11) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 391 |
|
|
elsif v_CALCULATION_CNTR = x"04" then
|
| 392 |
|
|
STATE_TABLE1(8) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 393 |
|
|
STATE_TABLE1(5) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 394 |
|
|
STATE_TABLE1(2) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 395 |
|
|
STATE_TABLE1(15) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 396 |
|
|
elsif v_CALCULATION_CNTR = x"05" then
|
| 397 |
|
|
STATE_TABLE1(12) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(7 downto 0)));
|
| 398 |
|
|
STATE_TABLE1(9) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(15 downto 8)));
|
| 399 |
|
|
STATE_TABLE1(6) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(23 downto 16)));
|
| 400 |
|
|
STATE_TABLE1(3) <= rom_FRV_SBOX(conv_integer(v_RAM_OUT0(31 downto 24)));
|
| 401 |
|
|
end if;
|
| 402 |
|
|
|
| 403 |
|
|
if LAST_ROUND = '1' then
|
| 404 |
|
|
|
| 405 |
|
|
if v_CALCULATION_CNTR = x"06" then
|
| 406 |
|
|
|
| 407 |
|
|
STATE_TABLE1(0) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(0);
|
| 408 |
|
|
STATE_TABLE1(1) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(1);
|
| 409 |
|
|
STATE_TABLE1(2) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(2);
|
| 410 |
|
|
STATE_TABLE1(3) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(3);
|
| 411 |
|
|
elsif v_CALCULATION_CNTR = x"07" then
|
| 412 |
|
|
DATA_O <= STATE_TABLE1(0);
|
| 413 |
|
|
VALID_O <= '1';
|
| 414 |
|
|
|
| 415 |
|
|
STATE_TABLE1(4) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(4);
|
| 416 |
|
|
STATE_TABLE1(5) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(5);
|
| 417 |
|
|
STATE_TABLE1(6) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(6);
|
| 418 |
|
|
STATE_TABLE1(7) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(7);
|
| 419 |
|
|
elsif v_CALCULATION_CNTR = x"08" then
|
| 420 |
|
|
DATA_O <= STATE_TABLE1(1);
|
| 421 |
|
|
VALID_O <= '1';
|
| 422 |
|
|
|
| 423 |
|
|
STATE_TABLE1(8) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(8);
|
| 424 |
|
|
STATE_TABLE1(9) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(9);
|
| 425 |
|
|
STATE_TABLE1(10) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(10);
|
| 426 |
|
|
STATE_TABLE1(11) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(11);
|
| 427 |
|
|
elsif v_CALCULATION_CNTR = x"09" then
|
| 428 |
|
|
DATA_O <= STATE_TABLE1(2);
|
| 429 |
|
|
VALID_O <= '1';
|
| 430 |
|
|
|
| 431 |
|
|
STATE_TABLE1(12) <= v_KEY_COLUMN(7 downto 0) xor STATE_TABLE1(12);
|
| 432 |
|
|
STATE_TABLE1(13) <= v_KEY_COLUMN(15 downto 8) xor STATE_TABLE1(13);
|
| 433 |
|
|
STATE_TABLE1(14) <= v_KEY_COLUMN(23 downto 16) xor STATE_TABLE1(14);
|
| 434 |
|
|
STATE_TABLE1(15) <= v_KEY_COLUMN(31 downto 24) xor STATE_TABLE1(15);
|
| 435 |
|
|
elsif v_CALCULATION_CNTR = x"0A" then
|
| 436 |
|
|
DATA_O <= STATE_TABLE1(3);
|
| 437 |
|
|
VALID_O <= '1';
|
| 438 |
|
|
elsif v_CALCULATION_CNTR = x"0B" then
|
| 439 |
|
|
DATA_O <= STATE_TABLE1(4);
|
| 440 |
|
|
VALID_O <= '1';
|
| 441 |
|
|
elsif v_CALCULATION_CNTR = x"0C" then
|
| 442 |
|
|
DATA_O <= STATE_TABLE1(5);
|
| 443 |
|
|
VALID_O <= '1';
|
| 444 |
|
|
elsif v_CALCULATION_CNTR = x"0D" then
|
| 445 |
|
|
DATA_O <= STATE_TABLE1(6);
|
| 446 |
|
|
VALID_O <= '1';
|
| 447 |
|
|
elsif v_CALCULATION_CNTR = x"0E" then
|
| 448 |
|
|
DATA_O <= STATE_TABLE1(7);
|
| 449 |
|
|
VALID_O <= '1';
|
| 450 |
|
|
elsif v_CALCULATION_CNTR = x"0F" then
|
| 451 |
|
|
DATA_O <= STATE_TABLE1(8);
|
| 452 |
|
|
VALID_O <= '1';
|
| 453 |
|
|
elsif v_CALCULATION_CNTR = x"10" then
|
| 454 |
|
|
DATA_O <= STATE_TABLE1(9);
|
| 455 |
|
|
VALID_O <= '1';
|
| 456 |
|
|
elsif v_CALCULATION_CNTR = x"11" then
|
| 457 |
|
|
DATA_O <= STATE_TABLE1(10);
|
| 458 |
|
|
VALID_O <= '1';
|
| 459 |
|
|
elsif v_CALCULATION_CNTR = x"12" then
|
| 460 |
|
|
DATA_O <= STATE_TABLE1(11);
|
| 461 |
|
|
VALID_O <= '1';
|
| 462 |
|
|
elsif v_CALCULATION_CNTR = x"13" then
|
| 463 |
|
|
DATA_O <= STATE_TABLE1(12);
|
| 464 |
|
|
VALID_O <= '1';
|
| 465 |
|
|
elsif v_CALCULATION_CNTR = x"14" then
|
| 466 |
|
|
DATA_O <= STATE_TABLE1(13);
|
| 467 |
|
|
VALID_O <= '1';
|
| 468 |
|
|
elsif v_CALCULATION_CNTR = x"15" then
|
| 469 |
|
|
DATA_O <= STATE_TABLE1(14);
|
| 470 |
|
|
VALID_O <= '1';
|
| 471 |
|
|
elsif v_CALCULATION_CNTR = x"16" then
|
| 472 |
|
|
DATA_O <= STATE_TABLE1(15);
|
| 473 |
|
|
VALID_O <= '1';
|
| 474 |
|
|
else
|
| 475 |
|
|
DATA_O <= x"00";
|
| 476 |
|
|
VALID_O <= '0';
|
| 477 |
|
|
end if;
|
| 478 |
|
|
else
|
| 479 |
|
|
VALID_O <= '0';
|
| 480 |
|
|
end if;
|
| 481 |
|
|
|
| 482 |
|
|
end if;
|
| 483 |
|
|
end process;
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
end Behavioral;
|
| 490 |
|
|
|
