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[/] [aes_128_192_256/] [web_uploads/] [key_expansion.vhdl] - Blame information for rev 6

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--------------------------------------------------------------------------------
-- Organization:      www.opendsp.pl
-- Engineer:          Jerzy Gbur
--
-- Create Date:    2006-05-13
-- Design Name:    aes
-- Module Name:    key_expansion
-- Project Name:   aes
-- Target Device:
-- Tool versions:
-- Description:
--              KEY_SIZE:      0 - 128
--                             1 - 192
--                             2 - 256
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library WORK;
use WORK.aes_pkg.ALL;
 
entity key_expansion is
   generic        (
                  KEY_SIZE             :  in    integer range 0 to 2 := 2
                  );
   port
                  (
                  KEY_I                :  in    std_logic_vector(7 downto 0);
                  VALID_KEY_I          :  in    std_logic;
 
                  CLK_I                :  in    std_logic;
                  RESET_I              :  in    std_logic;
                  CE_I                 :  in    std_logic;
 
                  DONE_O               :  out   std_logic;
                  GET_KEY_I            :  in    std_logic;
                  KEY_NUMB_I           :  in    std_logic_vector(5 downto 0);
 
                  KEY_EXP_O            :  out   std_logic_vector(31 downto 0)
                  );
 
end key_expansion;
 
architecture Behavioral of key_expansion is
 
   type           type_ROUND_TABLE     is array (0 to 63)  of std_logic_vector(31 downto 0);
 
   signal         KEY_EXPAN0           :  type_ROUND_TABLE;
 
   signal         t_FORWARD_TABLE      :  type_SBOX;
 
   signal         v_KEY32_IN           :  std_logic_vector(31 downto 0);
 
   signal         i_ROUND              :  integer range 0 to 13;
   signal         i_BYTE_CNTR4         :  integer range 0 to 3;
 
   signal         FF_VALID_KEY         :  std_logic;
   signal         v_KEY_COL_IN0        :  std_logic_vector(31 downto 0);
   signal         v_KEY_COL_OUT0       :  std_logic_vector(31 downto 0);
   signal         v_TEMP_VECTOR        :  std_logic_vector(31 downto 0);
   signal         i_FRW_ADD_RD0        :  integer range 0 to 255;
   signal         v_SUB_WORD           :  std_logic_vector(7 downto 0);
 
   signal         SRAM_WREN0           :  std_logic;
   signal         i_SRAM_ADDR_WR0      :  integer range 0 to 63;
   signal         i_SRAM_ADDR_RD0      :  integer range 0 to 63;
   signal         i_EXTERN_ADDRESS     :  integer range 0 to 63;
   signal         i_INTERN_ADDR_RD0    :  integer range 0 to 63;
 
   signal         v_CALCULATION_CNTR   :  std_logic_vector(7 downto 0);
   signal         START_CALCULATION    :  std_logic;
   signal         CALCULATION          :  std_logic;
   signal         FF_GET_KEY           :  std_logic;
 
begin
 
t_FORWARD_TABLE <= c_SBOX_FRV;
 
--****************************************************************************--
--* Packetization for 32bit words from input                                 *--
--****************************************************************************--
P0000:
   process(CLK_I)
   begin
      if rising_edge(CLK_I) then
         if CE_I = '1' then
            FF_VALID_KEY <= VALID_KEY_I;
 
            if VALID_KEY_I = '0' then
 
               i_BYTE_CNTR4   <=  0;
 
            elsif VALID_KEY_I = '1' then
 
               if i_BYTE_CNTR4 = 0 then
                  v_KEY32_IN(7 downto 0) <= KEY_I;
               elsif i_BYTE_CNTR4 = 1 then
                  v_KEY32_IN(15 downto 8) <= KEY_I;
               elsif i_BYTE_CNTR4 = 2 then
                  v_KEY32_IN(23 downto 16) <= KEY_I;
               elsif i_BYTE_CNTR4 = 3 then
                  v_KEY32_IN(31 downto 24) <= KEY_I;
               end if;
 
               if i_BYTE_CNTR4 = 3 then
                  i_BYTE_CNTR4 <= 0;
               else
                  i_BYTE_CNTR4 <= i_BYTE_CNTR4 + 1;
               end if;
 
            end if;
         end if;
 
      end if;
   end process;
 
--****************************************************************************--
--* RAM for Key Expansion                                                    *--
--****************************************************************************--
 
SRAM0:
   process(CLK_I)
   begin
      if rising_edge(CLK_I) then
 
         if RESET_I = '1' then
            SRAM_WREN0 <= '0';
         elsif CE_I = '1' then
            if VALID_KEY_I = '1' and i_BYTE_CNTR4 = 3 then
               SRAM_WREN0 <= '1';
            elsif v_CALCULATION_CNTR = x"08" then
               SRAM_WREN0 <= '1';
            elsif v_CALCULATION_CNTR = x"09" then
               SRAM_WREN0 <= '1';
            elsif v_CALCULATION_CNTR = x"0A" then
               SRAM_WREN0 <= '1';
            elsif v_CALCULATION_CNTR = x"0B" then
               SRAM_WREN0 <= '1';
            elsif KEY_SIZE = 1 then
               if v_CALCULATION_CNTR = x"0C" then
                  SRAM_WREN0 <= '1';
               elsif v_CALCULATION_CNTR = x"0D" then
                  SRAM_WREN0 <= '1';
               else
                  SRAM_WREN0 <= '0';
               end if;
            elsif KEY_SIZE = 2 then
               if v_CALCULATION_CNTR = x"11" then
                  SRAM_WREN0 <= '1';
               elsif v_CALCULATION_CNTR = x"12" then
                  SRAM_WREN0 <= '1';
               elsif v_CALCULATION_CNTR = x"13" then
                  SRAM_WREN0 <= '1';
               elsif v_CALCULATION_CNTR = x"14" then
                  SRAM_WREN0 <= '1';
               else
                  SRAM_WREN0 <= '0';
               end if;
            else
               SRAM_WREN0 <= '0';
            end if;
         end if;
 
         -- RAM
         if CE_I = '1' then
            if SRAM_WREN0 = '1' then
               KEY_EXPAN0(i_SRAM_ADDR_WR0) <= v_KEY_COL_IN0;
            end if;
            v_KEY_COL_OUT0  <= KEY_EXPAN0(i_SRAM_ADDR_RD0);
         end if;
 
         -- Write address
         if RESET_I = '1' then
            i_SRAM_ADDR_WR0 <= 0;
         elsif CE_I = '1' then
            if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then
               i_SRAM_ADDR_WR0 <= 0;
            elsif SRAM_WREN0 = '1' then
               i_SRAM_ADDR_WR0 <= i_SRAM_ADDR_WR0 + 1;
            end if;
         end if;
 
         -- Read address
         if RESET_I = '1' then
            i_INTERN_ADDR_RD0 <= 0;
         elsif CE_I = '1' then
            if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then
               i_INTERN_ADDR_RD0 <= 0;
            elsif v_CALCULATION_CNTR = x"07" then
               i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
            elsif v_CALCULATION_CNTR = x"08" then
               i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
            elsif v_CALCULATION_CNTR = x"09" then
               i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
            elsif v_CALCULATION_CNTR = x"0A" then
               i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
            elsif KEY_SIZE = 1 then
               if v_CALCULATION_CNTR = x"0B" then
                  i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
               elsif v_CALCULATION_CNTR = x"0C" then
                  i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
               end if;
            elsif KEY_SIZE = 2 then
               if v_CALCULATION_CNTR = x"10" then
                  i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
               elsif v_CALCULATION_CNTR = x"11" then
                  i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
               elsif v_CALCULATION_CNTR = x"12" then
                  i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
               elsif v_CALCULATION_CNTR = x"13" then
                  i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;
               end if;
            end if;
         end if;
 
         FF_GET_KEY <= GET_KEY_I;
      end if;
   end process;
 
i_EXTERN_ADDRESS <= conv_integer(KEY_NUMB_I);
 
i_SRAM_ADDR_RD0   <= i_INTERN_ADDR_RD0 when GET_KEY_I = '0' else i_EXTERN_ADDRESS;
 
KEY_EXP_O         <= v_KEY_COL_OUT0 when  FF_GET_KEY  = '1' else (others => '0');
 
--****************************************************************************--
--* ROM for Sub Word                                                         *--
--****************************************************************************--
i_FRW_ADD_RD0 <= conv_integer(v_TEMP_VECTOR(7 downto 0)) when v_CALCULATION_CNTR = x"02"   else
                 conv_integer(v_TEMP_VECTOR(15 downto 8)) when v_CALCULATION_CNTR = x"03"  else
                 conv_integer(v_TEMP_VECTOR(23 downto 16)) when v_CALCULATION_CNTR = x"04" else
                 conv_integer(v_TEMP_VECTOR(31 downto 24)) when v_CALCULATION_CNTR = x"05" else
                 conv_integer(v_TEMP_VECTOR(7 downto 0)) when v_CALCULATION_CNTR = x"0C" and KEY_SIZE = 2  else
                 conv_integer(v_TEMP_VECTOR(15 downto 8)) when v_CALCULATION_CNTR = x"0D" and KEY_SIZE = 2  else
                 conv_integer(v_TEMP_VECTOR(23 downto 16)) when v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 2 else
                 conv_integer(v_TEMP_VECTOR(31 downto 24)) when v_CALCULATION_CNTR = x"0F" and KEY_SIZE = 2 else
                 0;
 
 
 
ROM0:
   process(CLK_I)
   begin
      if rising_edge(CLK_I) then
         if CE_I = '1' then
            v_SUB_WORD  <= t_FORWARD_TABLE(i_FRW_ADD_RD0);
         end if;
      end if;
   end process;
 
 
--****************************************************************************--
--* v_KEY_COL_IN0                                                            *--
--****************************************************************************--
 
 
v_KEY_COL_IN0 <=  v_KEY32_IN     when FF_VALID_KEY = '1' and i_BYTE_CNTR4 = 0 else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"09" else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"0A" else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"0B" else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"0C" else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"0D" and KEY_SIZE = 1 else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 1 else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"12" and KEY_SIZE = 2 else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"13" and KEY_SIZE = 2 else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"14" and KEY_SIZE = 2 else
                  v_TEMP_VECTOR  when v_CALCULATION_CNTR = x"15" and KEY_SIZE = 2 else
                  (others => '0');
 
--****************************************************************************--
--* CALCULATION                                                              *--
--****************************************************************************--
 
P0002:
        process(CLK_I)
        begin
                if rising_edge(CLK_I) then
         if RESET_I = '1' then
            START_CALCULATION <= '0';
            CALCULATION <= '0';
            DONE_O <= '0';
         elsif CE_I = '1' then
            if FF_VALID_KEY = '1' and VALID_KEY_I = '0' then
               START_CALCULATION <= '1';
               CALCULATION <= '1';
               DONE_O <= '0';
            elsif i_ROUND = 10 and KEY_SIZE = 0 then
               DONE_O <= '1';
               CALCULATION <= '0';
            elsif i_ROUND = 8 and KEY_SIZE = 1 then
               DONE_O <= '1';
               CALCULATION <= '0';
            elsif i_ROUND = 7 and KEY_SIZE = 2 then
               DONE_O <= '1';
               CALCULATION <= '0';
            else
               START_CALCULATION <= '0';
            end if;
         end if;
                end if;
        end process;
 
P0003:
        process(CLK_I)
        begin
                if rising_edge(CLK_I) then
         if RESET_I = '1' then
            v_CALCULATION_CNTR <= (others => '0');
            i_ROUND <= 0;
         elsif CE_I = '1' then
            if START_CALCULATION = '1' then
               v_CALCULATION_CNTR <= (others => '0');
               i_ROUND <= 0;
            elsif v_CALCULATION_CNTR = x"0C" and KEY_SIZE = 0 then
               v_CALCULATION_CNTR <= (others => '0');
               i_ROUND <= i_ROUND + 1;
            elsif v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 1 then
               v_CALCULATION_CNTR <= (others => '0');
               i_ROUND <= i_ROUND + 1;
            elsif v_CALCULATION_CNTR = x"15" and KEY_SIZE = 2 then
               v_CALCULATION_CNTR <= (others => '0');
               i_ROUND <= i_ROUND + 1;
            elsif CALCULATION = '1' then
               v_CALCULATION_CNTR <= v_CALCULATION_CNTR + 1;
            else
               v_CALCULATION_CNTR <= (others => '0');
            end if;
         end if;
                end if;
        end process;
--****************************************************************************--
--* v_TEMP_VECTOR                                                            *--
--****************************************************************************--
P0:
        process(CLK_I)
        begin
                if rising_edge(CLK_I) then
                        if RESET_I = '1' then
            v_TEMP_VECTOR <= (others => '0');
         elsif CE_I = '1' then
            if START_CALCULATION = '1' then
               v_TEMP_VECTOR <= v_KEY32_IN;
            elsif v_CALCULATION_CNTR = x"03" then
               v_TEMP_VECTOR(7 downto 0)     <= v_SUB_WORD;
            elsif v_CALCULATION_CNTR = x"04" then
               v_TEMP_VECTOR(15 downto 8)    <= v_SUB_WORD;
            elsif v_CALCULATION_CNTR = x"05" then
               v_TEMP_VECTOR(23 downto 16)   <= v_SUB_WORD;
            elsif v_CALCULATION_CNTR = x"06" then
               v_TEMP_VECTOR(31 downto 24)   <= v_SUB_WORD;
 
            elsif v_CALCULATION_CNTR = x"07" then
               v_TEMP_VECTOR   <= (v_TEMP_VECTOR(7 downto 0) & v_TEMP_VECTOR(31 downto 8)) xor (x"000000" & c_RCON(i_ROUND));
            elsif v_CALCULATION_CNTR = x"08" then
               v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
            elsif v_CALCULATION_CNTR = x"09" then
               v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
            elsif v_CALCULATION_CNTR = x"0A" then
               v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
            elsif v_CALCULATION_CNTR = x"0B" then
               v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
            elsif KEY_SIZE = 1 then
               if v_CALCULATION_CNTR = x"0C" then
                  v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
               elsif v_CALCULATION_CNTR = x"0D" then
                  v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
               end if;
            elsif KEY_SIZE = 2 then
 
               if v_CALCULATION_CNTR = x"0D" then
                  v_TEMP_VECTOR(7 downto 0)     <= v_SUB_WORD;
               elsif v_CALCULATION_CNTR = x"0E" then
                  v_TEMP_VECTOR(15 downto 8)    <= v_SUB_WORD;
               elsif v_CALCULATION_CNTR = x"0F" then
                  v_TEMP_VECTOR(23 downto 16)   <= v_SUB_WORD;
               elsif v_CALCULATION_CNTR = x"10" then
                  v_TEMP_VECTOR(31 downto 24)   <= v_SUB_WORD;
 
               elsif v_CALCULATION_CNTR = x"11" then
                  v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
               elsif v_CALCULATION_CNTR = x"12" then
                  v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
               elsif v_CALCULATION_CNTR = x"13" then
                  v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
               elsif v_CALCULATION_CNTR = x"14" then
                  v_TEMP_VECTOR   <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;
               end if;
 
            end if;
         end if;
                end if;
        end process;
 
end Behavioral;

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Subversion Repositories aes_128_192_256

[/] [aes_128_192_256/] [web_uploads/] [key_expansion.vhdl] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	root	`--------------------------------------------------------------------------------`
2			`-- Organization: www.opendsp.pl`
3			`-- Engineer: Jerzy Gbur`
4			`--`
5			`-- Create Date: 2006-05-13`
6			`-- Design Name: aes`
7			`-- Module Name: key_expansion`
8			`-- Project Name: aes`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`-- KEY_SIZE: 0 - 128`
13			`-- 1 - 192`
14			`-- 2 - 256`
15			`--`
16			`-- Dependencies:`
17			`--`
18			`-- Revision:`
19			`-- Revision 0.01 - File Created`
20			`-- Additional Comments:`
21			`--`
22			`--------------------------------------------------------------------------------`
23
24			`library IEEE;`
25			`use IEEE.STD_LOGIC_1164.ALL;`
26			`use IEEE.STD_LOGIC_ARITH.ALL;`
27			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
28
29			`library WORK;`
30			`use WORK.aes_pkg.ALL;`
31
32			`entity key_expansion is`
33			`generic (`
34			`KEY_SIZE : in integer range 0 to 2 := 2`
35			`);`
36			`port`
37			`(`
38			`KEY_I : in std_logic_vector(7 downto 0);`
39			`VALID_KEY_I : in std_logic;`
40
41			`CLK_I : in std_logic;`
42			`RESET_I : in std_logic;`
43			`CE_I : in std_logic;`
44
45			`DONE_O : out std_logic;`
46			`GET_KEY_I : in std_logic;`
47			`KEY_NUMB_I : in std_logic_vector(5 downto 0);`
48
49			`KEY_EXP_O : out std_logic_vector(31 downto 0)`
50			`);`
51
52			`end key_expansion;`
53
54			`architecture Behavioral of key_expansion is`
55
56			`type type_ROUND_TABLE is array (0 to 63) of std_logic_vector(31 downto 0);`
57
58			`signal KEY_EXPAN0 : type_ROUND_TABLE;`
59
60			`signal t_FORWARD_TABLE : type_SBOX;`
61
62			`signal v_KEY32_IN : std_logic_vector(31 downto 0);`
63
64			`signal i_ROUND : integer range 0 to 13;`
65			`signal i_BYTE_CNTR4 : integer range 0 to 3;`
66
67			`signal FF_VALID_KEY : std_logic;`
68			`signal v_KEY_COL_IN0 : std_logic_vector(31 downto 0);`
69			`signal v_KEY_COL_OUT0 : std_logic_vector(31 downto 0);`
70			`signal v_TEMP_VECTOR : std_logic_vector(31 downto 0);`
71			`signal i_FRW_ADD_RD0 : integer range 0 to 255;`
72			`signal v_SUB_WORD : std_logic_vector(7 downto 0);`
73
74			`signal SRAM_WREN0 : std_logic;`
75			`signal i_SRAM_ADDR_WR0 : integer range 0 to 63;`
76			`signal i_SRAM_ADDR_RD0 : integer range 0 to 63;`
77			`signal i_EXTERN_ADDRESS : integer range 0 to 63;`
78			`signal i_INTERN_ADDR_RD0 : integer range 0 to 63;`
79
80			`signal v_CALCULATION_CNTR : std_logic_vector(7 downto 0);`
81			`signal START_CALCULATION : std_logic;`
82			`signal CALCULATION : std_logic;`
83			`signal FF_GET_KEY : std_logic;`
84
85			`begin`
86
87			`t_FORWARD_TABLE <= c_SBOX_FRV;`
88
89			`--****************************************************************************--`
90			`--* Packetization for 32bit words from input *--`
91			`--****************************************************************************--`
92			`P0000:`
93			`process(CLK_I)`
94			`begin`
95			`if rising_edge(CLK_I) then`
96			`if CE_I = '1' then`
97			`FF_VALID_KEY <= VALID_KEY_I;`
98
99			`if VALID_KEY_I = '0' then`
100
101			`i_BYTE_CNTR4 <= 0;`
102
103			`elsif VALID_KEY_I = '1' then`
104
105			`if i_BYTE_CNTR4 = 0 then`
106			`v_KEY32_IN(7 downto 0) <= KEY_I;`
107			`elsif i_BYTE_CNTR4 = 1 then`
108			`v_KEY32_IN(15 downto 8) <= KEY_I;`
109			`elsif i_BYTE_CNTR4 = 2 then`
110			`v_KEY32_IN(23 downto 16) <= KEY_I;`
111			`elsif i_BYTE_CNTR4 = 3 then`
112			`v_KEY32_IN(31 downto 24) <= KEY_I;`
113			`end if;`
114
115			`if i_BYTE_CNTR4 = 3 then`
116			`i_BYTE_CNTR4 <= 0;`
117			`else`
118			`i_BYTE_CNTR4 <= i_BYTE_CNTR4 + 1;`
119			`end if;`
120
121			`end if;`
122			`end if;`
123
124			`end if;`
125			`end process;`
126
127			`--****************************************************************************--`
128			`--* RAM for Key Expansion *--`
129			`--****************************************************************************--`
130
131			`SRAM0:`
132			`process(CLK_I)`
133			`begin`
134			`if rising_edge(CLK_I) then`
135
136			`if RESET_I = '1' then`
137			`SRAM_WREN0 <= '0';`
138			`elsif CE_I = '1' then`
139			`if VALID_KEY_I = '1' and i_BYTE_CNTR4 = 3 then`
140			`SRAM_WREN0 <= '1';`
141			`elsif v_CALCULATION_CNTR = x"08" then`
142			`SRAM_WREN0 <= '1';`
143			`elsif v_CALCULATION_CNTR = x"09" then`
144			`SRAM_WREN0 <= '1';`
145			`elsif v_CALCULATION_CNTR = x"0A" then`
146			`SRAM_WREN0 <= '1';`
147			`elsif v_CALCULATION_CNTR = x"0B" then`
148			`SRAM_WREN0 <= '1';`
149			`elsif KEY_SIZE = 1 then`
150			`if v_CALCULATION_CNTR = x"0C" then`
151			`SRAM_WREN0 <= '1';`
152			`elsif v_CALCULATION_CNTR = x"0D" then`
153			`SRAM_WREN0 <= '1';`
154			`else`
155			`SRAM_WREN0 <= '0';`
156			`end if;`
157			`elsif KEY_SIZE = 2 then`
158			`if v_CALCULATION_CNTR = x"11" then`
159			`SRAM_WREN0 <= '1';`
160			`elsif v_CALCULATION_CNTR = x"12" then`
161			`SRAM_WREN0 <= '1';`
162			`elsif v_CALCULATION_CNTR = x"13" then`
163			`SRAM_WREN0 <= '1';`
164			`elsif v_CALCULATION_CNTR = x"14" then`
165			`SRAM_WREN0 <= '1';`
166			`else`
167			`SRAM_WREN0 <= '0';`
168			`end if;`
169			`else`
170			`SRAM_WREN0 <= '0';`
171			`end if;`
172			`end if;`
173
174			`-- RAM`
175			`if CE_I = '1' then`
176			`if SRAM_WREN0 = '1' then`
177			`KEY_EXPAN0(i_SRAM_ADDR_WR0) <= v_KEY_COL_IN0;`
178			`end if;`
179			`v_KEY_COL_OUT0 <= KEY_EXPAN0(i_SRAM_ADDR_RD0);`
180			`end if;`
181
182			`-- Write address`
183			`if RESET_I = '1' then`
184			`i_SRAM_ADDR_WR0 <= 0;`
185			`elsif CE_I = '1' then`
186			`if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then`
187			`i_SRAM_ADDR_WR0 <= 0;`
188			`elsif SRAM_WREN0 = '1' then`
189			`i_SRAM_ADDR_WR0 <= i_SRAM_ADDR_WR0 + 1;`
190			`end if;`
191			`end if;`
192
193			`-- Read address`
194			`if RESET_I = '1' then`
195			`i_INTERN_ADDR_RD0 <= 0;`
196			`elsif CE_I = '1' then`
197			`if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then`
198			`i_INTERN_ADDR_RD0 <= 0;`
199			`elsif v_CALCULATION_CNTR = x"07" then`
200			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
201			`elsif v_CALCULATION_CNTR = x"08" then`
202			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
203			`elsif v_CALCULATION_CNTR = x"09" then`
204			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
205			`elsif v_CALCULATION_CNTR = x"0A" then`
206			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
207			`elsif KEY_SIZE = 1 then`
208			`if v_CALCULATION_CNTR = x"0B" then`
209			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
210			`elsif v_CALCULATION_CNTR = x"0C" then`
211			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
212			`end if;`
213			`elsif KEY_SIZE = 2 then`
214			`if v_CALCULATION_CNTR = x"10" then`
215			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
216			`elsif v_CALCULATION_CNTR = x"11" then`
217			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
218			`elsif v_CALCULATION_CNTR = x"12" then`
219			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
220			`elsif v_CALCULATION_CNTR = x"13" then`
221			`i_INTERN_ADDR_RD0 <= i_INTERN_ADDR_RD0 + 1;`
222			`end if;`
223			`end if;`
224			`end if;`
225
226			`FF_GET_KEY <= GET_KEY_I;`
227			`end if;`
228			`end process;`
229
230			`i_EXTERN_ADDRESS <= conv_integer(KEY_NUMB_I);`
231
232			`i_SRAM_ADDR_RD0 <= i_INTERN_ADDR_RD0 when GET_KEY_I = '0' else i_EXTERN_ADDRESS;`
233
234			`KEY_EXP_O <= v_KEY_COL_OUT0 when FF_GET_KEY = '1' else (others => '0');`
235
236			`--****************************************************************************--`
237			`--* ROM for Sub Word *--`
238			`--****************************************************************************--`
239			`i_FRW_ADD_RD0 <= conv_integer(v_TEMP_VECTOR(7 downto 0)) when v_CALCULATION_CNTR = x"02" else`
240			`conv_integer(v_TEMP_VECTOR(15 downto 8)) when v_CALCULATION_CNTR = x"03" else`
241			`conv_integer(v_TEMP_VECTOR(23 downto 16)) when v_CALCULATION_CNTR = x"04" else`
242			`conv_integer(v_TEMP_VECTOR(31 downto 24)) when v_CALCULATION_CNTR = x"05" else`
243			`conv_integer(v_TEMP_VECTOR(7 downto 0)) when v_CALCULATION_CNTR = x"0C" and KEY_SIZE = 2 else`
244			`conv_integer(v_TEMP_VECTOR(15 downto 8)) when v_CALCULATION_CNTR = x"0D" and KEY_SIZE = 2 else`
245			`conv_integer(v_TEMP_VECTOR(23 downto 16)) when v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 2 else`
246			`conv_integer(v_TEMP_VECTOR(31 downto 24)) when v_CALCULATION_CNTR = x"0F" and KEY_SIZE = 2 else`
247			`0;`
248
249
250
251			`ROM0:`
252			`process(CLK_I)`
253			`begin`
254			`if rising_edge(CLK_I) then`
255			`if CE_I = '1' then`
256			`v_SUB_WORD <= t_FORWARD_TABLE(i_FRW_ADD_RD0);`
257			`end if;`
258			`end if;`
259			`end process;`
260
261
262			`--****************************************************************************--`
263			`--* v_KEY_COL_IN0 *--`
264			`--****************************************************************************--`
265
266
267			`v_KEY_COL_IN0 <= v_KEY32_IN when FF_VALID_KEY = '1' and i_BYTE_CNTR4 = 0 else`
268			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"09" else`
269			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0A" else`
270			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0B" else`
271			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0C" else`
272			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0D" and KEY_SIZE = 1 else`
273			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 1 else`
274			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"12" and KEY_SIZE = 2 else`
275			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"13" and KEY_SIZE = 2 else`
276			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"14" and KEY_SIZE = 2 else`
277			`v_TEMP_VECTOR when v_CALCULATION_CNTR = x"15" and KEY_SIZE = 2 else`
278			`(others => '0');`
279
280			`--****************************************************************************--`
281			`--* CALCULATION *--`
282			`--****************************************************************************--`
283
284			`P0002:`
285			`process(CLK_I)`
286			`begin`
287			`if rising_edge(CLK_I) then`
288			`if RESET_I = '1' then`
289			`START_CALCULATION <= '0';`
290			`CALCULATION <= '0';`
291			`DONE_O <= '0';`
292			`elsif CE_I = '1' then`
293			`if FF_VALID_KEY = '1' and VALID_KEY_I = '0' then`
294			`START_CALCULATION <= '1';`
295			`CALCULATION <= '1';`
296			`DONE_O <= '0';`
297			`elsif i_ROUND = 10 and KEY_SIZE = 0 then`
298			`DONE_O <= '1';`
299			`CALCULATION <= '0';`
300			`elsif i_ROUND = 8 and KEY_SIZE = 1 then`
301			`DONE_O <= '1';`
302			`CALCULATION <= '0';`
303			`elsif i_ROUND = 7 and KEY_SIZE = 2 then`
304			`DONE_O <= '1';`
305			`CALCULATION <= '0';`
306			`else`
307			`START_CALCULATION <= '0';`
308			`end if;`
309			`end if;`
310			`end if;`
311			`end process;`
312
313			`P0003:`
314			`process(CLK_I)`
315			`begin`
316			`if rising_edge(CLK_I) then`
317			`if RESET_I = '1' then`
318			`v_CALCULATION_CNTR <= (others => '0');`
319			`i_ROUND <= 0;`
320			`elsif CE_I = '1' then`
321			`if START_CALCULATION = '1' then`
322			`v_CALCULATION_CNTR <= (others => '0');`
323			`i_ROUND <= 0;`
324			`elsif v_CALCULATION_CNTR = x"0C" and KEY_SIZE = 0 then`
325			`v_CALCULATION_CNTR <= (others => '0');`
326			`i_ROUND <= i_ROUND + 1;`
327			`elsif v_CALCULATION_CNTR = x"0E" and KEY_SIZE = 1 then`
328			`v_CALCULATION_CNTR <= (others => '0');`
329			`i_ROUND <= i_ROUND + 1;`
330			`elsif v_CALCULATION_CNTR = x"15" and KEY_SIZE = 2 then`
331			`v_CALCULATION_CNTR <= (others => '0');`
332			`i_ROUND <= i_ROUND + 1;`
333			`elsif CALCULATION = '1' then`
334			`v_CALCULATION_CNTR <= v_CALCULATION_CNTR + 1;`
335			`else`
336			`v_CALCULATION_CNTR <= (others => '0');`
337			`end if;`
338			`end if;`
339			`end if;`
340			`end process;`
341			`--****************************************************************************--`
342			`--* v_TEMP_VECTOR *--`
343			`--****************************************************************************--`
344			`P0:`
345			`process(CLK_I)`
346			`begin`
347			`if rising_edge(CLK_I) then`
348			`if RESET_I = '1' then`
349			`v_TEMP_VECTOR <= (others => '0');`
350			`elsif CE_I = '1' then`
351			`if START_CALCULATION = '1' then`
352			`v_TEMP_VECTOR <= v_KEY32_IN;`
353			`elsif v_CALCULATION_CNTR = x"03" then`
354			`v_TEMP_VECTOR(7 downto 0) <= v_SUB_WORD;`
355			`elsif v_CALCULATION_CNTR = x"04" then`
356			`v_TEMP_VECTOR(15 downto 8) <= v_SUB_WORD;`
357			`elsif v_CALCULATION_CNTR = x"05" then`
358			`v_TEMP_VECTOR(23 downto 16) <= v_SUB_WORD;`
359			`elsif v_CALCULATION_CNTR = x"06" then`
360			`v_TEMP_VECTOR(31 downto 24) <= v_SUB_WORD;`
361
362			`elsif v_CALCULATION_CNTR = x"07" then`
363			`v_TEMP_VECTOR <= (v_TEMP_VECTOR(7 downto 0) & v_TEMP_VECTOR(31 downto 8)) xor (x"000000" & c_RCON(i_ROUND));`
364			`elsif v_CALCULATION_CNTR = x"08" then`
365			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
366			`elsif v_CALCULATION_CNTR = x"09" then`
367			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
368			`elsif v_CALCULATION_CNTR = x"0A" then`
369			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
370			`elsif v_CALCULATION_CNTR = x"0B" then`
371			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
372			`elsif KEY_SIZE = 1 then`
373			`if v_CALCULATION_CNTR = x"0C" then`
374			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
375			`elsif v_CALCULATION_CNTR = x"0D" then`
376			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
377			`end if;`
378			`elsif KEY_SIZE = 2 then`
379
380			`if v_CALCULATION_CNTR = x"0D" then`
381			`v_TEMP_VECTOR(7 downto 0) <= v_SUB_WORD;`
382			`elsif v_CALCULATION_CNTR = x"0E" then`
383			`v_TEMP_VECTOR(15 downto 8) <= v_SUB_WORD;`
384			`elsif v_CALCULATION_CNTR = x"0F" then`
385			`v_TEMP_VECTOR(23 downto 16) <= v_SUB_WORD;`
386			`elsif v_CALCULATION_CNTR = x"10" then`
387			`v_TEMP_VECTOR(31 downto 24) <= v_SUB_WORD;`
388
389			`elsif v_CALCULATION_CNTR = x"11" then`
390			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
391			`elsif v_CALCULATION_CNTR = x"12" then`
392			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
393			`elsif v_CALCULATION_CNTR = x"13" then`
394			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
395			`elsif v_CALCULATION_CNTR = x"14" then`
396			`v_TEMP_VECTOR <= v_TEMP_VECTOR xor v_KEY_COL_OUT0;`
397			`end if;`
398
399			`end if;`
400			`end if;`
401			`end if;`
402			`end process;`
403
404			`end Behavioral;`