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[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [ram_16x64.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Ram module                                                  ////
////                                                              ////
////  Description:                                                ////
////  this is 16x64, we can use a 16x128 to replace two of this   ////
////    module, also, can use specific foundry libs instead       ////
////                                                              ////
////  To Do:                                                      ////
////   - done                                                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Luo Dongjun,   dongjun_luo@hotmail.com                ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
module ram_16x64 (clk,wr,wr_addr,wr_data,rd,rd_addr,rd_data);
 
input clk,wr,rd;
input [3:0] wr_addr,rd_addr;
input [63:0] wr_data;
output [63:0] rd_data;
 
reg [63:0] mem[15:0];
wire [63:0] rd_data;
 
// behavioral code for 16x64 mem
always @ (posedge clk)
begin
   if (wr)
      mem[wr_addr] <= wr_data;
end
 
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
 
reg [3:0] srd_addr;
 
always @ (posedge clk)
begin
        if (rd)
                srd_addr <= rd_addr;
end
 
assign rd_data = mem[srd_addr];
 
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
 
// always @ (posedge clk)
// begin
//    if (rd)
//       rd_data <= mem[rd_addr];
// end
 
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
 
endmodule

Line No.	Rev	Author	Line
1	5	motilito	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Ram module ////`
4			`//// ////`
5			`//// Description: ////`
6			`//// this is 16x64, we can use a 16x128 to replace two of this ////`
7			`//// module, also, can use specific foundry libs instead ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - done ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Luo Dongjun, dongjun_luo@hotmail.com ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`module ram_16x64 (clk,wr,wr_addr,wr_data,rd,rd_addr,rd_data);`
17
18			`input clk,wr,rd;`
19			`input [3:0] wr_addr,rd_addr;`
20			`input [63:0] wr_data;`
21			`output [63:0] rd_data;`
22
23			`reg [63:0] mem[15:0];`
24			`wire [63:0] rd_data;`
25
26			`// behavioral code for 16x64 mem`
27			`always @ (posedge clk)`
28			`begin`
29			`if (wr)`
30			`mem[wr_addr] <= wr_data;`
31			`end`
32
33			`//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI`
34
35			`reg [3:0] srd_addr;`
36
37			`always @ (posedge clk)`
38			`begin`
39			`if (rd)`
40			`srd_addr <= rd_addr;`
41			`end`
42
43			`assign rd_data = mem[srd_addr];`
44
45			`//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI`
46
47			`// always @ (posedge clk)`
48			`// begin`
49			`// if (rd)`
50			`// rd_data <= mem[rd_addr];`
51			`// end`
52
53			`//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI`
54
55			`endmodule`

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[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [ram_16x64.v] - Blame information for rev 5