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-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2010 Actel Corporation.  All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreAHBLite address decode logic
--                              for master 0 and master 1
--
--
-- SVN Revision Information:
-- SVN $Revision: 22340 $
-- SVN $Date: 2014-04-11 21:59:35 +0530 (Fri, 11 Apr 2014) $
--
--
-- *********************************************************************/
 
-- ========================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package coreahblite_support is
    function calc_msb_addr(x:integer) return integer;
end coreahblite_support;
 
package body coreahblite_support is
    function calc_msb_addr( x : integer ) return integer is
    begin
        if    x = 0 then return(31);
        elsif x = 1 then return(31);
        elsif x = 2 then return(27);
        elsif x = 3 then return(23);
        elsif x = 4 then return(19);
        elsif x = 5 then return(15);
        elsif x = 6 then return(11);
        else             return(31);
        end if;
    end calc_msb_addr;
end coreahblite_support;
-- ========================================================================
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coreahblite_support.all;
 
entity COREAHBLITE_ADDRDEC is
    generic (
        MEMSPACE         : integer range 0 to 6 := 0;
        HADDR_SHG_CFG    : integer range 0 to 1 := 1;
        M_AHBSLOTENABLE  : integer range 0 to (2**17)-1 := (2**17)-1;
        SC               : integer range 0 to (2**16)-1 := 0
    );
    port (
        ADDR             : in std_logic_vector(31 downto 0);
        REMAP            : in std_logic;
        ADDRDEC          : out std_logic_vector(16 downto 0);
        ABSOLUTEADDR     : out std_logic_vector(31 downto 0);
        RESERVEDDEC      : out std_logic
    );
end entity COREAHBLITE_ADDRDEC;
 
architecture COREAHBLITE_ADDRDEC_arch of COREAHBLITE_ADDRDEC is
 
constant SLAVE_0      : std_logic_vector(15 downto 0) := "0000000000000001";
constant SLAVE_1      : std_logic_vector(15 downto 0) := "0000000000000010";
constant SLAVE_2      : std_logic_vector(15 downto 0) := "0000000000000100";
constant SLAVE_3      : std_logic_vector(15 downto 0) := "0000000000001000";
constant SLAVE_4      : std_logic_vector(15 downto 0) := "0000000000010000";
constant SLAVE_5      : std_logic_vector(15 downto 0) := "0000000000100000";
constant SLAVE_6      : std_logic_vector(15 downto 0) := "0000000001000000";
constant SLAVE_7      : std_logic_vector(15 downto 0) := "0000000010000000";
constant SLAVE_8      : std_logic_vector(15 downto 0) := "0000000100000000";
constant SLAVE_9      : std_logic_vector(15 downto 0) := "0000001000000000";
constant SLAVE_10     : std_logic_vector(15 downto 0) := "0000010000000000";
constant SLAVE_11     : std_logic_vector(15 downto 0) := "0000100000000000";
constant SLAVE_12     : std_logic_vector(15 downto 0) := "0001000000000000";
constant SLAVE_13     : std_logic_vector(15 downto 0) := "0010000000000000";
constant SLAVE_14     : std_logic_vector(15 downto 0) := "0100000000000000";
constant SLAVE_15     : std_logic_vector(15 downto 0) := "1000000000000000";
constant NONE         : std_logic_vector(15 downto 0) := "0000000000000000";
 
constant SC_slv  : std_logic_vector(15 downto 0):=
    std_logic_vector(to_unsigned(SC,16));
 
constant MSB_ADDR     : integer := calc_msb_addr(MEMSPACE);
 
signal sdec_raw         : std_logic_vector(15 downto 0);
signal sdec             : std_logic_vector(15 downto 0);
signal s16dec           : std_logic;
signal absaddr          : std_logic_vector(31 downto 0);
signal ADDRDEC_pre      : std_logic_vector(16 downto 0);
 
signal slotdec          : std_logic_vector(3 downto 0);
signal m0_hugeslotdec   : std_logic;
signal m0_otherslotsdec : std_logic;
 
 
begin
    g_mem0_00 : if (MEMSPACE = 0) generate
    begin
        m0_hugeslotdec   <= '1' when (ADDR(31) = '1') else '0';
        m0_otherslotsdec <= '1' when (ADDR(30 downto 20) = "00000000000") else '0';
        slotdec <= ADDR(19 downto 16);
        process (ADDR, m0_hugeslotdec, m0_otherslotsdec, slotdec, REMAP)
        begin
            absaddr(31 downto 0) <= ADDR(31 downto 0);
            sdec_raw(15 downto 0) <= NONE;
            if (m0_hugeslotdec = '1') then
                if (HADDR_SHG_CFG = 0) then
                    absaddr(31) <= '0';
                else
                    absaddr(31) <= '1';
                end if;
            elsif (m0_otherslotsdec = '1') then
                case slotdec is
                    when "0000" =>
                        if (REMAP = '0') then
                            sdec_raw(15 downto 0) <= SLAVE_0;
                        else
                            absaddr(16) <= '1';
                            sdec_raw(15 downto 0) <= SLAVE_1;
                        end if;
                    when "0001" =>
                        if (REMAP = '0') then
                            sdec_raw(15 downto 0) <= SLAVE_1;
                        else
                            absaddr(16) <= '0';
                            sdec_raw(15 downto 0) <= SLAVE_0;
                        end if;
                    when "0010" => sdec_raw(15 downto 0) <= SLAVE_2;
                    when "0011" => sdec_raw(15 downto 0) <= SLAVE_3;
                    when "0100" => sdec_raw(15 downto 0) <= SLAVE_4;
                    when "0101" => sdec_raw(15 downto 0) <= SLAVE_5;
                    when "0110" => sdec_raw(15 downto 0) <= SLAVE_6;
                    when "0111" => sdec_raw(15 downto 0) <= SLAVE_7;
                    when "1000" => sdec_raw(15 downto 0) <= SLAVE_8;
                    when "1001" => sdec_raw(15 downto 0) <= SLAVE_9;
                    when "1010" => sdec_raw(15 downto 0) <= SLAVE_10;
                    when "1011" => sdec_raw(15 downto 0) <= SLAVE_11;
                    when "1100" => sdec_raw(15 downto 0) <= SLAVE_12;
                    when "1101" => sdec_raw(15 downto 0) <= SLAVE_13;
                    when "1110" => sdec_raw(15 downto 0) <= SLAVE_14;
                    when others => sdec_raw(15 downto 0) <= SLAVE_15;
                end case;
            end if;
        end process;
 
        sdec(15) <= sdec_raw(15);
        sdec(14) <= sdec_raw(14);
        sdec(13) <= sdec_raw(13);
        sdec(12) <= sdec_raw(12);
        sdec(11) <= sdec_raw(11);
        sdec(10) <= sdec_raw(10);
        sdec(9)  <= sdec_raw(9);
        sdec(8)  <= sdec_raw(8);
        sdec(7)  <= sdec_raw(7);
        sdec(6)  <= sdec_raw(6);
        sdec(5)  <= sdec_raw(5);
        sdec(4)  <= sdec_raw(4);
        sdec(3)  <= sdec_raw(3);
        sdec(2)  <= sdec_raw(2);
        sdec(1)  <= sdec_raw(1);
        sdec(0)  <= sdec_raw(0);
 
        s16dec <= m0_hugeslotdec;
 
        RESERVEDDEC <= '1' when m0_hugeslotdec='0' and m0_otherslotsdec='0'
                       else '0';
    end generate;
 
    g_mem1_00 : if (not(MEMSPACE = 0)) generate
    begin
        m0_hugeslotdec   <= '0';
        m0_otherslotsdec <= '0';
        slotdec <= ADDR(MSB_ADDR downto MSB_ADDR-3);
        process (ADDR, slotdec, REMAP)
        begin
            absaddr(31 downto 0) <= ADDR(31 downto 0);
            case slotdec is
                when "0000" =>
                    if (REMAP = '0') then
                        sdec_raw(15 downto 0) <= SLAVE_0;
                    else
                        absaddr(MSB_ADDR-3) <= '1';
                        sdec_raw(15 downto 0) <= SLAVE_1;
                    end if;
                when "0001" =>
                    if (REMAP = '0') then
                        sdec_raw(15 downto 0) <= SLAVE_1;
                    else
                        absaddr(MSB_ADDR-3) <= '0';
                        sdec_raw(15 downto 0) <= SLAVE_0;
                    end if;
                when "0010" => sdec_raw(15 downto 0) <= SLAVE_2;
                when "0011" => sdec_raw(15 downto 0) <= SLAVE_3;
                when "0100" => sdec_raw(15 downto 0) <= SLAVE_4;
                when "0101" => sdec_raw(15 downto 0) <= SLAVE_5;
                when "0110" => sdec_raw(15 downto 0) <= SLAVE_6;
                when "0111" => sdec_raw(15 downto 0) <= SLAVE_7;
                when "1000" => sdec_raw(15 downto 0) <= SLAVE_8;
                when "1001" => sdec_raw(15 downto 0) <= SLAVE_9;
                when "1010" => sdec_raw(15 downto 0) <= SLAVE_10;
                when "1011" => sdec_raw(15 downto 0) <= SLAVE_11;
                when "1100" => sdec_raw(15 downto 0) <= SLAVE_12;
                when "1101" => sdec_raw(15 downto 0) <= SLAVE_13;
                when "1110" => sdec_raw(15 downto 0) <= SLAVE_14;
                when others => sdec_raw(15 downto 0) <= SLAVE_15;
            end case;
        end process;
 
        sdec(15) <= sdec_raw(15) and not(SC_slv(15));
        sdec(14) <= sdec_raw(14) and not(SC_slv(14));
        sdec(13) <= sdec_raw(13) and not(SC_slv(13));
        sdec(12) <= sdec_raw(12) and not(SC_slv(12));
        sdec(11) <= sdec_raw(11) and not(SC_slv(11));
        sdec(10) <= sdec_raw(10) and not(SC_slv(10));
        sdec(9)  <= sdec_raw(9)  and not(SC_slv(9));
        sdec(8)  <= sdec_raw(8)  and not(SC_slv(8));
        sdec(7)  <= sdec_raw(7)  and not(SC_slv(7));
        sdec(6)  <= sdec_raw(6)  and not(SC_slv(6));
        sdec(5)  <= sdec_raw(5)  and not(SC_slv(5));
        sdec(4)  <= sdec_raw(4)  and not(SC_slv(4));
        sdec(3)  <= sdec_raw(3)  and not(SC_slv(3));
        sdec(2)  <= sdec_raw(2)  and not(SC_slv(2));
        sdec(1)  <= sdec_raw(1)  and not(SC_slv(1));
        sdec(0)  <= sdec_raw(0)  and not(SC_slv(0));
 
        s16dec <=    (sdec_raw(15) and SC_slv(15))
                  or (sdec_raw(14) and SC_slv(14))
                  or (sdec_raw(13) and SC_slv(13))
                  or (sdec_raw(12) and SC_slv(12))
                  or (sdec_raw(11) and SC_slv(11))
                  or (sdec_raw(10) and SC_slv(10))
                  or (sdec_raw(9)  and SC_slv(9) )
                  or (sdec_raw(8)  and SC_slv(8) )
                  or (sdec_raw(7)  and SC_slv(7) )
                  or (sdec_raw(6)  and SC_slv(6) )
                  or (sdec_raw(5)  and SC_slv(5) )
                  or (sdec_raw(4)  and SC_slv(4) )
                  or (sdec_raw(3)  and SC_slv(3) )
                  or (sdec_raw(2)  and SC_slv(2) )
                  or (sdec_raw(1)  and SC_slv(1) )
                  or (sdec_raw(0)  and SC_slv(0) );
 
        RESERVEDDEC <= '0';
    end generate;
 
    ADDRDEC_pre(16 downto 0) <= (s16dec & sdec(15 downto 0));
    ABSOLUTEADDR(31 downto 0) <= absaddr(31 downto 0);
    ADDRDEC(16 downto 0) <= ADDRDEC_pre(16 downto 0);
 
end architecture COREAHBLITE_ADDRDEC_arch;

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Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [Actel/] [DirectCore/] [CoreAHBLite/] [5.3.101/] [rtl/] [vhdl/] [core/] [coreahblite_addrdec.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`-- ********************************************************************/`
2			`-- Actel Corporation Proprietary and Confidential`
3			`-- Copyright 2010 Actel Corporation. All rights reserved.`
4			`--`
5			`-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN`
6			`-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED`
7			`-- IN ADVANCE IN WRITING.`
8			`--`
9			`-- Description: CoreAHBLite address decode logic`
10			`-- for master 0 and master 1`
11			`--`
12			`--`
13			`-- SVN Revision Information:`
14			`-- SVN $Revision: 22340 $`
15			`-- SVN $Date: 2014-04-11 21:59:35 +0530 (Fri, 11 Apr 2014) $`
16			`--`
17			`--`
18			`-- *********************************************************************/`
19
20			`-- ========================================================================`
21			`library ieee;`
22			`use ieee.std_logic_1164.all;`
23			`use ieee.numeric_std.all;`
24
25			`package coreahblite_support is`
26			`function calc_msb_addr(x:integer) return integer;`
27			`end coreahblite_support;`
28
29			`package body coreahblite_support is`
30			`function calc_msb_addr( x : integer ) return integer is`
31			`begin`
32			`if x = 0 then return(31);`
33			`elsif x = 1 then return(31);`
34			`elsif x = 2 then return(27);`
35			`elsif x = 3 then return(23);`
36			`elsif x = 4 then return(19);`
37			`elsif x = 5 then return(15);`
38			`elsif x = 6 then return(11);`
39			`else return(31);`
40			`end if;`
41			`end calc_msb_addr;`
42			`end coreahblite_support;`
43			`-- ========================================================================`
44
45			`library ieee;`
46			`use ieee.std_logic_1164.all;`
47			`use ieee.numeric_std.all;`
48			`use work.coreahblite_support.all;`
49
50			`entity COREAHBLITE_ADDRDEC is`
51			`generic (`
52			`MEMSPACE : integer range 0 to 6 := 0;`
53			`HADDR_SHG_CFG : integer range 0 to 1 := 1;`
54			`M_AHBSLOTENABLE : integer range 0 to (217)-1 := (217)-1;`
55			`SC : integer range 0 to (2**16)-1 := 0`
56			`);`
57			`port (`
58			`ADDR : in std_logic_vector(31 downto 0);`
59			`REMAP : in std_logic;`
60			`ADDRDEC : out std_logic_vector(16 downto 0);`
61			`ABSOLUTEADDR : out std_logic_vector(31 downto 0);`
62			`RESERVEDDEC : out std_logic`
63			`);`
64			`end entity COREAHBLITE_ADDRDEC;`
65
66			`architecture COREAHBLITE_ADDRDEC_arch of COREAHBLITE_ADDRDEC is`
67
68			`constant SLAVE_0 : std_logic_vector(15 downto 0) := "0000000000000001";`
69			`constant SLAVE_1 : std_logic_vector(15 downto 0) := "0000000000000010";`
70			`constant SLAVE_2 : std_logic_vector(15 downto 0) := "0000000000000100";`
71			`constant SLAVE_3 : std_logic_vector(15 downto 0) := "0000000000001000";`
72			`constant SLAVE_4 : std_logic_vector(15 downto 0) := "0000000000010000";`
73			`constant SLAVE_5 : std_logic_vector(15 downto 0) := "0000000000100000";`
74			`constant SLAVE_6 : std_logic_vector(15 downto 0) := "0000000001000000";`
75			`constant SLAVE_7 : std_logic_vector(15 downto 0) := "0000000010000000";`
76			`constant SLAVE_8 : std_logic_vector(15 downto 0) := "0000000100000000";`
77			`constant SLAVE_9 : std_logic_vector(15 downto 0) := "0000001000000000";`
78			`constant SLAVE_10 : std_logic_vector(15 downto 0) := "0000010000000000";`
79			`constant SLAVE_11 : std_logic_vector(15 downto 0) := "0000100000000000";`
80			`constant SLAVE_12 : std_logic_vector(15 downto 0) := "0001000000000000";`
81			`constant SLAVE_13 : std_logic_vector(15 downto 0) := "0010000000000000";`
82			`constant SLAVE_14 : std_logic_vector(15 downto 0) := "0100000000000000";`
83			`constant SLAVE_15 : std_logic_vector(15 downto 0) := "1000000000000000";`
84			`constant NONE : std_logic_vector(15 downto 0) := "0000000000000000";`
85
86			`constant SC_slv : std_logic_vector(15 downto 0):=`
87			`std_logic_vector(to_unsigned(SC,16));`
88
89			`constant MSB_ADDR : integer := calc_msb_addr(MEMSPACE);`
90
91			`signal sdec_raw : std_logic_vector(15 downto 0);`
92			`signal sdec : std_logic_vector(15 downto 0);`
93			`signal s16dec : std_logic;`
94			`signal absaddr : std_logic_vector(31 downto 0);`
95			`signal ADDRDEC_pre : std_logic_vector(16 downto 0);`
96
97			`signal slotdec : std_logic_vector(3 downto 0);`
98			`signal m0_hugeslotdec : std_logic;`
99			`signal m0_otherslotsdec : std_logic;`
100
101
102			`begin`
103			`g_mem0_00 : if (MEMSPACE = 0) generate`
104			`begin`
105			`m0_hugeslotdec <= '1' when (ADDR(31) = '1') else '0';`
106			`m0_otherslotsdec <= '1' when (ADDR(30 downto 20) = "00000000000") else '0';`
107			`slotdec <= ADDR(19 downto 16);`
108			`process (ADDR, m0_hugeslotdec, m0_otherslotsdec, slotdec, REMAP)`
109			`begin`
110			`absaddr(31 downto 0) <= ADDR(31 downto 0);`
111			`sdec_raw(15 downto 0) <= NONE;`
112			`if (m0_hugeslotdec = '1') then`
113			`if (HADDR_SHG_CFG = 0) then`
114			`absaddr(31) <= '0';`
115			`else`
116			`absaddr(31) <= '1';`
117			`end if;`
118			`elsif (m0_otherslotsdec = '1') then`
119			`case slotdec is`
120			`when "0000" =>`
121			`if (REMAP = '0') then`
122			`sdec_raw(15 downto 0) <= SLAVE_0;`
123			`else`
124			`absaddr(16) <= '1';`
125			`sdec_raw(15 downto 0) <= SLAVE_1;`
126			`end if;`
127			`when "0001" =>`
128			`if (REMAP = '0') then`
129			`sdec_raw(15 downto 0) <= SLAVE_1;`
130			`else`
131			`absaddr(16) <= '0';`
132			`sdec_raw(15 downto 0) <= SLAVE_0;`
133			`end if;`
134			`when "0010" => sdec_raw(15 downto 0) <= SLAVE_2;`
135			`when "0011" => sdec_raw(15 downto 0) <= SLAVE_3;`
136			`when "0100" => sdec_raw(15 downto 0) <= SLAVE_4;`
137			`when "0101" => sdec_raw(15 downto 0) <= SLAVE_5;`
138			`when "0110" => sdec_raw(15 downto 0) <= SLAVE_6;`
139			`when "0111" => sdec_raw(15 downto 0) <= SLAVE_7;`
140			`when "1000" => sdec_raw(15 downto 0) <= SLAVE_8;`
141			`when "1001" => sdec_raw(15 downto 0) <= SLAVE_9;`
142			`when "1010" => sdec_raw(15 downto 0) <= SLAVE_10;`
143			`when "1011" => sdec_raw(15 downto 0) <= SLAVE_11;`
144			`when "1100" => sdec_raw(15 downto 0) <= SLAVE_12;`
145			`when "1101" => sdec_raw(15 downto 0) <= SLAVE_13;`
146			`when "1110" => sdec_raw(15 downto 0) <= SLAVE_14;`
147			`when others => sdec_raw(15 downto 0) <= SLAVE_15;`
148			`end case;`
149			`end if;`
150			`end process;`
151
152			`sdec(15) <= sdec_raw(15);`
153			`sdec(14) <= sdec_raw(14);`
154			`sdec(13) <= sdec_raw(13);`
155			`sdec(12) <= sdec_raw(12);`
156			`sdec(11) <= sdec_raw(11);`
157			`sdec(10) <= sdec_raw(10);`
158			`sdec(9) <= sdec_raw(9);`
159			`sdec(8) <= sdec_raw(8);`
160			`sdec(7) <= sdec_raw(7);`
161			`sdec(6) <= sdec_raw(6);`
162			`sdec(5) <= sdec_raw(5);`
163			`sdec(4) <= sdec_raw(4);`
164			`sdec(3) <= sdec_raw(3);`
165			`sdec(2) <= sdec_raw(2);`
166			`sdec(1) <= sdec_raw(1);`
167			`sdec(0) <= sdec_raw(0);`
168
169			`s16dec <= m0_hugeslotdec;`
170
171			`RESERVEDDEC <= '1' when m0_hugeslotdec='0' and m0_otherslotsdec='0'`
172			`else '0';`
173			`end generate;`
174
175			`g_mem1_00 : if (not(MEMSPACE = 0)) generate`
176			`begin`
177			`m0_hugeslotdec <= '0';`
178			`m0_otherslotsdec <= '0';`
179			`slotdec <= ADDR(MSB_ADDR downto MSB_ADDR-3);`
180			`process (ADDR, slotdec, REMAP)`
181			`begin`
182			`absaddr(31 downto 0) <= ADDR(31 downto 0);`
183			`case slotdec is`
184			`when "0000" =>`
185			`if (REMAP = '0') then`
186			`sdec_raw(15 downto 0) <= SLAVE_0;`
187			`else`
188			`absaddr(MSB_ADDR-3) <= '1';`
189			`sdec_raw(15 downto 0) <= SLAVE_1;`
190			`end if;`
191			`when "0001" =>`
192			`if (REMAP = '0') then`
193			`sdec_raw(15 downto 0) <= SLAVE_1;`
194			`else`
195			`absaddr(MSB_ADDR-3) <= '0';`
196			`sdec_raw(15 downto 0) <= SLAVE_0;`
197			`end if;`
198			`when "0010" => sdec_raw(15 downto 0) <= SLAVE_2;`
199			`when "0011" => sdec_raw(15 downto 0) <= SLAVE_3;`
200			`when "0100" => sdec_raw(15 downto 0) <= SLAVE_4;`
201			`when "0101" => sdec_raw(15 downto 0) <= SLAVE_5;`
202			`when "0110" => sdec_raw(15 downto 0) <= SLAVE_6;`
203			`when "0111" => sdec_raw(15 downto 0) <= SLAVE_7;`
204			`when "1000" => sdec_raw(15 downto 0) <= SLAVE_8;`
205			`when "1001" => sdec_raw(15 downto 0) <= SLAVE_9;`
206			`when "1010" => sdec_raw(15 downto 0) <= SLAVE_10;`
207			`when "1011" => sdec_raw(15 downto 0) <= SLAVE_11;`
208			`when "1100" => sdec_raw(15 downto 0) <= SLAVE_12;`
209			`when "1101" => sdec_raw(15 downto 0) <= SLAVE_13;`
210			`when "1110" => sdec_raw(15 downto 0) <= SLAVE_14;`
211			`when others => sdec_raw(15 downto 0) <= SLAVE_15;`
212			`end case;`
213			`end process;`
214
215			`sdec(15) <= sdec_raw(15) and not(SC_slv(15));`
216			`sdec(14) <= sdec_raw(14) and not(SC_slv(14));`
217			`sdec(13) <= sdec_raw(13) and not(SC_slv(13));`
218			`sdec(12) <= sdec_raw(12) and not(SC_slv(12));`
219			`sdec(11) <= sdec_raw(11) and not(SC_slv(11));`
220			`sdec(10) <= sdec_raw(10) and not(SC_slv(10));`
221			`sdec(9) <= sdec_raw(9) and not(SC_slv(9));`
222			`sdec(8) <= sdec_raw(8) and not(SC_slv(8));`
223			`sdec(7) <= sdec_raw(7) and not(SC_slv(7));`
224			`sdec(6) <= sdec_raw(6) and not(SC_slv(6));`
225			`sdec(5) <= sdec_raw(5) and not(SC_slv(5));`
226			`sdec(4) <= sdec_raw(4) and not(SC_slv(4));`
227			`sdec(3) <= sdec_raw(3) and not(SC_slv(3));`
228			`sdec(2) <= sdec_raw(2) and not(SC_slv(2));`
229			`sdec(1) <= sdec_raw(1) and not(SC_slv(1));`
230			`sdec(0) <= sdec_raw(0) and not(SC_slv(0));`
231
232			`s16dec <= (sdec_raw(15) and SC_slv(15))`
233			`or (sdec_raw(14) and SC_slv(14))`
234			`or (sdec_raw(13) and SC_slv(13))`
235			`or (sdec_raw(12) and SC_slv(12))`
236			`or (sdec_raw(11) and SC_slv(11))`
237			`or (sdec_raw(10) and SC_slv(10))`
238			`or (sdec_raw(9) and SC_slv(9) )`
239			`or (sdec_raw(8) and SC_slv(8) )`
240			`or (sdec_raw(7) and SC_slv(7) )`
241			`or (sdec_raw(6) and SC_slv(6) )`
242			`or (sdec_raw(5) and SC_slv(5) )`
243			`or (sdec_raw(4) and SC_slv(4) )`
244			`or (sdec_raw(3) and SC_slv(3) )`
245			`or (sdec_raw(2) and SC_slv(2) )`
246			`or (sdec_raw(1) and SC_slv(1) )`
247			`or (sdec_raw(0) and SC_slv(0) );`
248
249			`RESERVEDDEC <= '0';`
250			`end generate;`
251
252			`ADDRDEC_pre(16 downto 0) <= (s16dec & sdec(15 downto 0));`
253			`ABSOLUTEADDR(31 downto 0) <= absaddr(31 downto 0);`
254			`ADDRDEC(16 downto 0) <= ADDRDEC_pre(16 downto 0);`
255
256			`end architecture COREAHBLITE_ADDRDEC_arch;`