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-- ********************************************************************/
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-- Actel Corporation Proprietary and Confidential
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-- Copyright 2010 Actel Corporation. All rights reserved.
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--
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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--
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-- Description: CoreAHBLite master stage logic for
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-- matrix (2 masters by 16 slaves),
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-- instantiates the following modules:
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-- COREAHBLITE_ADDRDEC, COREAHBLITE_DEFAULTSLAVESM
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--
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--
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-- SVN Revision Information:
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-- SVN $Revision: 23120 $
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-- SVN $Date: 2014-07-17 19:56:23 +0530 (Thu, 17 Jul 2014) $
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--
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--
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-- *********************************************************************/
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity COREAHBLITE_MASTERSTAGE is
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generic (
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MEMSPACE : integer range 0 to 6 := 0;
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HADDR_SHG_CFG : integer range 0 to 1 := 1;
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SC : integer range 0 to (2**16)-1 := 0;
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M_AHBSLOTENABLE : integer range 0 to (2**17)-1 := (2**17)-1;
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SYNC_RESET : integer := 0
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);
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port (
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HCLK : in std_logic;
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HRESETN : in std_logic;
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HADDR : in std_logic_vector(31 downto 0);
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HMASTLOCK : in std_logic;
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HSIZE : in std_logic_vector(2 downto 0);
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HTRANS : in std_logic;
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HWRITE : in std_logic;
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HRESP : out std_logic;
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HRDATA : out std_logic_vector(31 downto 0);
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HREADY_M : out std_logic;
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REMAP : in std_logic;
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SADDRREADY : in std_logic_vector(16 downto 0);
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SDATAREADY : in std_logic_vector(16 downto 0);
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SHRESP : in std_logic_vector(16 downto 0);
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GATEDHADDR : out std_logic_vector(31 downto 0);
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GATEDHMASTLOCK : out std_logic;
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GATEDHSIZE : out std_logic_vector(2 downto 0);
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GATEDHTRANS : out std_logic;
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GATEDHWRITE : out std_logic;
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SADDRSEL : out std_logic_vector(16 downto 0);
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SDATASEL : out std_logic_vector(16 downto 0);
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PREVDATASLAVEREADY : out std_logic;
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HRDATA_S0 : in std_logic_vector(31 downto 0);
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HREADYOUT_S0 : in std_logic;
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HRDATA_S1 : in std_logic_vector(31 downto 0);
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HREADYOUT_S1 : in std_logic;
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HRDATA_S2 : in std_logic_vector(31 downto 0);
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HREADYOUT_S2 : in std_logic;
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HRDATA_S3 : in std_logic_vector(31 downto 0);
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HREADYOUT_S3 : in std_logic;
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HRDATA_S4 : in std_logic_vector(31 downto 0);
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HREADYOUT_S4 : in std_logic;
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HRDATA_S5 : in std_logic_vector(31 downto 0);
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HREADYOUT_S5 : in std_logic;
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HRDATA_S6 : in std_logic_vector(31 downto 0);
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HREADYOUT_S6 : in std_logic;
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HRDATA_S7 : in std_logic_vector(31 downto 0);
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HREADYOUT_S7 : in std_logic;
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HRDATA_S8 : in std_logic_vector(31 downto 0);
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HREADYOUT_S8 : in std_logic;
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HRDATA_S9 : in std_logic_vector(31 downto 0);
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HREADYOUT_S9 : in std_logic;
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HRDATA_S10 : in std_logic_vector(31 downto 0);
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HREADYOUT_S10 : in std_logic;
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HRDATA_S11 : in std_logic_vector(31 downto 0);
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HREADYOUT_S11 : in std_logic;
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HRDATA_S12 : in std_logic_vector(31 downto 0);
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HREADYOUT_S12 : in std_logic;
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HRDATA_S13 : in std_logic_vector(31 downto 0);
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HREADYOUT_S13 : in std_logic;
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HRDATA_S14 : in std_logic_vector(31 downto 0);
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HREADYOUT_S14 : in std_logic;
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HRDATA_S15 : in std_logic_vector(31 downto 0);
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HREADYOUT_S15 : in std_logic;
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HRDATA_S16 : in std_logic_vector(31 downto 0);
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HREADYOUT_S16 : in std_logic
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);
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end entity COREAHBLITE_MASTERSTAGE;
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architecture COREAHBLITE_MASTERSTAGE_arch of COREAHBLITE_MASTERSTAGE is
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function or_v (
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v : std_logic_vector) return std_logic is
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variable sl : std_logic := '0';
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begin
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for i in v'range loop
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sl := sl or v(i);
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end loop;
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return(sl);
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end or_v;
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constant IDLE : std_logic := '0';
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constant REGISTERED : std_logic := '1';
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constant SLAVE_NONE : std_logic_vector(16 downto 0):=(others=>'0');
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constant CLIENT_NONE : std_logic_vector(15 downto 0):=(others=>'0');
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constant M_AHBSLOTENABLE_slv : std_logic_vector(16 downto 0):=
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std_logic_vector(to_unsigned(M_AHBSLOTENABLE,17));
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component COREAHBLITE_ADDRDEC is
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generic (
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MEMSPACE : integer range 0 to 6 := 0;
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HADDR_SHG_CFG : integer range 0 to 1 := 0;
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M_AHBSLOTENABLE : integer range 0 to (2**17)-1 := (2**17)-1;
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SC : integer range 0 to (2**16)-1 := 0
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);
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port (
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ADDR : in std_logic_vector(31 downto 0);
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REMAP : in std_logic;
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ADDRDEC : out std_logic_vector(16 downto 0);
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ABSOLUTEADDR : out std_logic_vector(31 downto 0);
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RESERVEDDEC : out std_logic
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);
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end component;
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component COREAHBLITE_DEFAULTSLAVESM is
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generic(SYNC_RESET : integer := 0);
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port (
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HCLK : in std_logic;
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HRESETN : in std_logic;
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DEFSLAVEDATASEL : in std_logic;
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DEFSLAVEDATAREADY : out std_logic;
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HRESP_DEFAULT : out std_logic
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);
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end component;
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signal PREGATEDHADDR : std_logic_vector(31 downto 0);
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signal masterRegAddrSel : std_logic;
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signal d_masterRegAddrSel : std_logic;
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signal masterAddrClockEnable : std_logic;
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signal regHADDR : std_logic_vector(31 downto 0);
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signal regHMASTLOCK : std_logic;
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signal regHSIZE : std_logic_vector(2 downto 0);
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signal regHTRANS : std_logic;
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signal regHWRITE : std_logic;
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signal addrRegSMCurrentState : std_logic;
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signal addrRegSMNextState : std_logic;
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signal sAddrDec : std_logic_vector(16 downto 0);
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signal SADDRSELInt : std_logic_vector(16 downto 0);
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signal SDATASELInt : std_logic_vector(16 downto 0);
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signal datasel_onehot : std_logic_vector(16 downto 0);
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signal DEFSLAVEDATAREADY : std_logic;
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signal HRESP_DEFAULT : std_logic;
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signal DEFSLAVEDATASEL : std_logic;
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signal DEFSLAVEDATASEL0 : std_logic;
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signal DEFSLAVEDATASEL1 : std_logic;
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signal DEFSLAVEDATASEL2 : std_logic;
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signal DEFSLAVEDATASEL3 : std_logic;
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signal DEFSLAVEDATASEL4 : std_logic;
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signal DEFSLAVEDATASEL5 : std_logic;
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signal DEFSLAVEDATASEL6 : std_logic;
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signal DEFSLAVEDATASEL7 : std_logic;
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signal DEFSLAVEDATASEL8 : std_logic;
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signal DEFSLAVEDATASEL9 : std_logic;
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signal DEFSLAVEDATASEL10 : std_logic;
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signal DEFSLAVEDATASEL11 : std_logic;
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signal DEFSLAVEDATASEL12 : std_logic;
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signal DEFSLAVEDATASEL13 : std_logic;
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signal DEFSLAVEDATASEL14 : std_logic;
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signal DEFSLAVEDATASEL15 : std_logic;
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signal DEFSLAVEDATASEL16 : std_logic;
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signal ReservedDecode : std_logic;
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signal RESERVEDADDRSELInt : std_logic;
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signal RESERVEDDATASELInt : std_logic;
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signal HREADY_M_pre : std_logic;
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-- Declare intermediate signals for referenced outputs
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signal HREADY_M_xhdl3 : std_logic;
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signal GATEDHADDR_xhdl0 : std_logic_vector(31 downto 0);
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signal GATEDHTRANS_xhdl1 : std_logic;
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signal GATEDHWRITE_xhdl2 : std_logic;
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signal PREVDATASLAVEREADY_xhdl4 : std_logic;
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signal aresetn : std_logic;
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signal sresetn : std_logic;
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begin
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aresetn <= '1' WHEN (SYNC_RESET=1) ELSE HRESETN;
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sresetn <= HRESETN WHEN (SYNC_RESET=1) ELSE '1';
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-- Drive referenced outputs
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HREADY_M <= HREADY_M_pre;
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GATEDHADDR <= GATEDHADDR_xhdl0;
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GATEDHTRANS <= GATEDHTRANS_xhdl1;
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GATEDHWRITE <= GATEDHWRITE_xhdl2;
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PREVDATASLAVEREADY <= PREVDATASLAVEREADY_xhdl4;
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SADDRSEL <= SADDRSELInt(16 downto 0);
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SDATASEL <= SDATASELInt(16 downto 0);
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DEFSLAVEDATASEL0 <= (SDATASELInt(0) and (not(M_AHBSLOTENABLE_slv(0))));
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DEFSLAVEDATASEL1 <= (SDATASELInt(1) and (not(M_AHBSLOTENABLE_slv(1))));
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DEFSLAVEDATASEL2 <= (SDATASELInt(2) and (not(M_AHBSLOTENABLE_slv(2))));
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DEFSLAVEDATASEL3 <= (SDATASELInt(3) and (not(M_AHBSLOTENABLE_slv(3))));
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DEFSLAVEDATASEL4 <= (SDATASELInt(4) and (not(M_AHBSLOTENABLE_slv(4))));
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DEFSLAVEDATASEL5 <= (SDATASELInt(5) and (not(M_AHBSLOTENABLE_slv(5))));
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DEFSLAVEDATASEL6 <= (SDATASELInt(6) and (not(M_AHBSLOTENABLE_slv(6))));
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DEFSLAVEDATASEL7 <= (SDATASELInt(7) and (not(M_AHBSLOTENABLE_slv(7))));
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DEFSLAVEDATASEL8 <= (SDATASELInt(8) and (not(M_AHBSLOTENABLE_slv(8))));
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DEFSLAVEDATASEL9 <= (SDATASELInt(9) and (not(M_AHBSLOTENABLE_slv(9))));
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DEFSLAVEDATASEL10 <= (SDATASELInt(10) and (not(M_AHBSLOTENABLE_slv(10))));
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DEFSLAVEDATASEL11 <= (SDATASELInt(11) and (not(M_AHBSLOTENABLE_slv(11))));
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DEFSLAVEDATASEL12 <= (SDATASELInt(12) and (not(M_AHBSLOTENABLE_slv(12))));
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DEFSLAVEDATASEL13 <= (SDATASELInt(13) and (not(M_AHBSLOTENABLE_slv(13))));
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DEFSLAVEDATASEL14 <= (SDATASELInt(14) and (not(M_AHBSLOTENABLE_slv(14))));
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DEFSLAVEDATASEL15 <= (SDATASELInt(15) and (not(M_AHBSLOTENABLE_slv(15))));
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DEFSLAVEDATASEL16 <= (SDATASELInt(16) and (not(M_AHBSLOTENABLE_slv(16))));
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DEFSLAVEDATASEL <= (
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DEFSLAVEDATASEL0 or DEFSLAVEDATASEL1 or
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DEFSLAVEDATASEL2 or DEFSLAVEDATASEL3 or
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DEFSLAVEDATASEL4 or DEFSLAVEDATASEL5 or
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DEFSLAVEDATASEL6 or DEFSLAVEDATASEL7 or
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DEFSLAVEDATASEL8 or DEFSLAVEDATASEL9 or
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DEFSLAVEDATASEL10 or DEFSLAVEDATASEL11 or
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DEFSLAVEDATASEL12 or DEFSLAVEDATASEL13 or
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DEFSLAVEDATASEL14 or DEFSLAVEDATASEL15 or
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DEFSLAVEDATASEL16
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or RESERVEDDATASELInt
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);
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process (HCLK, aresetn)
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begin
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if ((not(aresetn)) = '1') then
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regHADDR <= "00000000000000000000000000000000";
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regHMASTLOCK <= '0';
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regHSIZE <= "000";
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regHTRANS <= '0';
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regHWRITE <= '0';
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elsif (HCLK'event and HCLK = '1') then
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if ((not(sresetn)) = '1') then
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regHADDR <= "00000000000000000000000000000000";
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regHMASTLOCK <= '0';
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regHSIZE <= "000";
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regHTRANS <= '0';
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regHWRITE <= '0';
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else
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if (masterAddrClockEnable = '1') then
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regHADDR <= HADDR;
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regHMASTLOCK <= HMASTLOCK;
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regHSIZE <= HSIZE;
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regHTRANS <= HTRANS;
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regHWRITE <= HWRITE;
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end if;
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end if;
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end if;
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end process;
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process (masterRegAddrSel, HADDR, HMASTLOCK, HSIZE, HTRANS, HWRITE, regHADDR, regHMASTLOCK, regHSIZE, regHTRANS, regHWRITE)
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begin
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if (masterRegAddrSel = '0') then
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PREGATEDHADDR <= HADDR;
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GATEDHMASTLOCK <= HMASTLOCK;
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GATEDHSIZE <= HSIZE;
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GATEDHTRANS_xhdl1 <= HTRANS;
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GATEDHWRITE_xhdl2 <= HWRITE;
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else
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PREGATEDHADDR <= regHADDR;
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GATEDHMASTLOCK <= regHMASTLOCK;
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GATEDHSIZE <= regHSIZE;
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GATEDHTRANS_xhdl1 <= regHTRANS;
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GATEDHWRITE_xhdl2 <= regHWRITE;
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end if;
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end process;
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address_decode : COREAHBLITE_ADDRDEC
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generic map (
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MEMSPACE => MEMSPACE,
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HADDR_SHG_CFG => HADDR_SHG_CFG,
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M_AHBSLOTENABLE => M_AHBSLOTENABLE,
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SC => SC
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)
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port map (
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ADDR => PREGATEDHADDR,
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|
|
REMAP => REMAP,
|
| 287 |
|
|
ADDRDEC => sAddrDec(16 downto 0),
|
| 288 |
|
|
ABSOLUTEADDR => GATEDHADDR_xhdl0(31 downto 0),
|
| 289 |
|
|
RESERVEDDEC => ReservedDecode
|
| 290 |
|
|
);
|
| 291 |
|
|
|
| 292 |
|
|
process (GATEDHTRANS_xhdl1, sAddrDec, ReservedDecode)
|
| 293 |
|
|
begin
|
| 294 |
|
|
if (GATEDHTRANS_xhdl1 = '1') then
|
| 295 |
|
|
SADDRSELInt <= sAddrDec;
|
| 296 |
|
|
RESERVEDADDRSELInt <= ReservedDecode;
|
| 297 |
|
|
else
|
| 298 |
|
|
SADDRSELInt <= SLAVE_NONE;
|
| 299 |
|
|
RESERVEDADDRSELInt <= '0';
|
| 300 |
|
|
end if;
|
| 301 |
|
|
end process;
|
| 302 |
|
|
|
| 303 |
|
|
process (HCLK, aresetn)
|
| 304 |
|
|
begin
|
| 305 |
|
|
if ((not(aresetn)) = '1') then
|
| 306 |
|
|
SDATASELInt <= SLAVE_NONE;
|
| 307 |
|
|
elsif (HCLK'event and HCLK = '1') then
|
| 308 |
|
|
if ((not(sresetn)) = '1') then
|
| 309 |
|
|
SDATASELInt <= SLAVE_NONE;
|
| 310 |
|
|
else
|
| 311 |
|
|
if (PREVDATASLAVEREADY_xhdl4 = '1') then
|
| 312 |
|
|
SDATASELInt <= SADDRSELInt;
|
| 313 |
|
|
end if;
|
| 314 |
|
|
end if;
|
| 315 |
|
|
end if;
|
| 316 |
|
|
end process;
|
| 317 |
|
|
|
| 318 |
|
|
process (HCLK, aresetn)
|
| 319 |
|
|
begin
|
| 320 |
|
|
if ((not(aresetn)) = '1') then
|
| 321 |
|
|
RESERVEDDATASELInt <= '0';
|
| 322 |
|
|
elsif (HCLK'event and HCLK = '1') then
|
| 323 |
|
|
if ((not(sresetn)) = '1') then
|
| 324 |
|
|
RESERVEDDATASELInt <= '0';
|
| 325 |
|
|
else
|
| 326 |
|
|
if (PREVDATASLAVEREADY_xhdl4 = '1') then
|
| 327 |
|
|
RESERVEDDATASELInt <= RESERVEDADDRSELInt;
|
| 328 |
|
|
end if;
|
| 329 |
|
|
end if;
|
| 330 |
|
|
end if;
|
| 331 |
|
|
end process;
|
| 332 |
|
|
|
| 333 |
|
|
datasel_onehot <= SDATASELInt(16 downto 0);
|
| 334 |
|
|
process (
|
| 335 |
|
|
RESERVEDDATASELInt,
|
| 336 |
|
|
DEFSLAVEDATAREADY,
|
| 337 |
|
|
HRESP_DEFAULT,
|
| 338 |
|
|
datasel_onehot,
|
| 339 |
|
|
SDATAREADY,
|
| 340 |
|
|
SHRESP,
|
| 341 |
|
|
HRDATA_S0, HREADYOUT_S0,
|
| 342 |
|
|
HRDATA_S1, HREADYOUT_S1,
|
| 343 |
|
|
HRDATA_S2, HREADYOUT_S2,
|
| 344 |
|
|
HRDATA_S3, HREADYOUT_S3,
|
| 345 |
|
|
HRDATA_S4, HREADYOUT_S4,
|
| 346 |
|
|
HRDATA_S5, HREADYOUT_S5,
|
| 347 |
|
|
HRDATA_S6, HREADYOUT_S6,
|
| 348 |
|
|
HRDATA_S7, HREADYOUT_S7,
|
| 349 |
|
|
HRDATA_S8, HREADYOUT_S8,
|
| 350 |
|
|
HRDATA_S9, HREADYOUT_S9,
|
| 351 |
|
|
HRDATA_S10, HREADYOUT_S10,
|
| 352 |
|
|
HRDATA_S11, HREADYOUT_S11,
|
| 353 |
|
|
HRDATA_S12, HREADYOUT_S12,
|
| 354 |
|
|
HRDATA_S13, HREADYOUT_S13,
|
| 355 |
|
|
HRDATA_S14, HREADYOUT_S14,
|
| 356 |
|
|
HRDATA_S15, HREADYOUT_S15,
|
| 357 |
|
|
HRDATA_S16, HREADYOUT_S16
|
| 358 |
|
|
)
|
| 359 |
|
|
begin
|
| 360 |
|
|
if (RESERVEDDATASELInt='1') then
|
| 361 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 362 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 363 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 364 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 365 |
|
|
else
|
| 366 |
|
|
case datasel_onehot is
|
| 367 |
|
|
when "00000000000000001" =>
|
| 368 |
|
|
if ((M_AHBSLOTENABLE_slv(0)) = '1') then
|
| 369 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(0);
|
| 370 |
|
|
HRESP <= SHRESP(0);
|
| 371 |
|
|
HRDATA <= HRDATA_S0;
|
| 372 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S0;
|
| 373 |
|
|
else
|
| 374 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 375 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 376 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 377 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 378 |
|
|
end if;
|
| 379 |
|
|
when "00000000000000010" =>
|
| 380 |
|
|
if ((M_AHBSLOTENABLE_slv(1)) = '1') then
|
| 381 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(1);
|
| 382 |
|
|
HRESP <= SHRESP(1);
|
| 383 |
|
|
HRDATA <= HRDATA_S1;
|
| 384 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S1;
|
| 385 |
|
|
else
|
| 386 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 387 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 388 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 389 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 390 |
|
|
end if;
|
| 391 |
|
|
when "00000000000000100" =>
|
| 392 |
|
|
if ((M_AHBSLOTENABLE_slv(2)) = '1') then
|
| 393 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(2);
|
| 394 |
|
|
HRESP <= SHRESP(2);
|
| 395 |
|
|
HRDATA <= HRDATA_S2;
|
| 396 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S2;
|
| 397 |
|
|
else
|
| 398 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 399 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 400 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 401 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 402 |
|
|
end if;
|
| 403 |
|
|
when "00000000000001000" =>
|
| 404 |
|
|
if ((M_AHBSLOTENABLE_slv(3)) = '1') then
|
| 405 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(3);
|
| 406 |
|
|
HRESP <= SHRESP(3);
|
| 407 |
|
|
HRDATA <= HRDATA_S3;
|
| 408 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S3;
|
| 409 |
|
|
else
|
| 410 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 411 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 412 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 413 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 414 |
|
|
end if;
|
| 415 |
|
|
when "00000000000010000" =>
|
| 416 |
|
|
if ((M_AHBSLOTENABLE_slv(4)) = '1') then
|
| 417 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(4);
|
| 418 |
|
|
HRESP <= SHRESP(4);
|
| 419 |
|
|
HRDATA <= HRDATA_S4;
|
| 420 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S4;
|
| 421 |
|
|
else
|
| 422 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 423 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 424 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 425 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 426 |
|
|
end if;
|
| 427 |
|
|
when "00000000000100000" =>
|
| 428 |
|
|
if ((M_AHBSLOTENABLE_slv(5)) = '1') then
|
| 429 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(5);
|
| 430 |
|
|
HRESP <= SHRESP(5);
|
| 431 |
|
|
HRDATA <= HRDATA_S5;
|
| 432 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S5;
|
| 433 |
|
|
else
|
| 434 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 435 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 436 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 437 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 438 |
|
|
end if;
|
| 439 |
|
|
when "00000000001000000" =>
|
| 440 |
|
|
if ((M_AHBSLOTENABLE_slv(6)) = '1') then
|
| 441 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(6);
|
| 442 |
|
|
HRESP <= SHRESP(6);
|
| 443 |
|
|
HRDATA <= HRDATA_S6;
|
| 444 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S6;
|
| 445 |
|
|
else
|
| 446 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 447 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 448 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 449 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 450 |
|
|
end if;
|
| 451 |
|
|
when "00000000010000000" =>
|
| 452 |
|
|
if ((M_AHBSLOTENABLE_slv(7)) = '1') then
|
| 453 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(7);
|
| 454 |
|
|
HRESP <= SHRESP(7);
|
| 455 |
|
|
HRDATA <= HRDATA_S7;
|
| 456 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S7;
|
| 457 |
|
|
else
|
| 458 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 459 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 460 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 461 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 462 |
|
|
end if;
|
| 463 |
|
|
when "00000000100000000" =>
|
| 464 |
|
|
if ((M_AHBSLOTENABLE_slv(8)) = '1') then
|
| 465 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(8);
|
| 466 |
|
|
HRESP <= SHRESP(8);
|
| 467 |
|
|
HRDATA <= HRDATA_S8;
|
| 468 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S8;
|
| 469 |
|
|
else
|
| 470 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 471 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 472 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 473 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 474 |
|
|
end if;
|
| 475 |
|
|
when "00000001000000000" =>
|
| 476 |
|
|
if ((M_AHBSLOTENABLE_slv(9)) = '1') then
|
| 477 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(9);
|
| 478 |
|
|
HRESP <= SHRESP(9);
|
| 479 |
|
|
HRDATA <= HRDATA_S9;
|
| 480 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S9;
|
| 481 |
|
|
else
|
| 482 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 483 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 484 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 485 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 486 |
|
|
end if;
|
| 487 |
|
|
when "00000010000000000" =>
|
| 488 |
|
|
if ((M_AHBSLOTENABLE_slv(10)) = '1') then
|
| 489 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(10);
|
| 490 |
|
|
HRESP <= SHRESP(10);
|
| 491 |
|
|
HRDATA <= HRDATA_S10;
|
| 492 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S10;
|
| 493 |
|
|
else
|
| 494 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 495 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 496 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 497 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 498 |
|
|
end if;
|
| 499 |
|
|
when "00000100000000000" =>
|
| 500 |
|
|
if ((M_AHBSLOTENABLE_slv(11)) = '1') then
|
| 501 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(11);
|
| 502 |
|
|
HRESP <= SHRESP(11);
|
| 503 |
|
|
HRDATA <= HRDATA_S11;
|
| 504 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S11;
|
| 505 |
|
|
else
|
| 506 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 507 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 508 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 509 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 510 |
|
|
end if;
|
| 511 |
|
|
when "00001000000000000" =>
|
| 512 |
|
|
if ((M_AHBSLOTENABLE_slv(12)) = '1') then
|
| 513 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(12);
|
| 514 |
|
|
HRESP <= SHRESP(12);
|
| 515 |
|
|
HRDATA <= HRDATA_S12;
|
| 516 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S12;
|
| 517 |
|
|
else
|
| 518 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 519 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 520 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 521 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 522 |
|
|
end if;
|
| 523 |
|
|
when "00010000000000000" =>
|
| 524 |
|
|
if ((M_AHBSLOTENABLE_slv(13)) = '1') then
|
| 525 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(13);
|
| 526 |
|
|
HRESP <= SHRESP(13);
|
| 527 |
|
|
HRDATA <= HRDATA_S13;
|
| 528 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S13;
|
| 529 |
|
|
else
|
| 530 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 531 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 532 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 533 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 534 |
|
|
end if;
|
| 535 |
|
|
when "00100000000000000" =>
|
| 536 |
|
|
if ((M_AHBSLOTENABLE_slv(14)) = '1') then
|
| 537 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(14);
|
| 538 |
|
|
HRESP <= SHRESP(14);
|
| 539 |
|
|
HRDATA <= HRDATA_S14;
|
| 540 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S14;
|
| 541 |
|
|
else
|
| 542 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 543 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 544 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 545 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 546 |
|
|
end if;
|
| 547 |
|
|
when "01000000000000000" =>
|
| 548 |
|
|
if ((M_AHBSLOTENABLE_slv(15)) = '1') then
|
| 549 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(15);
|
| 550 |
|
|
HRESP <= SHRESP(15);
|
| 551 |
|
|
HRDATA <= HRDATA_S15;
|
| 552 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S15;
|
| 553 |
|
|
else
|
| 554 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 555 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 556 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 557 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 558 |
|
|
end if;
|
| 559 |
|
|
when "10000000000000000" =>
|
| 560 |
|
|
if ((M_AHBSLOTENABLE_slv(16)) = '1') then
|
| 561 |
|
|
HREADY_M_xhdl3 <= SDATAREADY(16);
|
| 562 |
|
|
HRESP <= SHRESP(16);
|
| 563 |
|
|
HRDATA <= HRDATA_S16;
|
| 564 |
|
|
PREVDATASLAVEREADY_xhdl4 <= HREADYOUT_S16;
|
| 565 |
|
|
else
|
| 566 |
|
|
HREADY_M_xhdl3 <= DEFSLAVEDATAREADY;
|
| 567 |
|
|
HRESP <= HRESP_DEFAULT;
|
| 568 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 569 |
|
|
PREVDATASLAVEREADY_xhdl4 <= DEFSLAVEDATAREADY;
|
| 570 |
|
|
end if;
|
| 571 |
|
|
when others =>
|
| 572 |
|
|
HREADY_M_xhdl3 <= '1';
|
| 573 |
|
|
HRESP <= '0';
|
| 574 |
|
|
HRDATA <= "00000000000000000000000000000000";
|
| 575 |
|
|
PREVDATASLAVEREADY_xhdl4 <= '1';
|
| 576 |
|
|
end case;
|
| 577 |
|
|
end if;
|
| 578 |
|
|
end process;
|
| 579 |
|
|
|
| 580 |
|
|
process (addrRegSMCurrentState, HTRANS, HREADY_M_xhdl3, sAddrDec, SADDRREADY)
|
| 581 |
|
|
begin
|
| 582 |
|
|
masterAddrClockEnable <= '0';
|
| 583 |
|
|
d_masterRegAddrSel <= '0';
|
| 584 |
|
|
case addrRegSMCurrentState is
|
| 585 |
|
|
when IDLE =>
|
| 586 |
|
|
if ((HTRANS and HREADY_M_xhdl3 and
|
| 587 |
|
|
((sAddrDec(0) and not(SADDRREADY(0))) or
|
| 588 |
|
|
(sAddrDec(1) and not(SADDRREADY(1))) or
|
| 589 |
|
|
(sAddrDec(2) and not(SADDRREADY(2))) or
|
| 590 |
|
|
(sAddrDec(3) and not(SADDRREADY(3))) or
|
| 591 |
|
|
(sAddrDec(4) and not(SADDRREADY(4))) or
|
| 592 |
|
|
(sAddrDec(5) and not(SADDRREADY(5))) or
|
| 593 |
|
|
(sAddrDec(6) and not(SADDRREADY(6))) or
|
| 594 |
|
|
(sAddrDec(7) and not(SADDRREADY(7))) or
|
| 595 |
|
|
(sAddrDec(8) and not(SADDRREADY(8))) or
|
| 596 |
|
|
(sAddrDec(9) and not(SADDRREADY(9))) or
|
| 597 |
|
|
(sAddrDec(10) and not(SADDRREADY(10))) or
|
| 598 |
|
|
(sAddrDec(11) and not(SADDRREADY(11))) or
|
| 599 |
|
|
(sAddrDec(12) and not(SADDRREADY(12))) or
|
| 600 |
|
|
(sAddrDec(13) and not(SADDRREADY(13))) or
|
| 601 |
|
|
(sAddrDec(14) and not(SADDRREADY(14))) or
|
| 602 |
|
|
(sAddrDec(15) and not(SADDRREADY(15))) or
|
| 603 |
|
|
(sAddrDec(16) and not(SADDRREADY(16)))
|
| 604 |
|
|
)) = '1'
|
| 605 |
|
|
) then
|
| 606 |
|
|
masterAddrClockEnable <= '1';
|
| 607 |
|
|
d_masterRegAddrSel <= '1';
|
| 608 |
|
|
addrRegSMNextState <= REGISTERED;
|
| 609 |
|
|
else
|
| 610 |
|
|
addrRegSMNextState <= IDLE;
|
| 611 |
|
|
end if;
|
| 612 |
|
|
when REGISTERED =>
|
| 613 |
|
|
if ((
|
| 614 |
|
|
(sAddrDec(0) and SADDRREADY(0)) or
|
| 615 |
|
|
(sAddrDec(1) and SADDRREADY(1)) or
|
| 616 |
|
|
(sAddrDec(2) and SADDRREADY(2)) or
|
| 617 |
|
|
(sAddrDec(3) and SADDRREADY(3)) or
|
| 618 |
|
|
(sAddrDec(4) and SADDRREADY(4)) or
|
| 619 |
|
|
(sAddrDec(5) and SADDRREADY(5)) or
|
| 620 |
|
|
(sAddrDec(6) and SADDRREADY(6)) or
|
| 621 |
|
|
(sAddrDec(7) and SADDRREADY(7)) or
|
| 622 |
|
|
(sAddrDec(8) and SADDRREADY(8)) or
|
| 623 |
|
|
(sAddrDec(9) and SADDRREADY(9)) or
|
| 624 |
|
|
(sAddrDec(10) and SADDRREADY(10)) or
|
| 625 |
|
|
(sAddrDec(11) and SADDRREADY(11)) or
|
| 626 |
|
|
(sAddrDec(12) and SADDRREADY(12)) or
|
| 627 |
|
|
(sAddrDec(13) and SADDRREADY(13)) or
|
| 628 |
|
|
(sAddrDec(14) and SADDRREADY(14)) or
|
| 629 |
|
|
(sAddrDec(15) and SADDRREADY(15)) or
|
| 630 |
|
|
(sAddrDec(16) and SADDRREADY(16))) = '1'
|
| 631 |
|
|
) then
|
| 632 |
|
|
addrRegSMNextState <= IDLE;
|
| 633 |
|
|
else
|
| 634 |
|
|
d_masterRegAddrSel <= '1';
|
| 635 |
|
|
addrRegSMNextState <= REGISTERED;
|
| 636 |
|
|
end if;
|
| 637 |
|
|
when others =>
|
| 638 |
|
|
addrRegSMNextState <= IDLE;
|
| 639 |
|
|
end case;
|
| 640 |
|
|
end process;
|
| 641 |
|
|
|
| 642 |
|
|
process (HCLK, aresetn)
|
| 643 |
|
|
begin
|
| 644 |
|
|
if ((not(aresetn)) = '1') then
|
| 645 |
|
|
addrRegSMCurrentState <= IDLE;
|
| 646 |
|
|
masterRegAddrSel <= '0';
|
| 647 |
|
|
elsif (HCLK'event and HCLK = '1') then
|
| 648 |
|
|
if ((not(sresetn)) = '1') then
|
| 649 |
|
|
addrRegSMCurrentState <= IDLE;
|
| 650 |
|
|
masterRegAddrSel <= '0';
|
| 651 |
|
|
else
|
| 652 |
|
|
addrRegSMCurrentState <= addrRegSMNextState;
|
| 653 |
|
|
masterRegAddrSel <= d_masterRegAddrSel;
|
| 654 |
|
|
end if;
|
| 655 |
|
|
end if;
|
| 656 |
|
|
end process;
|
| 657 |
|
|
|
| 658 |
|
|
default_slave_sm : COREAHBLITE_DEFAULTSLAVESM
|
| 659 |
|
|
generic map( SYNC_RESET => SYNC_RESET)
|
| 660 |
|
|
port map (
|
| 661 |
|
|
HCLK => HCLK,
|
| 662 |
|
|
HRESETN => HRESETN,
|
| 663 |
|
|
DEFSLAVEDATASEL => DEFSLAVEDATASEL,
|
| 664 |
|
|
DEFSLAVEDATAREADY => DEFSLAVEDATAREADY,
|
| 665 |
|
|
HRESP_DEFAULT => HRESP_DEFAULT
|
| 666 |
|
|
);
|
| 667 |
|
|
|
| 668 |
|
|
HREADY_M_pre <= HREADY_M_xhdl3;
|
| 669 |
|
|
|
| 670 |
|
|
end architecture COREAHBLITE_MASTERSTAGE_arch;
|
