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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreAHBLite_0/] [rtl/] [vhdl/] [test/] [user/] [testbench.vhd] - Blame information for rev 3

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1 3 uson 
-- ********************************************************************/
2 
-- Actel Corporation Proprietary and Confidential
3 
-- Copyright 2010 Actel Corporation.  All rights reserved.
4 
--
5 
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
6 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
7 
-- IN ADVANCE IN WRITING.
8 
--
9 
-- Description: CoreAHBLite - user testbench
10 
--
11 
-- Revision Information:
12 
-- Date                 Description
13 
-- ----                 -----------------------------------------
14 
-- 10Feb10              Production Release Version 3.1
15 
--
16 
-- SVN Revision Information:
17 
-- SVN $Revision: 29812 $
18 
-- SVN $Date: 2017-05-12 15:15:39 +0530 (Fri, 12 May 2017) $
19 
--
20 
-- Resolved SARs
21 
-- SAR      Date     Who   Description
22 
--
23 
-- Notes:
24 
-- 1. best viewed with tabstops set to "4" (tabs used throughout file)
25 
--
26 
-- *********************************************************************/
27 
 
28 
library ieee;
29 
use ieee.std_logic_1164.all;
30 
use ieee.numeric_std.all;
31 
use work.coreparameters.all;
32 
use work.top_CoreAHBLite_0_components.all;
33 
use work.bfm_package.all;
34 
 
35 
 
36 
entity testbench is
37 
generic (
38 
 
39 
SYSCLK_PERIOD       : integer := 10; -- 100MHz
40 
 
41 
-- the locations and names of these can be overridden at run time
42 
MASTER0_VECTFILE    : string := "coreahblite_usertb_ahb_master0.vec";
43 
MASTER1_VECTFILE    : string := "coreahblite_usertb_ahb_master1.vec";
44 
MASTER2_VECTFILE    : string := "coreahblite_usertb_ahb_master2.vec";
45 
MASTER3_VECTFILE    : string := "coreahblite_usertb_ahb_master3.vec";
46 
 
47 
-- propagation delay in ns
48 
TPD                 : integer := 3
49 
);
50 
end entity testbench;
51 
 
52 
architecture testbench_arch of testbench is
53 
 
54 
-----------------------------------------------------------------------------
55 
-- components
56 
-----------------------------------------------------------------------------
57 
-- from work.components ...
58 
 
59 
 
60 
signal stopsim          : integer range 0 to 1 := 0;
61 
 
62 
signal SYSCLK           : std_logic;
63 
signal SYSRSTN          : std_logic;
64 
 
65 
-- using HCLK & HRESETN from master 0 to connect to CoreAHBLite
66 
signal HCLK                     : std_logic;
67 
signal HRESETN          : std_logic;
68 
 
69 
-- control remap signal from master 0 BFM
70 
signal REMAP_M0         : std_logic;
71 
 
72 
-- GPIO for 2 master BFM's
73 
signal GP_OUT_M0        : std_logic_vector(31 downto 0);
74 
signal GP_OUT_M1        : std_logic_vector(31 downto 0);
75 
-- GP_IN shared
76 
signal GP_IN            : std_logic_vector(31 downto 0);
77 
 
78 
-- signals for testbench request/acknowledgement between masters
79 
signal M0_REQ           : std_logic;
80 
signal M0_ACK           : std_logic;
81 
signal M1_REQ           : std_logic;
82 
signal M1_ACK           : std_logic;
83 
 
84 
signal HREADY_M0               : std_logic;
85 
signal HRESP_M0                : std_logic_vector(1 downto 0);
86 
signal HRDATA_M0               : std_logic_vector(31 downto 0);
87 
signal HTRANS_M0               : std_logic_vector(1 downto 0);
88 
signal HSIZE_M0                : std_logic_vector(2 downto 0);
89 
signal HWRITE_M0               : std_logic;
90 
signal HMASTLOCK_M0            : std_logic;
91 
signal HADDR_M0                : std_logic_vector(31 downto 0);
92 
signal HWDATA_M0               : std_logic_vector(31 downto 0);
93 
signal HBURST_M0               : std_logic_vector(2 downto 0);
94 
signal HPROT_M0                : std_logic_vector(3 downto 0);
95 
 
96 
signal HREADY_M1               : std_logic;
97 
signal HRESP_M1                : std_logic_vector(1 downto 0);
98 
signal HRDATA_M1               : std_logic_vector(31 downto 0);
99 
signal HTRANS_M1               : std_logic_vector(1 downto 0);
100 
signal HSIZE_M1                : std_logic_vector(2 downto 0);
101 
signal HWRITE_M1               : std_logic;
102 
signal HMASTLOCK_M1            : std_logic;
103 
signal HADDR_M1                : std_logic_vector(31 downto 0);
104 
signal HWDATA_M1               : std_logic_vector(31 downto 0);
105 
signal HBURST_M1               : std_logic_vector(2 downto 0);
106 
signal HPROT_M1                : std_logic_vector(3 downto 0);
107 
 
108 
signal HREADY_M2               : std_logic;
109 
signal HRESP_M2                : std_logic_vector(1 downto 0);
110 
signal HRDATA_M2               : std_logic_vector(31 downto 0);
111 
signal HTRANS_M2               : std_logic_vector(1 downto 0);
112 
signal HSIZE_M2                : std_logic_vector(2 downto 0);
113 
signal HWRITE_M2               : std_logic;
114 
signal HMASTLOCK_M2            : std_logic;
115 
signal HADDR_M2                : std_logic_vector(31 downto 0);
116 
signal HWDATA_M2               : std_logic_vector(31 downto 0);
117 
signal HBURST_M2               : std_logic_vector(2 downto 0);
118 
signal HPROT_M2                : std_logic_vector(3 downto 0);
119 
 
120 
signal HREADY_M3               : std_logic;
121 
signal HRESP_M3                : std_logic_vector(1 downto 0);
122 
signal HRDATA_M3               : std_logic_vector(31 downto 0);
123 
signal HTRANS_M3               : std_logic_vector(1 downto 0);
124 
signal HSIZE_M3                : std_logic_vector(2 downto 0);
125 
signal HWRITE_M3               : std_logic;
126 
signal HMASTLOCK_M3            : std_logic;
127 
signal HADDR_M3                : std_logic_vector(31 downto 0);
128 
signal HWDATA_M3               : std_logic_vector(31 downto 0);
129 
signal HBURST_M3               : std_logic_vector(2 downto 0);
130 
signal HPROT_M3                : std_logic_vector(3 downto 0);
131 
 
132 
signal HWRITE_S0               : std_logic;
133 
signal HSIZE_S0                : std_logic_vector(2 downto 0);
134 
signal HTRANS_S0               : std_logic_vector(1 downto 0);
135 
signal HWDATA_S0               : std_logic_vector(31 downto 0);
136 
signal HREADYIN_S0             : std_logic;
137 
signal HSEL_S0                 : std_logic;
138 
signal HADDR_S0                : std_logic_vector(31 downto 0);
139 
signal HRDATA_S0               : std_logic_vector(31 downto 0);
140 
signal HRESP_S0                : std_logic_vector(1 downto 0);
141 
signal HREADY_S0,HMASTLOCK_S0  : std_logic;
142 
signal HBURST_S0               : std_logic_vector(2 downto 0);
143 
signal HPROT_S0                : std_logic_vector(3 downto 0);
144 
 
145 
signal HWRITE_S1               : std_logic;
146 
signal HSIZE_S1                : std_logic_vector(2 downto 0);
147 
signal HTRANS_S1               : std_logic_vector(1 downto 0);
148 
signal HWDATA_S1               : std_logic_vector(31 downto 0);
149 
signal HREADYIN_S1             : std_logic;
150 
signal HSEL_S1                 : std_logic;
151 
signal HADDR_S1                : std_logic_vector(31 downto 0);
152 
signal HRDATA_S1               : std_logic_vector(31 downto 0);
153 
signal HRESP_S1                : std_logic_vector(1 downto 0);
154 
signal HREADY_S1,HMASTLOCK_S1  : std_logic;
155 
signal HBURST_S1               : std_logic_vector(2 downto 0);
156 
signal HPROT_S1                : std_logic_vector(3 downto 0);
157 
 
158 
signal HWRITE_S2               : std_logic;
159 
signal HSIZE_S2                : std_logic_vector(2 downto 0);
160 
signal HTRANS_S2               : std_logic_vector(1 downto 0);
161 
signal HWDATA_S2               : std_logic_vector(31 downto 0);
162 
signal HREADYIN_S2             : std_logic;
163 
signal HSEL_S2                 : std_logic;
164 
signal HADDR_S2                : std_logic_vector(31 downto 0);
165 
signal HRDATA_S2               : std_logic_vector(31 downto 0);
166 
signal HRESP_S2                : std_logic_vector(1 downto 0);
167 
signal HREADY_S2,HMASTLOCK_S2  : std_logic;
168 
signal HBURST_S2               : std_logic_vector(2 downto 0);
169 
signal HPROT_S2                : std_logic_vector(3 downto 0);
170 
 
171 
signal HWRITE_S3               : std_logic;
172 
signal HSIZE_S3                : std_logic_vector(2 downto 0);
173 
signal HTRANS_S3               : std_logic_vector(1 downto 0);
174 
signal HWDATA_S3               : std_logic_vector(31 downto 0);
175 
signal HREADYIN_S3             : std_logic;
176 
signal HSEL_S3                 : std_logic;
177 
signal HADDR_S3                : std_logic_vector(31 downto 0);
178 
signal HRDATA_S3               : std_logic_vector(31 downto 0);
179 
signal HRESP_S3                : std_logic_vector(1 downto 0);
180 
signal HREADY_S3,HMASTLOCK_S3  : std_logic;
181 
signal HBURST_S3               : std_logic_vector(2 downto 0);
182 
signal HPROT_S3                : std_logic_vector(3 downto 0);
183 
 
184 
signal HWRITE_S4               : std_logic;
185 
signal HSIZE_S4                : std_logic_vector(2 downto 0);
186 
signal HTRANS_S4               : std_logic_vector(1 downto 0);
187 
signal HWDATA_S4               : std_logic_vector(31 downto 0);
188 
signal HREADYIN_S4             : std_logic;
189 
signal HSEL_S4                 : std_logic;
190 
signal HADDR_S4                : std_logic_vector(31 downto 0);
191 
signal HRDATA_S4               : std_logic_vector(31 downto 0);
192 
signal HRESP_S4                : std_logic_vector(1 downto 0);
193 
signal HREADY_S4,HMASTLOCK_S4  : std_logic;
194 
signal HBURST_S4               : std_logic_vector(2 downto 0);
195 
signal HPROT_S4                : std_logic_vector(3 downto 0);
196 
 
197 
signal HWRITE_S5               : std_logic;
198 
signal HSIZE_S5                : std_logic_vector(2 downto 0);
199 
signal HTRANS_S5               : std_logic_vector(1 downto 0);
200 
signal HWDATA_S5               : std_logic_vector(31 downto 0);
201 
signal HREADYIN_S5             : std_logic;
202 
signal HSEL_S5                 : std_logic;
203 
signal HADDR_S5                : std_logic_vector(31 downto 0);
204 
signal HRDATA_S5               : std_logic_vector(31 downto 0);
205 
signal HRESP_S5                : std_logic_vector(1 downto 0);
206 
signal HREADY_S5,HMASTLOCK_S5  : std_logic;
207 
signal HBURST_S5               : std_logic_vector(2 downto 0);
208 
signal HPROT_S5                : std_logic_vector(3 downto 0);
209 
 
210 
signal HWRITE_S6               : std_logic;
211 
signal HSIZE_S6                : std_logic_vector(2 downto 0);
212 
signal HTRANS_S6               : std_logic_vector(1 downto 0);
213 
signal HWDATA_S6               : std_logic_vector(31 downto 0);
214 
signal HREADYIN_S6             : std_logic;
215 
signal HSEL_S6                 : std_logic;
216 
signal HADDR_S6                : std_logic_vector(31 downto 0);
217 
signal HRDATA_S6               : std_logic_vector(31 downto 0);
218 
signal HRESP_S6                : std_logic_vector(1 downto 0);
219 
signal HREADY_S6,HMASTLOCK_S6  : std_logic;
220 
signal HBURST_S6               : std_logic_vector(2 downto 0);
221 
signal HPROT_S6                : std_logic_vector(3 downto 0);
222 
 
223 
signal HWRITE_S7               : std_logic;
224 
signal HSIZE_S7                : std_logic_vector(2 downto 0);
225 
signal HTRANS_S7               : std_logic_vector(1 downto 0);
226 
signal HWDATA_S7               : std_logic_vector(31 downto 0);
227 
signal HREADYIN_S7             : std_logic;
228 
signal HSEL_S7                 : std_logic;
229 
signal HADDR_S7                : std_logic_vector(31 downto 0);
230 
signal HRDATA_S7               : std_logic_vector(31 downto 0);
231 
signal HRESP_S7                : std_logic_vector(1 downto 0);
232 
signal HREADY_S7,HMASTLOCK_S7  : std_logic;
233 
signal HBURST_S7               : std_logic_vector(2 downto 0);
234 
signal HPROT_S7                : std_logic_vector(3 downto 0);
235 
 
236 
signal HWRITE_S8               : std_logic;
237 
signal HSIZE_S8                : std_logic_vector(2 downto 0);
238 
signal HTRANS_S8               : std_logic_vector(1 downto 0);
239 
signal HWDATA_S8               : std_logic_vector(31 downto 0);
240 
signal HREADYIN_S8             : std_logic;
241 
signal HSEL_S8                 : std_logic;
242 
signal HADDR_S8                : std_logic_vector(31 downto 0);
243 
signal HRDATA_S8               : std_logic_vector(31 downto 0);
244 
signal HRESP_S8                : std_logic_vector(1 downto 0);
245 
signal HREADY_S8,HMASTLOCK_S8  : std_logic;
246 
signal HBURST_S8               : std_logic_vector(2 downto 0);
247 
signal HPROT_S8                : std_logic_vector(3 downto 0);
248 
 
249 
signal HWRITE_S9               : std_logic;
250 
signal HSIZE_S9                : std_logic_vector(2 downto 0);
251 
signal HTRANS_S9               : std_logic_vector(1 downto 0);
252 
signal HWDATA_S9               : std_logic_vector(31 downto 0);
253 
signal HREADYIN_S9             : std_logic;
254 
signal HSEL_S9                 : std_logic;
255 
signal HADDR_S9                : std_logic_vector(31 downto 0);
256 
signal HRDATA_S9               : std_logic_vector(31 downto 0);
257 
signal HRESP_S9                : std_logic_vector(1 downto 0);
258 
signal HREADY_S9,HMASTLOCK_S9  : std_logic;
259 
signal HBURST_S9               : std_logic_vector(2 downto 0);
260 
signal HPROT_S9                : std_logic_vector(3 downto 0);
261 
 
262 
signal HWRITE_S10              : std_logic;
263 
signal HSIZE_S10               : std_logic_vector(2 downto 0);
264 
signal HTRANS_S10              : std_logic_vector(1 downto 0);
265 
signal HWDATA_S10              : std_logic_vector(31 downto 0);
266 
signal HREADYIN_S10            : std_logic;
267 
signal HSEL_S10                : std_logic;
268 
signal HADDR_S10               : std_logic_vector(31 downto 0);
269 
signal HRDATA_S10              : std_logic_vector(31 downto 0);
270 
signal HRESP_S10               : std_logic_vector(1 downto 0);
271 
signal HREADY_S10,HMASTLOCK_S10: std_logic;
272 
signal HBURST_S10              : std_logic_vector(2 downto 0);
273 
signal HPROT_S10               : std_logic_vector(3 downto 0);
274 
 
275 
signal HWRITE_S11              : std_logic;
276 
signal HSIZE_S11               : std_logic_vector(2 downto 0);
277 
signal HTRANS_S11              : std_logic_vector(1 downto 0);
278 
signal HWDATA_S11              : std_logic_vector(31 downto 0);
279 
signal HREADYIN_S11            : std_logic;
280 
signal HSEL_S11                : std_logic;
281 
signal HADDR_S11               : std_logic_vector(31 downto 0);
282 
signal HRDATA_S11              : std_logic_vector(31 downto 0);
283 
signal HRESP_S11               : std_logic_vector(1 downto 0);
284 
signal HREADY_S11,HMASTLOCK_S11: std_logic;
285 
signal HBURST_S11              : std_logic_vector(2 downto 0);
286 
signal HPROT_S11               : std_logic_vector(3 downto 0);
287 
 
288 
signal HWRITE_S12              : std_logic;
289 
signal HSIZE_S12               : std_logic_vector(2 downto 0);
290 
signal HTRANS_S12              : std_logic_vector(1 downto 0);
291 
signal HWDATA_S12              : std_logic_vector(31 downto 0);
292 
signal HREADYIN_S12            : std_logic;
293 
signal HSEL_S12                : std_logic;
294 
signal HADDR_S12               : std_logic_vector(31 downto 0);
295 
signal HRDATA_S12              : std_logic_vector(31 downto 0);
296 
signal HRESP_S12               : std_logic_vector(1 downto 0);
297 
signal HREADY_S12,HMASTLOCK_S12: std_logic;
298 
signal HBURST_S12              : std_logic_vector(2 downto 0);
299 
signal HPROT_S12               : std_logic_vector(3 downto 0);
300 
 
301 
signal HWRITE_S13              : std_logic;
302 
signal HSIZE_S13               : std_logic_vector(2 downto 0);
303 
signal HTRANS_S13              : std_logic_vector(1 downto 0);
304 
signal HWDATA_S13              : std_logic_vector(31 downto 0);
305 
signal HREADYIN_S13            : std_logic;
306 
signal HSEL_S13                : std_logic;
307 
signal HADDR_S13               : std_logic_vector(31 downto 0);
308 
signal HRDATA_S13              : std_logic_vector(31 downto 0);
309 
signal HRESP_S13               : std_logic_vector(1 downto 0);
310 
signal HREADY_S13,HMASTLOCK_S13: std_logic;
311 
signal HBURST_S13              : std_logic_vector(2 downto 0);
312 
signal HPROT_S13               : std_logic_vector(3 downto 0);
313 
 
314 
signal HWRITE_S14              : std_logic;
315 
signal HSIZE_S14               : std_logic_vector(2 downto 0);
316 
signal HTRANS_S14              : std_logic_vector(1 downto 0);
317 
signal HWDATA_S14              : std_logic_vector(31 downto 0);
318 
signal HREADYIN_S14            : std_logic;
319 
signal HSEL_S14                : std_logic;
320 
signal HADDR_S14               : std_logic_vector(31 downto 0);
321 
signal HRDATA_S14              : std_logic_vector(31 downto 0);
322 
signal HRESP_S14               : std_logic_vector(1 downto 0);
323 
signal HREADY_S14,HMASTLOCK_S14: std_logic;
324 
signal HBURST_S14              : std_logic_vector(2 downto 0);
325 
signal HPROT_S14               : std_logic_vector(3 downto 0);
326 
 
327 
signal HWRITE_S15              : std_logic;
328 
signal HSIZE_S15               : std_logic_vector(2 downto 0);
329 
signal HTRANS_S15              : std_logic_vector(1 downto 0);
330 
signal HWDATA_S15              : std_logic_vector(31 downto 0);
331 
signal HREADYIN_S15            : std_logic;
332 
signal HSEL_S15                : std_logic;
333 
signal HADDR_S15               : std_logic_vector(31 downto 0);
334 
signal HRDATA_S15              : std_logic_vector(31 downto 0);
335 
signal HRESP_S15               : std_logic_vector(1 downto 0);
336 
signal HREADY_S15,HMASTLOCK_S15: std_logic;
337 
signal HBURST_S15              : std_logic_vector(2 downto 0);
338 
signal HPROT_S15               : std_logic_vector(3 downto 0);
339 
 
340 
signal HWRITE_S16              : std_logic;
341 
signal HSIZE_S16               : std_logic_vector(2 downto 0);
342 
signal HTRANS_S16              : std_logic_vector(1 downto 0);
343 
signal HWDATA_S16              : std_logic_vector(31 downto 0);
344 
signal HREADYIN_S16            : std_logic;
345 
signal HSEL_S16                : std_logic;
346 
signal HADDR_S16               : std_logic_vector(31 downto 0);
347 
signal HRDATA_S16              : std_logic_vector(31 downto 0);
348 
signal HRESP_S16               : std_logic_vector(1 downto 0);
349 
signal HREADY_S16,HMASTLOCK_S16: std_logic;
350 
signal HBURST_S16              : std_logic_vector(2 downto 0);
351 
signal HPROT_S16               : std_logic_vector(3 downto 0);
352 
 
353 
signal FINISHED_master0        : std_logic;
354 
signal FINISHED_master1        : std_logic;
355 
signal FINISHED_master2        : std_logic;
356 
signal FINISHED_master3        : std_logic;
357 
 
358 
signal s0_write                : std_logic;
359 
signal s1_write                : std_logic;
360 
signal s2_write                : std_logic;
361 
signal s3_write                : std_logic;
362 
signal s4_write                : std_logic;
363 
signal s5_write                : std_logic;
364 
signal s6_write                : std_logic;
365 
signal s7_write                : std_logic;
366 
signal s8_write                : std_logic;
367 
signal s9_write                : std_logic;
368 
signal s10_write               : std_logic;
369 
signal s11_write               : std_logic;
370 
signal s12_write               : std_logic;
371 
signal s13_write               : std_logic;
372 
signal s14_write               : std_logic;
373 
signal s15_write               : std_logic;
374 
signal s16_write               : std_logic;
375 
 
376 
-- misc. signals
377 
signal GND256:                          std_logic_vector(255 downto 0)   :=(others=>'0');
378 
signal GND15:                           std_logic_vector(14 downto 0)    :=(others=>'0');
379 
signal GND12:                           std_logic_vector(11 downto 0)    :=(others=>'0');
380 
 
381 
begin
382 
 
383 
   -- Main simulation
384 
   process
385 
   begin
386 
      SYSRSTN <= '0';
387 
 
388 
      -- Release system reset
389 
      wait for (SYSCLK_PERIOD * 4)*1 ns;
390 
      SYSRSTN <= '1';
391 
 
392 
      -- wait until all BFM's are finished
393 
      while (
394 
        not(
395 
            (
396 
                    (FINISHED_master0 = '1')
397 
                and (FINISHED_master1 = '1')
398 
                and (FINISHED_master2 = '1')
399 
                and (FINISHED_master3 = '1')
400 
            )
401 
           )
402 
      ) loop
403 
              wait on SYSCLK;
404 
          wait for (TPD)*1 ns;
405 
      end loop;
406 
      wait for 1 ns;
407 
      stopsim <= 1;
408 
      wait;
409 
   end process;
410 
 
411 
   -- tie-off unused inputs to DUT
412 
   HBURST_M0      <= "000";
413 
   HBURST_M1      <= "000";
414 
   HBURST_M2      <= "000";
415 
   HBURST_M3      <= "000";
416 
   HPROT_M0       <= "0000";
417 
   HPROT_M1       <= "0000";
418 
   HPROT_M2       <= "0000";
419 
   HPROT_M3       <= "0000";
420 
   HRESP_S0(1)    <= '0';
421 
   HRESP_S1(1)    <= '0';
422 
   HRESP_S2(1)    <= '0';
423 
   HRESP_S3(1)    <= '0';
424 
   HRESP_S4(1)    <= '0';
425 
   HRESP_S5(1)    <= '0';
426 
   HRESP_S6(1)    <= '0';
427 
   HRESP_S7(1)    <= '0';
428 
   HRESP_S8(1)    <= '0';
429 
   HRESP_S9(1)    <= '0';
430 
   HRESP_S10(1)   <= '0';
431 
   HRESP_S11(1)   <= '0';
432 
   HRESP_S12(1)   <= '0';
433 
   HRESP_S13(1)   <= '0';
434 
   HRESP_S14(1)   <= '0';
435 
   HRESP_S15(1)   <= '0';
436 
   HRESP_S16(1)   <= '0';
437 
 
438 
   -- System clock
439 
   process
440 
   begin
441 
     SYSCLK <= '0';
442 
     wait for (SYSCLK_PERIOD / 2)*1 ns;
443 
     SYSCLK <= '1';
444 
     wait for (SYSCLK_PERIOD / 2)*1 ns;
445 
     if (stopsim = 1) then
446 
      wait;
447 
    end if;
448 
   end process;
449 
 
450 
-- Instantiate module to test
451 
u_coreahblite : top_CoreAHBLite_0_CoreAHBLite
452 
generic map (
453 
        FAMILY => FAMILY,
454 
        MEMSPACE => MEMSPACE,
455 
    HADDR_SHG_CFG => HADDR_SHG_CFG,
456 
        SC_0  => SC_0 ,
457 
        SC_1  => SC_1 ,
458 
        SC_2  => SC_2 ,
459 
        SC_3  => SC_3 ,
460 
        SC_4  => SC_4 ,
461 
        SC_5  => SC_5 ,
462 
        SC_6  => SC_6 ,
463 
        SC_7  => SC_7 ,
464 
        SC_8  => SC_8 ,
465 
        SC_9  => SC_9 ,
466 
        SC_10 => SC_10,
467 
        SC_11 => SC_11,
468 
        SC_12 => SC_12,
469 
        SC_13 => SC_13,
470 
        SC_14 => SC_14,
471 
        SC_15 => SC_15,
472 
        M0_AHBSLOT0ENABLE  => M0_AHBSLOT0ENABLE,
473 
        M0_AHBSLOT1ENABLE  => M0_AHBSLOT1ENABLE,
474 
        M0_AHBSLOT2ENABLE  => M0_AHBSLOT2ENABLE,
475 
        M0_AHBSLOT3ENABLE  => M0_AHBSLOT3ENABLE,
476 
        M0_AHBSLOT4ENABLE  => M0_AHBSLOT4ENABLE,
477 
        M0_AHBSLOT5ENABLE  => M0_AHBSLOT5ENABLE,
478 
        M0_AHBSLOT6ENABLE  => M0_AHBSLOT6ENABLE,
479 
        M0_AHBSLOT7ENABLE  => M0_AHBSLOT7ENABLE,
480 
        M0_AHBSLOT8ENABLE  => M0_AHBSLOT8ENABLE,
481 
        M0_AHBSLOT9ENABLE  => M0_AHBSLOT9ENABLE,
482 
        M0_AHBSLOT10ENABLE => M0_AHBSLOT10ENABLE,
483 
        M0_AHBSLOT11ENABLE => M0_AHBSLOT11ENABLE,
484 
        M0_AHBSLOT12ENABLE => M0_AHBSLOT12ENABLE,
485 
        M0_AHBSLOT13ENABLE => M0_AHBSLOT13ENABLE,
486 
        M0_AHBSLOT14ENABLE => M0_AHBSLOT14ENABLE,
487 
        M0_AHBSLOT15ENABLE => M0_AHBSLOT15ENABLE,
488 
        M0_AHBSLOT16ENABLE => M0_AHBSLOT16ENABLE,
489 
        M1_AHBSLOT0ENABLE  => M1_AHBSLOT0ENABLE,
490 
        M1_AHBSLOT1ENABLE  => M1_AHBSLOT1ENABLE,
491 
        M1_AHBSLOT2ENABLE  => M1_AHBSLOT2ENABLE,
492 
        M1_AHBSLOT3ENABLE  => M1_AHBSLOT3ENABLE,
493 
        M1_AHBSLOT4ENABLE  => M1_AHBSLOT4ENABLE,
494 
        M1_AHBSLOT5ENABLE  => M1_AHBSLOT5ENABLE,
495 
        M1_AHBSLOT6ENABLE  => M1_AHBSLOT6ENABLE,
496 
        M1_AHBSLOT7ENABLE  => M1_AHBSLOT7ENABLE,
497 
        M1_AHBSLOT8ENABLE  => M1_AHBSLOT8ENABLE,
498 
        M1_AHBSLOT9ENABLE  => M1_AHBSLOT9ENABLE,
499 
        M1_AHBSLOT10ENABLE => M1_AHBSLOT10ENABLE,
500 
        M1_AHBSLOT11ENABLE => M1_AHBSLOT11ENABLE,
501 
        M1_AHBSLOT12ENABLE => M1_AHBSLOT12ENABLE,
502 
        M1_AHBSLOT13ENABLE => M1_AHBSLOT13ENABLE,
503 
        M1_AHBSLOT14ENABLE => M1_AHBSLOT14ENABLE,
504 
        M1_AHBSLOT15ENABLE => M1_AHBSLOT15ENABLE,
505 
        M1_AHBSLOT16ENABLE => M1_AHBSLOT16ENABLE,
506 
        M2_AHBSLOT0ENABLE  => M2_AHBSLOT0ENABLE,
507 
        M2_AHBSLOT1ENABLE  => M2_AHBSLOT1ENABLE,
508 
        M2_AHBSLOT2ENABLE  => M2_AHBSLOT2ENABLE,
509 
        M2_AHBSLOT3ENABLE  => M2_AHBSLOT3ENABLE,
510 
        M2_AHBSLOT4ENABLE  => M2_AHBSLOT4ENABLE,
511 
        M2_AHBSLOT5ENABLE  => M2_AHBSLOT5ENABLE,
512 
        M2_AHBSLOT6ENABLE  => M2_AHBSLOT6ENABLE,
513 
        M2_AHBSLOT7ENABLE  => M2_AHBSLOT7ENABLE,
514 
        M2_AHBSLOT8ENABLE  => M2_AHBSLOT8ENABLE,
515 
        M2_AHBSLOT9ENABLE  => M2_AHBSLOT9ENABLE,
516 
        M2_AHBSLOT10ENABLE => M2_AHBSLOT10ENABLE,
517 
        M2_AHBSLOT11ENABLE => M2_AHBSLOT11ENABLE,
518 
        M2_AHBSLOT12ENABLE => M2_AHBSLOT12ENABLE,
519 
        M2_AHBSLOT13ENABLE => M2_AHBSLOT13ENABLE,
520 
        M2_AHBSLOT14ENABLE => M2_AHBSLOT14ENABLE,
521 
        M2_AHBSLOT15ENABLE => M2_AHBSLOT15ENABLE,
522 
        M2_AHBSLOT16ENABLE => M2_AHBSLOT16ENABLE,
523 
        M3_AHBSLOT0ENABLE  => M3_AHBSLOT0ENABLE,
524 
        M3_AHBSLOT1ENABLE  => M3_AHBSLOT1ENABLE,
525 
        M3_AHBSLOT2ENABLE  => M3_AHBSLOT2ENABLE,
526 
        M3_AHBSLOT3ENABLE  => M3_AHBSLOT3ENABLE,
527 
        M3_AHBSLOT4ENABLE  => M3_AHBSLOT4ENABLE,
528 
        M3_AHBSLOT5ENABLE  => M3_AHBSLOT5ENABLE,
529 
        M3_AHBSLOT6ENABLE  => M3_AHBSLOT6ENABLE,
530 
        M3_AHBSLOT7ENABLE  => M3_AHBSLOT7ENABLE,
531 
        M3_AHBSLOT8ENABLE  => M3_AHBSLOT8ENABLE,
532 
        M3_AHBSLOT9ENABLE  => M3_AHBSLOT9ENABLE,
533 
        M3_AHBSLOT10ENABLE => M3_AHBSLOT10ENABLE,
534 
        M3_AHBSLOT11ENABLE => M3_AHBSLOT11ENABLE,
535 
        M3_AHBSLOT12ENABLE => M3_AHBSLOT12ENABLE,
536 
        M3_AHBSLOT13ENABLE => M3_AHBSLOT13ENABLE,
537 
        M3_AHBSLOT14ENABLE => M3_AHBSLOT14ENABLE,
538 
        M3_AHBSLOT15ENABLE => M3_AHBSLOT15ENABLE,
539 
        M3_AHBSLOT16ENABLE => M3_AHBSLOT16ENABLE
540 
)
541 
port map (
542 
        -- ResetController interface
543 
        -- Inputs
544 
        HCLK => HCLK,
545 
        HRESETN => HRESETN,
546 
 
547 
        -- controls master 0 memory aliasing (swaps slots 0 and 1)
548 
        REMAP_M0 => REMAP_M0,
549 
 
550 
        -- Mirrored master AHB-Lite interface to Master 0
551 
        -- Inputs
552 
        HADDR_M0 => HADDR_M0,
553 
        HMASTLOCK_M0 => HMASTLOCK_M0,
554 
        HSIZE_M0 => HSIZE_M0,
555 
        HTRANS_M0 => HTRANS_M0,
556 
        HWRITE_M0 => HWRITE_M0,
557 
        HWDATA_M0 => HWDATA_M0,
558 
        HBURST_M0 => HBURST_M0,
559 
        HPROT_M0 => HPROT_M0,
560 
        -- Outputs
561 
        HRESP_M0 => HRESP_M0,
562 
        HRDATA_M0 => HRDATA_M0,
563 
        HREADY_M0 => HREADY_M0,
564 
 
565 
        -- Mirrored master AHB-Lite interface to Master 1
566 
        -- Inputs
567 
        HADDR_M1 => HADDR_M1,
568 
        HMASTLOCK_M1 => HMASTLOCK_M1,
569 
        HSIZE_M1 => HSIZE_M1,
570 
        HTRANS_M1 => HTRANS_M1,
571 
        HWRITE_M1 => HWRITE_M1,
572 
        HWDATA_M1 => HWDATA_M1,
573 
        HBURST_M1 => HBURST_M1,
574 
        HPROT_M1 => HPROT_M1,
575 
        -- Outputs
576 
        HRESP_M1 => HRESP_M1,
577 
        HRDATA_M1 => HRDATA_M1,
578 
        HREADY_M1 => HREADY_M1,
579 
 
580 
        -- Mirrored master AHB-Lite interface to Master 2
581 
        -- Inputs
582 
        HADDR_M2 => HADDR_M2,
583 
        HMASTLOCK_M2 => HMASTLOCK_M2,
584 
        HSIZE_M2 => HSIZE_M2,
585 
        HTRANS_M2 => HTRANS_M2,
586 
        HWRITE_M2 => HWRITE_M2,
587 
        HWDATA_M2 => HWDATA_M2,
588 
        HBURST_M2 => HBURST_M2,
589 
        HPROT_M2 => HPROT_M2,
590 
        -- Outputs
591 
        HRESP_M2 => HRESP_M2,
592 
        HRDATA_M2 => HRDATA_M2,
593 
        HREADY_M2 => HREADY_M2,
594 
 
595 
        -- Mirrored master AHB-Lite interface to Master 3
596 
        -- Inputs
597 
        HADDR_M3 => HADDR_M3,
598 
        HMASTLOCK_M3 => HMASTLOCK_M3,
599 
        HSIZE_M3 => HSIZE_M3,
600 
        HTRANS_M3 => HTRANS_M3,
601 
        HWRITE_M3 => HWRITE_M3,
602 
        HWDATA_M3 => HWDATA_M3,
603 
        HBURST_M3 => HBURST_M3,
604 
        HPROT_M3 => HPROT_M3,
605 
        -- Outputs
606 
        HRESP_M3 => HRESP_M3,
607 
        HRDATA_M3 => HRDATA_M3,
608 
        HREADY_M3 => HREADY_M3,
609 
 
610 
        -- Mirrored slave AHB-Lite interface to Slave 0
611 
        -- Inputs
612 
        HRDATA_S0 => HRDATA_S0,
613 
        HREADYOUT_S0 => HREADY_S0,
614 
        HRESP_S0 => HRESP_S0,
615 
        -- Outputs
616 
        HSEL_S0 => HSEL_S0,
617 
        HADDR_S0 => HADDR_S0,
618 
        HSIZE_S0 => HSIZE_S0,
619 
        HTRANS_S0 => HTRANS_S0,
620 
        HWRITE_S0 => HWRITE_S0,
621 
        HWDATA_S0 => HWDATA_S0,
622 
        HREADY_S0 => HREADYIN_S0,
623 
        HMASTLOCK_S0 => HMASTLOCK_S0,
624 
        HBURST_S0 => HBURST_S0,
625 
        HPROT_S0 => HPROT_S0,
626 
 
627 
        -- Mirrored slave AHB-Lite interface to Slave 1
628 
        -- Inputs
629 
        HRDATA_S1 => HRDATA_S1,
630 
        HREADYOUT_S1 => HREADY_S1,
631 
        HRESP_S1 => HRESP_S1,
632 
        -- Outputs
633 
        HSEL_S1 => HSEL_S1,
634 
        HADDR_S1 => HADDR_S1,
635 
        HSIZE_S1 => HSIZE_S1,
636 
        HTRANS_S1 => HTRANS_S1,
637 
        HWRITE_S1 => HWRITE_S1,
638 
        HWDATA_S1 => HWDATA_S1,
639 
        HREADY_S1 => HREADYIN_S1,
640 
        HMASTLOCK_S1 => HMASTLOCK_S1,
641 
        HBURST_S1 => HBURST_S1,
642 
        HPROT_S1 => HPROT_S1,
643 
 
644 
        -- Mirrored slave AHB-Lite interface to Slave 2
645 
        -- Inputs
646 
        HRDATA_S2 => HRDATA_S2,
647 
        HREADYOUT_S2 => HREADY_S2,
648 
        HRESP_S2 => HRESP_S2,
649 
        -- Outputs
650 
        HSEL_S2 => HSEL_S2,
651 
        HADDR_S2 => HADDR_S2,
652 
        HSIZE_S2 => HSIZE_S2,
653 
        HTRANS_S2 => HTRANS_S2,
654 
        HWRITE_S2 => HWRITE_S2,
655 
        HWDATA_S2 => HWDATA_S2,
656 
        HREADY_S2 => HREADYIN_S2,
657 
        HMASTLOCK_S2 => HMASTLOCK_S2,
658 
        HBURST_S2 => HBURST_S2,
659 
        HPROT_S2 => HPROT_S2,
660 
 
661 
        -- Mirrored slave AHB-Lite interface to Slave 3
662 
        -- Inputs
663 
        HRDATA_S3 => HRDATA_S3,
664 
        HREADYOUT_S3 => HREADY_S3,
665 
        HRESP_S3 => HRESP_S3,
666 
        -- Output
667 
        HSEL_S3 => HSEL_S3,
668 
        HADDR_S3 => HADDR_S3,
669 
        HSIZE_S3 => HSIZE_S3,
670 
        HTRANS_S3 => HTRANS_S3,
671 
        HWRITE_S3 => HWRITE_S3,
672 
        HWDATA_S3 => HWDATA_S3,
673 
        HREADY_S3 => HREADYIN_S3,
674 
        HMASTLOCK_S3 => HMASTLOCK_S3,
675 
        HBURST_S3 => HBURST_S3,
676 
        HPROT_S3 => HPROT_S3,
677 
 
678 
        -- Mirrored slave AHB-Lite interface to Slave 4
679 
        -- Inputs
680 
        HRDATA_S4 => HRDATA_S4,
681 
        HREADYOUT_S4 => HREADY_S4,
682 
        HRESP_S4 => HRESP_S4,
683 
        -- Output
684 
        HSEL_S4 => HSEL_S4,
685 
        HADDR_S4 => HADDR_S4,
686 
        HSIZE_S4 => HSIZE_S4,
687 
        HTRANS_S4 => HTRANS_S4,
688 
        HWRITE_S4 => HWRITE_S4,
689 
        HWDATA_S4 => HWDATA_S4,
690 
        HREADY_S4 => HREADYIN_S4,
691 
        HMASTLOCK_S4 => HMASTLOCK_S4,
692 
        HBURST_S4 => HBURST_S4,
693 
        HPROT_S4 => HPROT_S4,
694 
 
695 
        -- Mirrored slave AHB-Lite interface to Slave 5
696 
        -- Inputs
697 
        HRDATA_S5 => HRDATA_S5,
698 
        HREADYOUT_S5 => HREADY_S5,
699 
        HRESP_S5 => HRESP_S5,
700 
        -- Output
701 
        HSEL_S5 => HSEL_S5,
702 
        HADDR_S5 => HADDR_S5,
703 
        HSIZE_S5 => HSIZE_S5,
704 
        HTRANS_S5 => HTRANS_S5,
705 
        HWRITE_S5 => HWRITE_S5,
706 
        HWDATA_S5 => HWDATA_S5,
707 
        HREADY_S5 => HREADYIN_S5,
708 
        HMASTLOCK_S5 => HMASTLOCK_S5,
709 
        HBURST_S5 => HBURST_S5,
710 
        HPROT_S5 => HPROT_S5,
711 
 
712 
        -- Mirrored slave AHB-Lite interface to Slave 6
713 
        -- Inputs
714 
        HRDATA_S6 => HRDATA_S6,
715 
        HREADYOUT_S6 => HREADY_S6,
716 
        HRESP_S6 => HRESP_S6,
717 
        -- Output
718 
        HSEL_S6 => HSEL_S6,
719 
        HADDR_S6 => HADDR_S6,
720 
        HSIZE_S6 => HSIZE_S6,
721 
        HTRANS_S6 => HTRANS_S6,
722 
        HWRITE_S6 => HWRITE_S6,
723 
        HWDATA_S6 => HWDATA_S6,
724 
        HREADY_S6 => HREADYIN_S6,
725 
        HMASTLOCK_S6 => HMASTLOCK_S6,
726 
        HBURST_S6 => HBURST_S6,
727 
        HPROT_S6 => HPROT_S6,
728 
 
729 
        -- Mirrored slave AHB-Lite interface to Slave 7
730 
        -- Inputs
731 
        HRDATA_S7 => HRDATA_S7,
732 
        HREADYOUT_S7 => HREADY_S7,
733 
        HRESP_S7 => HRESP_S7,
734 
        -- Output
735 
        HSEL_S7 => HSEL_S7,
736 
        HADDR_S7 => HADDR_S7,
737 
        HSIZE_S7 => HSIZE_S7,
738 
        HTRANS_S7 => HTRANS_S7,
739 
        HWRITE_S7 => HWRITE_S7,
740 
        HWDATA_S7 => HWDATA_S7,
741 
        HREADY_S7 => HREADYIN_S7,
742 
        HMASTLOCK_S7 => HMASTLOCK_S7,
743 
        HBURST_S7 => HBURST_S7,
744 
        HPROT_S7 => HPROT_S7,
745 
 
746 
        -- Mirrored slave AHB-Lite interface to Slave 8
747 
        -- Inputs
748 
        HRDATA_S8 => HRDATA_S8,
749 
        HREADYOUT_S8 => HREADY_S8,
750 
        HRESP_S8 => HRESP_S8,
751 
        -- Output
752 
        HSEL_S8 => HSEL_S8,
753 
        HADDR_S8 => HADDR_S8,
754 
        HSIZE_S8 => HSIZE_S8,
755 
        HTRANS_S8 => HTRANS_S8,
756 
        HWRITE_S8 => HWRITE_S8,
757 
        HWDATA_S8 => HWDATA_S8,
758 
        HREADY_S8 => HREADYIN_S8,
759 
        HMASTLOCK_S8 => HMASTLOCK_S8,
760 
        HBURST_S8 => HBURST_S8,
761 
        HPROT_S8 => HPROT_S8,
762 
 
763 
        -- Mirrored slave AHB-Lite interface to Slave 9
764 
        -- Inputs
765 
        HRDATA_S9 => HRDATA_S9,
766 
        HREADYOUT_S9 => HREADY_S9,
767 
        HRESP_S9 => HRESP_S9,
768 
        -- Output
769 
        HSEL_S9 => HSEL_S9,
770 
        HADDR_S9 => HADDR_S9,
771 
        HSIZE_S9 => HSIZE_S9,
772 
        HTRANS_S9 => HTRANS_S9,
773 
        HWRITE_S9 => HWRITE_S9,
774 
        HWDATA_S9 => HWDATA_S9,
775 
        HREADY_S9 => HREADYIN_S9,
776 
        HMASTLOCK_S9 => HMASTLOCK_S9,
777 
        HBURST_S9 => HBURST_S9,
778 
        HPROT_S9 => HPROT_S9,
779 
 
780 
        -- Mirrored slave AHB-Lite interface to Slave 10
781 
        -- Inputs
782 
        HRDATA_S10 => HRDATA_S10,
783 
        HREADYOUT_S10 => HREADY_S10,
784 
        HRESP_S10 => HRESP_S10,
785 
        -- Output
786 
        HSEL_S10 => HSEL_S10,
787 
        HADDR_S10 => HADDR_S10,
788 
        HSIZE_S10 => HSIZE_S10,
789 
        HTRANS_S10 => HTRANS_S10,
790 
        HWRITE_S10 => HWRITE_S10,
791 
        HWDATA_S10 => HWDATA_S10,
792 
        HREADY_S10 => HREADYIN_S10,
793 
        HMASTLOCK_S10 => HMASTLOCK_S10,
794 
        HBURST_S10 => HBURST_S10,
795 
        HPROT_S10 => HPROT_S10,
796 
 
797 
        -- Mirrored slave AHB-Lite interface to Slave 11
798 
        -- Inputs
799 
        HRDATA_S11 => HRDATA_S11,
800 
        HREADYOUT_S11 => HREADY_S11,
801 
        HRESP_S11 => HRESP_S11,
802 
        -- Output
803 
        HSEL_S11 => HSEL_S11,
804 
        HADDR_S11 => HADDR_S11,
805 
        HSIZE_S11 => HSIZE_S11,
806 
        HTRANS_S11 => HTRANS_S11,
807 
        HWRITE_S11 => HWRITE_S11,
808 
        HWDATA_S11 => HWDATA_S11,
809 
        HREADY_S11 => HREADYIN_S11,
810 
        HMASTLOCK_S11 => HMASTLOCK_S11,
811 
        HBURST_S11 => HBURST_S11,
812 
        HPROT_S11 => HPROT_S11,
813 
 
814 
        -- Mirrored slave AHB-Lite interface to Slave 12
815 
        -- Inputs
816 
        HRDATA_S12 => HRDATA_S12,
817 
        HREADYOUT_S12 => HREADY_S12,
818 
        HRESP_S12 => HRESP_S12,
819 
        -- Output
820 
        HSEL_S12 => HSEL_S12,
821 
        HADDR_S12 => HADDR_S12,
822 
        HSIZE_S12 => HSIZE_S12,
823 
        HTRANS_S12 => HTRANS_S12,
824 
        HWRITE_S12 => HWRITE_S12,
825 
        HWDATA_S12 => HWDATA_S12,
826 
        HREADY_S12 => HREADYIN_S12,
827 
        HMASTLOCK_S12 => HMASTLOCK_S12,
828 
        HBURST_S12 => HBURST_S12,
829 
        HPROT_S12 => HPROT_S12,
830 
 
831 
        -- Mirrored slave AHB-Lite interface to Slave 13
832 
        -- Inputs
833 
        HRDATA_S13 => HRDATA_S13,
834 
        HREADYOUT_S13 => HREADY_S13,
835 
        HRESP_S13 => HRESP_S13,
836 
        -- Output
837 
        HSEL_S13 => HSEL_S13,
838 
        HADDR_S13 => HADDR_S13,
839 
        HSIZE_S13 => HSIZE_S13,
840 
        HTRANS_S13 => HTRANS_S13,
841 
        HWRITE_S13 => HWRITE_S13,
842 
        HWDATA_S13 => HWDATA_S13,
843 
        HREADY_S13 => HREADYIN_S13,
844 
        HMASTLOCK_S13 => HMASTLOCK_S13,
845 
        HBURST_S13 => HBURST_S13,
846 
        HPROT_S13 => HPROT_S13,
847 
 
848 
        -- Mirrored slave AHB-Lite interface to Slave 14
849 
        -- Inputs
850 
        HRDATA_S14 => HRDATA_S14,
851 
        HREADYOUT_S14 => HREADY_S14,
852 
        HRESP_S14 => HRESP_S14,
853 
        -- Output
854 
        HSEL_S14 => HSEL_S14,
855 
        HADDR_S14 => HADDR_S14,
856 
        HSIZE_S14 => HSIZE_S14,
857 
        HTRANS_S14 => HTRANS_S14,
858 
        HWRITE_S14 => HWRITE_S14,
859 
        HWDATA_S14 => HWDATA_S14,
860 
        HREADY_S14 => HREADYIN_S14,
861 
        HMASTLOCK_S14 => HMASTLOCK_S14,
862 
        HBURST_S14 => HBURST_S14,
863 
        HPROT_S14 => HPROT_S14,
864 
 
865 
        -- Mirrored slave AHB-Lite interface to Slave 15
866 
        -- Inputs
867 
        HRDATA_S15 => HRDATA_S15,
868 
        HREADYOUT_S15 => HREADY_S15,
869 
        HRESP_S15 => HRESP_S15,
870 
        -- Output
871 
        HSEL_S15 => HSEL_S15,
872 
        HADDR_S15 => HADDR_S15,
873 
        HSIZE_S15 => HSIZE_S15,
874 
        HTRANS_S15 => HTRANS_S15,
875 
        HWRITE_S15 => HWRITE_S15,
876 
        HWDATA_S15 => HWDATA_S15,
877 
        HREADY_S15 => HREADYIN_S15,
878 
        HMASTLOCK_S15 => HMASTLOCK_S15,
879 
        HBURST_S15 => HBURST_S15,
880 
        HPROT_S15 => HPROT_S15,
881 
 
882 
        -- Mirrored slave AHB-Lite interface to Huge Slave
883 
        -- Inputs
884 
        HRDATA_S16 => HRDATA_S16,
885 
        HREADYOUT_S16 => HREADY_S16,
886 
        HRESP_S16 => HRESP_S16,
887 
        -- Outputs
888 
        HSEL_S16 => HSEL_S16,
889 
        HADDR_S16 => HADDR_S16,
890 
        HSIZE_S16 => HSIZE_S16,
891 
        HTRANS_S16 => HTRANS_S16,
892 
        HWRITE_S16 => HWRITE_S16,
893 
        HWDATA_S16 => HWDATA_S16,
894 
        HREADY_S16 => HREADYIN_S16,
895 
        HMASTLOCK_S16 => HMASTLOCK_S16,
896 
        HBURST_S16 => HBURST_S16,
897 
        HPROT_S16 => HPROT_S16
898 
);
899 
 
900 
-- BFM masters monitor various signals
901 
GP_IN <=
902 
        REMAP_M0 &           -- 31
903 
        M1_ACK &             -- 30
904 
        M1_REQ &             -- 29
905 
        M0_ACK &             -- 28
906 
        M0_REQ &             -- 27
907 
    FINISHED_master3 &   -- 26
908 
    FINISHED_master2 &   -- 25
909 
    FINISHED_master1 &   -- 24
910 
    FINISHED_master0 &   -- 23
911 
        "000000" &           -- 22:17
912 
    s16_write &          -- 16
913 
    s15_write &          -- 15
914 
    s14_write &          -- 14
915 
    s13_write &          -- 13
916 
    s12_write &          -- 12
917 
    s11_write &          -- 11
918 
    s10_write &          -- 10
919 
    s9_write &           --  9
920 
    s8_write &           --  8
921 
    s7_write &           --  7
922 
    s6_write &           --  6
923 
    s5_write &           --  5
924 
    s4_write &           --  4
925 
    s3_write &           --  3
926 
    s2_write &           --  2
927 
    s1_write &           --  1
928 
    s0_write;            --  0
929 
 
930 
 
931 
-- Master 0 BFM
932 
master0 : BFM_AHBL
933 
generic map (
934 
        VECTFILE    => MASTER0_VECTFILE,
935 
        -- passing testbench parameters to BFM ARGVALUE* parameters
936 
        ARGVALUE0   => FAMILY,
937 
        ARGVALUE1   => MEMSPACE,
938 
        ARGVALUE2   => HADDR_SHG_CFG,
939 
        ARGVALUE3   => SC_0 ,
940 
        ARGVALUE4   => SC_1 ,
941 
        ARGVALUE5   => SC_2 ,
942 
        ARGVALUE6   => SC_3 ,
943 
        ARGVALUE7   => SC_4 ,
944 
        ARGVALUE8   => SC_5 ,
945 
        ARGVALUE9   => SC_6 ,
946 
        ARGVALUE10  => SC_7 ,
947 
        ARGVALUE11  => SC_8 ,
948 
        ARGVALUE12  => SC_9 ,
949 
        ARGVALUE13  => SC_10,
950 
        ARGVALUE14  => SC_11,
951 
        ARGVALUE15  => SC_12,
952 
        ARGVALUE16  => SC_13,
953 
        ARGVALUE17  => SC_14,
954 
        ARGVALUE18  => SC_15,
955 
        ARGVALUE19  => M0_AHBSLOT0ENABLE ,
956 
        ARGVALUE20  => M0_AHBSLOT1ENABLE ,
957 
        ARGVALUE21  => M0_AHBSLOT2ENABLE ,
958 
        ARGVALUE22  => M0_AHBSLOT3ENABLE ,
959 
        ARGVALUE23  => M0_AHBSLOT4ENABLE ,
960 
        ARGVALUE24  => M0_AHBSLOT5ENABLE ,
961 
        ARGVALUE25  => M0_AHBSLOT6ENABLE ,
962 
        ARGVALUE26  => M0_AHBSLOT7ENABLE ,
963 
        ARGVALUE27  => M0_AHBSLOT8ENABLE ,
964 
        ARGVALUE28  => M0_AHBSLOT9ENABLE ,
965 
        ARGVALUE29  => M0_AHBSLOT10ENABLE,
966 
        ARGVALUE30  => M0_AHBSLOT11ENABLE,
967 
        ARGVALUE31  => M0_AHBSLOT12ENABLE,
968 
        ARGVALUE32  => M0_AHBSLOT13ENABLE,
969 
        ARGVALUE33  => M0_AHBSLOT14ENABLE,
970 
        ARGVALUE34  => M0_AHBSLOT15ENABLE,
971 
        ARGVALUE35  => M0_AHBSLOT16ENABLE,
972 
        ARGVALUE36  => M1_AHBSLOT0ENABLE ,
973 
        ARGVALUE37  => M1_AHBSLOT1ENABLE ,
974 
        ARGVALUE38  => M1_AHBSLOT2ENABLE ,
975 
        ARGVALUE39  => M1_AHBSLOT3ENABLE ,
976 
        ARGVALUE40  => M1_AHBSLOT4ENABLE ,
977 
        ARGVALUE41  => M1_AHBSLOT5ENABLE ,
978 
        ARGVALUE42  => M1_AHBSLOT6ENABLE ,
979 
        ARGVALUE43  => M1_AHBSLOT7ENABLE ,
980 
        ARGVALUE44  => M1_AHBSLOT8ENABLE ,
981 
        ARGVALUE45  => M1_AHBSLOT9ENABLE ,
982 
        ARGVALUE46  => M1_AHBSLOT10ENABLE,
983 
        ARGVALUE47  => M1_AHBSLOT11ENABLE,
984 
        ARGVALUE48  => M1_AHBSLOT12ENABLE,
985 
        ARGVALUE49  => M1_AHBSLOT13ENABLE,
986 
        ARGVALUE50  => M1_AHBSLOT14ENABLE,
987 
        ARGVALUE51  => M1_AHBSLOT15ENABLE,
988 
        ARGVALUE52  => M1_AHBSLOT16ENABLE,
989 
        ARGVALUE53  => M2_AHBSLOT0ENABLE ,
990 
        ARGVALUE54  => M2_AHBSLOT1ENABLE ,
991 
        ARGVALUE55  => M2_AHBSLOT2ENABLE ,
992 
        ARGVALUE56  => M2_AHBSLOT3ENABLE ,
993 
        ARGVALUE57  => M2_AHBSLOT4ENABLE ,
994 
        ARGVALUE58  => M2_AHBSLOT5ENABLE ,
995 
        ARGVALUE59  => M2_AHBSLOT6ENABLE ,
996 
        ARGVALUE60  => M2_AHBSLOT7ENABLE ,
997 
        ARGVALUE61  => M2_AHBSLOT8ENABLE ,
998 
        ARGVALUE62  => M2_AHBSLOT9ENABLE ,
999 
        ARGVALUE63  => M2_AHBSLOT10ENABLE,
1000 
        ARGVALUE64  => M2_AHBSLOT11ENABLE,
1001 
        ARGVALUE65  => M2_AHBSLOT12ENABLE,
1002 
        ARGVALUE66  => M2_AHBSLOT13ENABLE,
1003 
        ARGVALUE67  => M2_AHBSLOT14ENABLE,
1004 
        ARGVALUE68  => M2_AHBSLOT15ENABLE,
1005 
        ARGVALUE69  => M2_AHBSLOT16ENABLE,
1006 
        ARGVALUE70  => M3_AHBSLOT0ENABLE ,
1007 
        ARGVALUE71  => M3_AHBSLOT1ENABLE ,
1008 
        ARGVALUE72  => M3_AHBSLOT2ENABLE ,
1009 
        ARGVALUE73  => M3_AHBSLOT3ENABLE ,
1010 
        ARGVALUE74  => M3_AHBSLOT4ENABLE ,
1011 
        ARGVALUE75  => M3_AHBSLOT5ENABLE ,
1012 
        ARGVALUE76  => M3_AHBSLOT6ENABLE ,
1013 
        ARGVALUE77  => M3_AHBSLOT7ENABLE ,
1014 
        ARGVALUE78  => M3_AHBSLOT8ENABLE ,
1015 
        ARGVALUE79  => M3_AHBSLOT9ENABLE ,
1016 
        ARGVALUE80  => M3_AHBSLOT10ENABLE,
1017 
        ARGVALUE81  => M3_AHBSLOT11ENABLE,
1018 
        ARGVALUE82  => M3_AHBSLOT12ENABLE,
1019 
        ARGVALUE83  => M3_AHBSLOT13ENABLE,
1020 
        ARGVALUE84  => M3_AHBSLOT14ENABLE,
1021 
        ARGVALUE85  => M3_AHBSLOT15ENABLE,
1022 
        ARGVALUE86  => M3_AHBSLOT16ENABLE
1023 
) port map (
1024 
        -- Inputs
1025 
        SYSCLK          => SYSCLK,
1026 
        SYSRSTN         => SYSRSTN,
1027 
        HREADY          => HREADY_M0,
1028 
        HRESP           => HRESP_M0(0),
1029 
        HRDATA          => HRDATA_M0,
1030 
        -- Outputs
1031 
        HCLK            => HCLK,
1032 
        HRESETN         => HRESETN,
1033 
        HTRANS          => HTRANS_M0,
1034 
        HBURST          => open,
1035 
        HSEL            => open,
1036 
        HPROT           => open,
1037 
        HSIZE           => HSIZE_M0,
1038 
        HWRITE          => HWRITE_M0,
1039 
        HMASTLOCK       => HMASTLOCK_M0,
1040 
        HADDR           => HADDR_M0,
1041 
        HWDATA          => HWDATA_M0,
1042 
        INTERRUPT       => GND256,
1043 
        GP_OUT          => GP_OUT_M0,
1044 
        GP_IN           => GP_IN,
1045 
        EXT_WR          => open,
1046 
        EXT_RD          => open,
1047 
        EXT_ADDR        => open,
1048 
        EXT_DATA        => open,
1049 
        EXT_WAIT        => '0',
1050 
        FINISHED        => FINISHED_master0,
1051 
        FAILED          => open
1052 
);
1053 
 
1054 
-- control remap signals from master 0 BFM
1055 
REMAP_M0        <= GP_OUT_M0(31);
1056 
 
1057 
-- signals for testbench request/acknowledgement between masters
1058 
M0_REQ          <= GP_OUT_M0(27);
1059 
M0_ACK          <= GP_OUT_M0(28);
1060 
 
1061 
 
1062 
-- Master 1 BFM
1063 
master1 : BFM_AHBL
1064 
generic map (
1065 
        VECTFILE    => MASTER1_VECTFILE,
1066 
        -- passing testbench parameters to BFM ARGVALUE* parameters
1067 
        ARGVALUE0   => FAMILY,
1068 
        ARGVALUE1   => MEMSPACE,
1069 
        ARGVALUE2   => HADDR_SHG_CFG,
1070 
        ARGVALUE3   => SC_0 ,
1071 
        ARGVALUE4   => SC_1 ,
1072 
        ARGVALUE5   => SC_2 ,
1073 
        ARGVALUE6   => SC_3 ,
1074 
        ARGVALUE7   => SC_4 ,
1075 
        ARGVALUE8   => SC_5 ,
1076 
        ARGVALUE9   => SC_6 ,
1077 
        ARGVALUE10  => SC_7 ,
1078 
        ARGVALUE11  => SC_8 ,
1079 
        ARGVALUE12  => SC_9 ,
1080 
        ARGVALUE13  => SC_10,
1081 
        ARGVALUE14  => SC_11,
1082 
        ARGVALUE15  => SC_12,
1083 
        ARGVALUE16  => SC_13,
1084 
        ARGVALUE17  => SC_14,
1085 
        ARGVALUE18  => SC_15,
1086 
        ARGVALUE19  => M0_AHBSLOT0ENABLE ,
1087 
        ARGVALUE20  => M0_AHBSLOT1ENABLE ,
1088 
        ARGVALUE21  => M0_AHBSLOT2ENABLE ,
1089 
        ARGVALUE22  => M0_AHBSLOT3ENABLE ,
1090 
        ARGVALUE23  => M0_AHBSLOT4ENABLE ,
1091 
        ARGVALUE24  => M0_AHBSLOT5ENABLE ,
1092 
        ARGVALUE25  => M0_AHBSLOT6ENABLE ,
1093 
        ARGVALUE26  => M0_AHBSLOT7ENABLE ,
1094 
        ARGVALUE27  => M0_AHBSLOT8ENABLE ,
1095 
        ARGVALUE28  => M0_AHBSLOT9ENABLE ,
1096 
        ARGVALUE29  => M0_AHBSLOT10ENABLE,
1097 
        ARGVALUE30  => M0_AHBSLOT11ENABLE,
1098 
        ARGVALUE31  => M0_AHBSLOT12ENABLE,
1099 
        ARGVALUE32  => M0_AHBSLOT13ENABLE,
1100 
        ARGVALUE33  => M0_AHBSLOT14ENABLE,
1101 
        ARGVALUE34  => M0_AHBSLOT15ENABLE,
1102 
        ARGVALUE35  => M0_AHBSLOT16ENABLE,
1103 
        ARGVALUE36  => M1_AHBSLOT0ENABLE ,
1104 
        ARGVALUE37  => M1_AHBSLOT1ENABLE ,
1105 
        ARGVALUE38  => M1_AHBSLOT2ENABLE ,
1106 
        ARGVALUE39  => M1_AHBSLOT3ENABLE ,
1107 
        ARGVALUE40  => M1_AHBSLOT4ENABLE ,
1108 
        ARGVALUE41  => M1_AHBSLOT5ENABLE ,
1109 
        ARGVALUE42  => M1_AHBSLOT6ENABLE ,
1110 
        ARGVALUE43  => M1_AHBSLOT7ENABLE ,
1111 
        ARGVALUE44  => M1_AHBSLOT8ENABLE ,
1112 
        ARGVALUE45  => M1_AHBSLOT9ENABLE ,
1113 
        ARGVALUE46  => M1_AHBSLOT10ENABLE,
1114 
        ARGVALUE47  => M1_AHBSLOT11ENABLE,
1115 
        ARGVALUE48  => M1_AHBSLOT12ENABLE,
1116 
        ARGVALUE49  => M1_AHBSLOT13ENABLE,
1117 
        ARGVALUE50  => M1_AHBSLOT14ENABLE,
1118 
        ARGVALUE51  => M1_AHBSLOT15ENABLE,
1119 
        ARGVALUE52  => M1_AHBSLOT16ENABLE,
1120 
        ARGVALUE53  => M2_AHBSLOT0ENABLE ,
1121 
        ARGVALUE54  => M2_AHBSLOT1ENABLE ,
1122 
        ARGVALUE55  => M2_AHBSLOT2ENABLE ,
1123 
        ARGVALUE56  => M2_AHBSLOT3ENABLE ,
1124 
        ARGVALUE57  => M2_AHBSLOT4ENABLE ,
1125 
        ARGVALUE58  => M2_AHBSLOT5ENABLE ,
1126 
        ARGVALUE59  => M2_AHBSLOT6ENABLE ,
1127 
        ARGVALUE60  => M2_AHBSLOT7ENABLE ,
1128 
        ARGVALUE61  => M2_AHBSLOT8ENABLE ,
1129 
        ARGVALUE62  => M2_AHBSLOT9ENABLE ,
1130 
        ARGVALUE63  => M2_AHBSLOT10ENABLE,
1131 
        ARGVALUE64  => M2_AHBSLOT11ENABLE,
1132 
        ARGVALUE65  => M2_AHBSLOT12ENABLE,
1133 
        ARGVALUE66  => M2_AHBSLOT13ENABLE,
1134 
        ARGVALUE67  => M2_AHBSLOT14ENABLE,
1135 
        ARGVALUE68  => M2_AHBSLOT15ENABLE,
1136 
        ARGVALUE69  => M2_AHBSLOT16ENABLE,
1137 
        ARGVALUE70  => M3_AHBSLOT0ENABLE ,
1138 
        ARGVALUE71  => M3_AHBSLOT1ENABLE ,
1139 
        ARGVALUE72  => M3_AHBSLOT2ENABLE ,
1140 
        ARGVALUE73  => M3_AHBSLOT3ENABLE ,
1141 
        ARGVALUE74  => M3_AHBSLOT4ENABLE ,
1142 
        ARGVALUE75  => M3_AHBSLOT5ENABLE ,
1143 
        ARGVALUE76  => M3_AHBSLOT6ENABLE ,
1144 
        ARGVALUE77  => M3_AHBSLOT7ENABLE ,
1145 
        ARGVALUE78  => M3_AHBSLOT8ENABLE ,
1146 
        ARGVALUE79  => M3_AHBSLOT9ENABLE ,
1147 
        ARGVALUE80  => M3_AHBSLOT10ENABLE,
1148 
        ARGVALUE81  => M3_AHBSLOT11ENABLE,
1149 
        ARGVALUE82  => M3_AHBSLOT12ENABLE,
1150 
        ARGVALUE83  => M3_AHBSLOT13ENABLE,
1151 
        ARGVALUE84  => M3_AHBSLOT14ENABLE,
1152 
        ARGVALUE85  => M3_AHBSLOT15ENABLE,
1153 
        ARGVALUE86  => M3_AHBSLOT16ENABLE
1154 
) port map (
1155 
        -- Inputs
1156 
        SYSCLK  => SYSCLK,
1157 
        SYSRSTN => SYSRSTN,
1158 
        HREADY  => HREADY_M1,
1159 
        HRESP   => HRESP_M1(0),
1160 
        HRDATA  => HRDATA_M1,
1161 
        -- Outputs
1162 
        -- using master 0 HCLK,HRESETN to drive slaves & DUT
1163 
        HCLK            => open,
1164 
        HRESETN         => open,
1165 
        HTRANS          => HTRANS_M1,
1166 
        HBURST          => open,
1167 
        HSEL            => open,
1168 
        HPROT           => open,
1169 
        HSIZE           => HSIZE_M1,
1170 
        HWRITE          => HWRITE_M1,
1171 
        HMASTLOCK       => HMASTLOCK_M1,
1172 
        HADDR           => HADDR_M1,
1173 
        HWDATA          => HWDATA_M1,
1174 
        INTERRUPT       => GND256,
1175 
        GP_OUT          => GP_OUT_M1,
1176 
        GP_IN           => GP_IN,
1177 
        EXT_WR          => open,
1178 
        EXT_RD          => open,
1179 
        EXT_ADDR        => open,
1180 
        EXT_DATA        => open,
1181 
        EXT_WAIT        => '0',
1182 
        FINISHED        => FINISHED_master1,
1183 
        FAILED          => open
1184 
);
1185 
 
1186 
-- signals for testbench request/acknowledgement between masters
1187 
M1_REQ                  <= GP_OUT_M1(29);
1188 
M1_ACK                  <= GP_OUT_M1(30);
1189 
 
1190 
 
1191 
-- Master 2 BFM
1192 
master2 : BFM_AHBL
1193 
generic map (
1194 
        VECTFILE    => MASTER2_VECTFILE,
1195 
        -- passing testbench parameters to BFM ARGVALUE* parameters
1196 
        ARGVALUE0   => FAMILY,
1197 
        ARGVALUE1   => MEMSPACE,
1198 
        ARGVALUE2   => HADDR_SHG_CFG,
1199 
        ARGVALUE3   => SC_0 ,
1200 
        ARGVALUE4   => SC_1 ,
1201 
        ARGVALUE5   => SC_2 ,
1202 
        ARGVALUE6   => SC_3 ,
1203 
        ARGVALUE7   => SC_4 ,
1204 
        ARGVALUE8   => SC_5 ,
1205 
        ARGVALUE9   => SC_6 ,
1206 
        ARGVALUE10  => SC_7 ,
1207 
        ARGVALUE11  => SC_8 ,
1208 
        ARGVALUE12  => SC_9 ,
1209 
        ARGVALUE13  => SC_10,
1210 
        ARGVALUE14  => SC_11,
1211 
        ARGVALUE15  => SC_12,
1212 
        ARGVALUE16  => SC_13,
1213 
        ARGVALUE17  => SC_14,
1214 
        ARGVALUE18  => SC_15,
1215 
        ARGVALUE19  => M0_AHBSLOT0ENABLE ,
1216 
        ARGVALUE20  => M0_AHBSLOT1ENABLE ,
1217 
        ARGVALUE21  => M0_AHBSLOT2ENABLE ,
1218 
        ARGVALUE22  => M0_AHBSLOT3ENABLE ,
1219 
        ARGVALUE23  => M0_AHBSLOT4ENABLE ,
1220 
        ARGVALUE24  => M0_AHBSLOT5ENABLE ,
1221 
        ARGVALUE25  => M0_AHBSLOT6ENABLE ,
1222 
        ARGVALUE26  => M0_AHBSLOT7ENABLE ,
1223 
        ARGVALUE27  => M0_AHBSLOT8ENABLE ,
1224 
        ARGVALUE28  => M0_AHBSLOT9ENABLE ,
1225 
        ARGVALUE29  => M0_AHBSLOT10ENABLE,
1226 
        ARGVALUE30  => M0_AHBSLOT11ENABLE,
1227 
        ARGVALUE31  => M0_AHBSLOT12ENABLE,
1228 
        ARGVALUE32  => M0_AHBSLOT13ENABLE,
1229 
        ARGVALUE33  => M0_AHBSLOT14ENABLE,
1230 
        ARGVALUE34  => M0_AHBSLOT15ENABLE,
1231 
        ARGVALUE35  => M0_AHBSLOT16ENABLE,
1232 
        ARGVALUE36  => M1_AHBSLOT0ENABLE ,
1233 
        ARGVALUE37  => M1_AHBSLOT1ENABLE ,
1234 
        ARGVALUE38  => M1_AHBSLOT2ENABLE ,
1235 
        ARGVALUE39  => M1_AHBSLOT3ENABLE ,
1236 
        ARGVALUE40  => M1_AHBSLOT4ENABLE ,
1237 
        ARGVALUE41  => M1_AHBSLOT5ENABLE ,
1238 
        ARGVALUE42  => M1_AHBSLOT6ENABLE ,
1239 
        ARGVALUE43  => M1_AHBSLOT7ENABLE ,
1240 
        ARGVALUE44  => M1_AHBSLOT8ENABLE ,
1241 
        ARGVALUE45  => M1_AHBSLOT9ENABLE ,
1242 
        ARGVALUE46  => M1_AHBSLOT10ENABLE,
1243 
        ARGVALUE47  => M1_AHBSLOT11ENABLE,
1244 
        ARGVALUE48  => M1_AHBSLOT12ENABLE,
1245 
        ARGVALUE49  => M1_AHBSLOT13ENABLE,
1246 
        ARGVALUE50  => M1_AHBSLOT14ENABLE,
1247 
        ARGVALUE51  => M1_AHBSLOT15ENABLE,
1248 
        ARGVALUE52  => M1_AHBSLOT16ENABLE,
1249 
        ARGVALUE53  => M2_AHBSLOT0ENABLE ,
1250 
        ARGVALUE54  => M2_AHBSLOT1ENABLE ,
1251 
        ARGVALUE55  => M2_AHBSLOT2ENABLE ,
1252 
        ARGVALUE56  => M2_AHBSLOT3ENABLE ,
1253 
        ARGVALUE57  => M2_AHBSLOT4ENABLE ,
1254 
        ARGVALUE58  => M2_AHBSLOT5ENABLE ,
1255 
        ARGVALUE59  => M2_AHBSLOT6ENABLE ,
1256 
        ARGVALUE60  => M2_AHBSLOT7ENABLE ,
1257 
        ARGVALUE61  => M2_AHBSLOT8ENABLE ,
1258 
        ARGVALUE62  => M2_AHBSLOT9ENABLE ,
1259 
        ARGVALUE63  => M2_AHBSLOT10ENABLE,
1260 
        ARGVALUE64  => M2_AHBSLOT11ENABLE,
1261 
        ARGVALUE65  => M2_AHBSLOT12ENABLE,
1262 
        ARGVALUE66  => M2_AHBSLOT13ENABLE,
1263 
        ARGVALUE67  => M2_AHBSLOT14ENABLE,
1264 
        ARGVALUE68  => M2_AHBSLOT15ENABLE,
1265 
        ARGVALUE69  => M2_AHBSLOT16ENABLE,
1266 
        ARGVALUE70  => M3_AHBSLOT0ENABLE ,
1267 
        ARGVALUE71  => M3_AHBSLOT1ENABLE ,
1268 
        ARGVALUE72  => M3_AHBSLOT2ENABLE ,
1269 
        ARGVALUE73  => M3_AHBSLOT3ENABLE ,
1270 
        ARGVALUE74  => M3_AHBSLOT4ENABLE ,
1271 
        ARGVALUE75  => M3_AHBSLOT5ENABLE ,
1272 
        ARGVALUE76  => M3_AHBSLOT6ENABLE ,
1273 
        ARGVALUE77  => M3_AHBSLOT7ENABLE ,
1274 
        ARGVALUE78  => M3_AHBSLOT8ENABLE ,
1275 
        ARGVALUE79  => M3_AHBSLOT9ENABLE ,
1276 
        ARGVALUE80  => M3_AHBSLOT10ENABLE,
1277 
        ARGVALUE81  => M3_AHBSLOT11ENABLE,
1278 
        ARGVALUE82  => M3_AHBSLOT12ENABLE,
1279 
        ARGVALUE83  => M3_AHBSLOT13ENABLE,
1280 
        ARGVALUE84  => M3_AHBSLOT14ENABLE,
1281 
        ARGVALUE85  => M3_AHBSLOT15ENABLE,
1282 
        ARGVALUE86  => M3_AHBSLOT16ENABLE
1283 
) port map (
1284 
        -- Inputs
1285 
        SYSCLK  => SYSCLK,
1286 
        SYSRSTN => SYSRSTN,
1287 
        HREADY  => HREADY_M2,
1288 
        HRESP   => HRESP_M2(0),
1289 
        HRDATA  => HRDATA_M2,
1290 
        -- Outputs
1291 
        -- using master 0 HCLK,HRESETN to drive slaves & DUT
1292 
        HCLK            => open,
1293 
        HRESETN         => open,
1294 
        HTRANS          => HTRANS_M2,
1295 
        HBURST          => open,
1296 
        HSEL            => open,
1297 
        HPROT           => open,
1298 
        HSIZE           => HSIZE_M2,
1299 
        HWRITE          => HWRITE_M2,
1300 
        HMASTLOCK       => HMASTLOCK_M2,
1301 
        HADDR           => HADDR_M2,
1302 
        HWDATA          => HWDATA_M2,
1303 
        INTERRUPT       => GND256,
1304 
        GP_OUT          => open,
1305 
        GP_IN           => GP_IN,
1306 
        EXT_WR          => open,
1307 
        EXT_RD          => open,
1308 
        EXT_ADDR        => open,
1309 
        EXT_DATA        => open,
1310 
        EXT_WAIT        => '0',
1311 
        FINISHED        => FINISHED_master2,
1312 
        FAILED          => open
1313 
);
1314 
 
1315 
-- Master 3 BFM
1316 
master3 : BFM_AHBL
1317 
generic map (
1318 
        VECTFILE    => MASTER3_VECTFILE,
1319 
        -- passing testbench parameters to BFM ARGVALUE* parameters
1320 
        ARGVALUE0   => FAMILY,
1321 
        ARGVALUE1   => MEMSPACE,
1322 
        ARGVALUE2   => HADDR_SHG_CFG,
1323 
        ARGVALUE3   => SC_0 ,
1324 
        ARGVALUE4   => SC_1 ,
1325 
        ARGVALUE5   => SC_2 ,
1326 
        ARGVALUE6   => SC_3 ,
1327 
        ARGVALUE7   => SC_4 ,
1328 
        ARGVALUE8   => SC_5 ,
1329 
        ARGVALUE9   => SC_6 ,
1330 
        ARGVALUE10  => SC_7 ,
1331 
        ARGVALUE11  => SC_8 ,
1332 
        ARGVALUE12  => SC_9 ,
1333 
        ARGVALUE13  => SC_10,
1334 
        ARGVALUE14  => SC_11,
1335 
        ARGVALUE15  => SC_12,
1336 
        ARGVALUE16  => SC_13,
1337 
        ARGVALUE17  => SC_14,
1338 
        ARGVALUE18  => SC_15,
1339 
        ARGVALUE19  => M0_AHBSLOT0ENABLE ,
1340 
        ARGVALUE20  => M0_AHBSLOT1ENABLE ,
1341 
        ARGVALUE21  => M0_AHBSLOT2ENABLE ,
1342 
        ARGVALUE22  => M0_AHBSLOT3ENABLE ,
1343 
        ARGVALUE23  => M0_AHBSLOT4ENABLE ,
1344 
        ARGVALUE24  => M0_AHBSLOT5ENABLE ,
1345 
        ARGVALUE25  => M0_AHBSLOT6ENABLE ,
1346 
        ARGVALUE26  => M0_AHBSLOT7ENABLE ,
1347 
        ARGVALUE27  => M0_AHBSLOT8ENABLE ,
1348 
        ARGVALUE28  => M0_AHBSLOT9ENABLE ,
1349 
        ARGVALUE29  => M0_AHBSLOT10ENABLE,
1350 
        ARGVALUE30  => M0_AHBSLOT11ENABLE,
1351 
        ARGVALUE31  => M0_AHBSLOT12ENABLE,
1352 
        ARGVALUE32  => M0_AHBSLOT13ENABLE,
1353 
        ARGVALUE33  => M0_AHBSLOT14ENABLE,
1354 
        ARGVALUE34  => M0_AHBSLOT15ENABLE,
1355 
        ARGVALUE35  => M0_AHBSLOT16ENABLE,
1356 
        ARGVALUE36  => M1_AHBSLOT0ENABLE ,
1357 
        ARGVALUE37  => M1_AHBSLOT1ENABLE ,
1358 
        ARGVALUE38  => M1_AHBSLOT2ENABLE ,
1359 
        ARGVALUE39  => M1_AHBSLOT3ENABLE ,
1360 
        ARGVALUE40  => M1_AHBSLOT4ENABLE ,
1361 
        ARGVALUE41  => M1_AHBSLOT5ENABLE ,
1362 
        ARGVALUE42  => M1_AHBSLOT6ENABLE ,
1363 
        ARGVALUE43  => M1_AHBSLOT7ENABLE ,
1364 
        ARGVALUE44  => M1_AHBSLOT8ENABLE ,
1365 
        ARGVALUE45  => M1_AHBSLOT9ENABLE ,
1366 
        ARGVALUE46  => M1_AHBSLOT10ENABLE,
1367 
        ARGVALUE47  => M1_AHBSLOT11ENABLE,
1368 
        ARGVALUE48  => M1_AHBSLOT12ENABLE,
1369 
        ARGVALUE49  => M1_AHBSLOT13ENABLE,
1370 
        ARGVALUE50  => M1_AHBSLOT14ENABLE,
1371 
        ARGVALUE51  => M1_AHBSLOT15ENABLE,
1372 
        ARGVALUE52  => M1_AHBSLOT16ENABLE,
1373 
        ARGVALUE53  => M2_AHBSLOT0ENABLE ,
1374 
        ARGVALUE54  => M2_AHBSLOT1ENABLE ,
1375 
        ARGVALUE55  => M2_AHBSLOT2ENABLE ,
1376 
        ARGVALUE56  => M2_AHBSLOT3ENABLE ,
1377 
        ARGVALUE57  => M2_AHBSLOT4ENABLE ,
1378 
        ARGVALUE58  => M2_AHBSLOT5ENABLE ,
1379 
        ARGVALUE59  => M2_AHBSLOT6ENABLE ,
1380 
        ARGVALUE60  => M2_AHBSLOT7ENABLE ,
1381 
        ARGVALUE61  => M2_AHBSLOT8ENABLE ,
1382 
        ARGVALUE62  => M2_AHBSLOT9ENABLE ,
1383 
        ARGVALUE63  => M2_AHBSLOT10ENABLE,
1384 
        ARGVALUE64  => M2_AHBSLOT11ENABLE,
1385 
        ARGVALUE65  => M2_AHBSLOT12ENABLE,
1386 
        ARGVALUE66  => M2_AHBSLOT13ENABLE,
1387 
        ARGVALUE67  => M2_AHBSLOT14ENABLE,
1388 
        ARGVALUE68  => M2_AHBSLOT15ENABLE,
1389 
        ARGVALUE69  => M2_AHBSLOT16ENABLE,
1390 
        ARGVALUE70  => M3_AHBSLOT0ENABLE ,
1391 
        ARGVALUE71  => M3_AHBSLOT1ENABLE ,
1392 
        ARGVALUE72  => M3_AHBSLOT2ENABLE ,
1393 
        ARGVALUE73  => M3_AHBSLOT3ENABLE ,
1394 
        ARGVALUE74  => M3_AHBSLOT4ENABLE ,
1395 
        ARGVALUE75  => M3_AHBSLOT5ENABLE ,
1396 
        ARGVALUE76  => M3_AHBSLOT6ENABLE ,
1397 
        ARGVALUE77  => M3_AHBSLOT7ENABLE ,
1398 
        ARGVALUE78  => M3_AHBSLOT8ENABLE ,
1399 
        ARGVALUE79  => M3_AHBSLOT9ENABLE ,
1400 
        ARGVALUE80  => M3_AHBSLOT10ENABLE,
1401 
        ARGVALUE81  => M3_AHBSLOT11ENABLE,
1402 
        ARGVALUE82  => M3_AHBSLOT12ENABLE,
1403 
        ARGVALUE83  => M3_AHBSLOT13ENABLE,
1404 
        ARGVALUE84  => M3_AHBSLOT14ENABLE,
1405 
        ARGVALUE85  => M3_AHBSLOT15ENABLE,
1406 
        ARGVALUE86  => M3_AHBSLOT16ENABLE
1407 
) port map (
1408 
        -- Inputs
1409 
        SYSCLK  => SYSCLK,
1410 
        SYSRSTN => SYSRSTN,
1411 
        HREADY  => HREADY_M3,
1412 
        HRESP   => HRESP_M3(0),
1413 
        HRDATA  => HRDATA_M3,
1414 
        -- Outputs
1415 
        -- using master 0 HCLK,HRESETN to drive slaves & DUT
1416 
        HCLK            => open,
1417 
        HRESETN         => open,
1418 
        HTRANS          => HTRANS_M3,
1419 
        HBURST          => open,
1420 
        HSEL            => open,
1421 
        HPROT           => open,
1422 
        HSIZE           => HSIZE_M3,
1423 
        HWRITE          => HWRITE_M3,
1424 
        HMASTLOCK       => HMASTLOCK_M3,
1425 
        HADDR           => HADDR_M3,
1426 
        HWDATA          => HWDATA_M3,
1427 
        INTERRUPT       => GND256,
1428 
        GP_OUT          => open,
1429 
        GP_IN           => GP_IN,
1430 
        EXT_WR          => open,
1431 
        EXT_RD          => open,
1432 
        EXT_ADDR        => open,
1433 
        EXT_DATA        => open,
1434 
        EXT_WAIT        => '0',
1435 
        FINISHED        => FINISHED_master3,
1436 
        FAILED          => open
1437 
);
1438 
 
1439 
 
1440 
   slave0 : BFM_AHBSLAVE
1441 
      generic map (
1442 
         awidth    => 16,
1443 
         depth     => 65536,
1444 
         initfile  => " ",
1445 
         id        => 1,
1446 
         enfunc    => 0,
1447 
         tpd       => 5,
1448 
         debug     => 0
1449 
      )
1450 
      port map (
1451 
         -- MP7Bridge interface
1452 
         -- Inputs
1453 
         hclk       => HCLK,
1454 
         hresetn    => HRESETN,
1455 
         -- AhbFabric interface
1456 
         -- Inputs
1457 
         hwrite     => HWRITE_S0,
1458 
         hsize      => HSIZE_S0,
1459 
         htrans     => HTRANS_S0,
1460 
         hwdata     => HWDATA_S0,
1461 
         hreadyin   => HREADYIN_S0,
1462 
         hsel       => HSEL_S0,
1463 
         haddr      => HADDR_S0(15 downto 0),
1464 
         hmastlock  => '0',
1465 
         hburst     => HBURST_S0,
1466 
         hprot      => HPROT_S0,
1467 
         -- Output
1468 
         hrdata     => HRDATA_S0,
1469 
         hresp      => HRESP_S0(0),
1470 
         hreadyout  => HREADY_S0
1471 
      );
1472 
 
1473 
 
1474 
 
1475 
   slave1 : BFM_AHBSLAVE
1476 
      generic map (
1477 
         awidth    => 16,
1478 
         depth     => 65536,
1479 
         initfile  => " ",
1480 
         id        => 1,
1481 
         enfunc    => 0,
1482 
         tpd       => 5,
1483 
         debug     => 0
1484 
      )
1485 
      port map (
1486 
         -- MP7Bridge interface
1487 
         -- Inputs
1488 
         hclk       => HCLK,
1489 
         hresetn    => HRESETN,
1490 
         -- AhbFabric interface
1491 
         -- Inputs
1492 
         hwrite     => HWRITE_S1,
1493 
         hsize      => HSIZE_S1,
1494 
         htrans     => HTRANS_S1,
1495 
         hwdata     => HWDATA_S1,
1496 
         hreadyin   => HREADYIN_S1,
1497 
         hsel       => HSEL_S1,
1498 
         haddr      => HADDR_S1(15 downto 0),
1499 
         hmastlock  => '0',
1500 
         hburst     => HBURST_S1,
1501 
         hprot      => HPROT_S1,
1502 
         -- Output
1503 
         hrdata     => HRDATA_S1,
1504 
         hresp      => HRESP_S1(0),
1505 
         hreadyout  => HREADY_S1
1506 
      );
1507 
 
1508 
 
1509 
 
1510 
   slave2 : BFM_AHBSLAVE
1511 
      generic map (
1512 
         awidth    => 16,
1513 
         depth     => 65536,
1514 
         initfile  => " ",
1515 
         id        => 1,
1516 
         enfunc    => 0,
1517 
         tpd       => 5,
1518 
         debug     => 0
1519 
      )
1520 
      port map (
1521 
         -- MP7Bridge interface
1522 
         -- Inputs
1523 
         hclk       => HCLK,
1524 
         hresetn    => HRESETN,
1525 
         -- AhbFabric interface
1526 
         -- Inputs
1527 
         hwrite     => HWRITE_S2,
1528 
         hsize      => HSIZE_S2,
1529 
         htrans     => HTRANS_S2,
1530 
         hwdata     => HWDATA_S2,
1531 
         hreadyin   => HREADYIN_S2,
1532 
         hsel       => HSEL_S2,
1533 
         haddr      => HADDR_S2(15 downto 0),
1534 
         hmastlock  => '0',
1535 
         hburst     => HBURST_S2,
1536 
         hprot      => HPROT_S2,
1537 
         -- Output
1538 
         hrdata     => HRDATA_S2,
1539 
         hresp      => HRESP_S2(0),
1540 
         hreadyout  => HREADY_S2
1541 
      );
1542 
 
1543 
 
1544 
 
1545 
   slave3 : BFM_AHBSLAVE
1546 
      generic map (
1547 
         awidth    => 16,
1548 
         depth     => 65536,
1549 
         initfile  => " ",
1550 
         id        => 1,
1551 
         enfunc    => 0,
1552 
         tpd       => 5,
1553 
         debug     => 0
1554 
      )
1555 
      port map (
1556 
         -- MP7Bridge interface
1557 
         -- Inputs
1558 
         hclk       => HCLK,
1559 
         hresetn    => HRESETN,
1560 
         -- AhbFabric interface
1561 
         -- Inputs
1562 
         hwrite     => HWRITE_S3,
1563 
         hsize      => HSIZE_S3,
1564 
         htrans     => HTRANS_S3,
1565 
         hwdata     => HWDATA_S3,
1566 
         hreadyin   => HREADYIN_S3,
1567 
         hsel       => HSEL_S3,
1568 
         haddr      => HADDR_S3(15 downto 0),
1569 
         hmastlock  => '0',
1570 
         hburst     => HBURST_S3,
1571 
         hprot      => HPROT_S3,
1572 
         -- Output
1573 
         hrdata     => HRDATA_S3,
1574 
         hresp      => HRESP_S3(0),
1575 
         hreadyout  => HREADY_S3
1576 
      );
1577 
 
1578 
 
1579 
 
1580 
   slave4 : BFM_AHBSLAVE
1581 
      generic map (
1582 
         awidth    => 16,
1583 
         depth     => 65536,
1584 
         initfile  => " ",
1585 
         id        => 1,
1586 
         enfunc    => 0,
1587 
         tpd       => 5,
1588 
         debug     => 0
1589 
      )
1590 
      port map (
1591 
         -- MP7Bridge interface
1592 
         -- Inputs
1593 
         hclk       => HCLK,
1594 
         hresetn    => HRESETN,
1595 
         -- AhbFabric interface
1596 
         -- Inputs
1597 
         hwrite     => HWRITE_S4,
1598 
         hsize      => HSIZE_S4,
1599 
         htrans     => HTRANS_S4,
1600 
         hwdata     => HWDATA_S4,
1601 
         hreadyin   => HREADYIN_S4,
1602 
         hsel       => HSEL_S4,
1603 
         haddr      => HADDR_S4(15 downto 0),
1604 
         hmastlock  => '0',
1605 
         hburst     => HBURST_S4,
1606 
         hprot      => HPROT_S4,
1607 
         -- Output
1608 
         hrdata     => HRDATA_S4,
1609 
         hresp      => HRESP_S4(0),
1610 
         hreadyout  => HREADY_S4
1611 
      );
1612 
 
1613 
 
1614 
 
1615 
   slave5 : BFM_AHBSLAVE
1616 
      generic map (
1617 
         awidth    => 16,
1618 
         depth     => 65536,
1619 
         initfile  => " ",
1620 
         id        => 1,
1621 
         enfunc    => 0,
1622 
         tpd       => 5,
1623 
         debug     => 0
1624 
      )
1625 
      port map (
1626 
         -- MP7Bridge interface
1627 
         -- Inputs
1628 
         hclk       => HCLK,
1629 
         hresetn    => HRESETN,
1630 
         -- AhbFabric interface
1631 
         -- Inputs
1632 
         hwrite     => HWRITE_S5,
1633 
         hsize      => HSIZE_S5,
1634 
         htrans     => HTRANS_S5,
1635 
         hwdata     => HWDATA_S5,
1636 
         hreadyin   => HREADYIN_S5,
1637 
         hsel       => HSEL_S5,
1638 
         haddr      => HADDR_S5(15 downto 0),
1639 
         hmastlock  => '0',
1640 
         hburst     => HBURST_S5,
1641 
         hprot      => HPROT_S5,
1642 
         -- Output
1643 
         hrdata     => HRDATA_S5,
1644 
         hresp      => HRESP_S5(0),
1645 
         hreadyout  => HREADY_S5
1646 
      );
1647 
 
1648 
 
1649 
 
1650 
   slave6 : BFM_AHBSLAVE
1651 
      generic map (
1652 
         awidth    => 16,
1653 
         depth     => 65536,
1654 
         initfile  => " ",
1655 
         id        => 1,
1656 
         enfunc    => 0,
1657 
         tpd       => 5,
1658 
         debug     => 0
1659 
      )
1660 
      port map (
1661 
         -- MP7Bridge interface
1662 
         -- Inputs
1663 
         hclk       => HCLK,
1664 
         hresetn    => HRESETN,
1665 
         -- AhbFabric interface
1666 
         -- Inputs
1667 
         hwrite     => HWRITE_S6,
1668 
         hsize      => HSIZE_S6,
1669 
         htrans     => HTRANS_S6,
1670 
         hwdata     => HWDATA_S6,
1671 
         hreadyin   => HREADYIN_S6,
1672 
         hsel       => HSEL_S6,
1673 
         haddr      => HADDR_S6(15 downto 0),
1674 
         hmastlock  => '0',
1675 
         hburst     => HBURST_S6,
1676 
         hprot      => HPROT_S6,
1677 
         -- Output
1678 
         hrdata     => HRDATA_S6,
1679 
         hresp      => HRESP_S6(0),
1680 
         hreadyout  => HREADY_S6
1681 
      );
1682 
 
1683 
 
1684 
 
1685 
   slave7 : BFM_AHBSLAVE
1686 
      generic map (
1687 
         awidth    => 16,
1688 
         depth     => 65536,
1689 
         initfile  => " ",
1690 
         id        => 1,
1691 
         enfunc    => 0,
1692 
         tpd       => 5,
1693 
         debug     => 0
1694 
      )
1695 
      port map (
1696 
         -- MP7Bridge interface
1697 
         -- Inputs
1698 
         hclk       => HCLK,
1699 
         hresetn    => HRESETN,
1700 
         -- AhbFabric interface
1701 
         -- Inputs
1702 
         hwrite     => HWRITE_S7,
1703 
         hsize      => HSIZE_S7,
1704 
         htrans     => HTRANS_S7,
1705 
         hwdata     => HWDATA_S7,
1706 
         hreadyin   => HREADYIN_S7,
1707 
         hsel       => HSEL_S7,
1708 
         haddr      => HADDR_S7(15 downto 0),
1709 
         hmastlock  => '0',
1710 
         hburst     => HBURST_S7,
1711 
         hprot      => HPROT_S7,
1712 
         -- Output
1713 
         hrdata     => HRDATA_S7,
1714 
         hresp      => HRESP_S7(0),
1715 
         hreadyout  => HREADY_S7
1716 
      );
1717 
 
1718 
 
1719 
 
1720 
   slave8 : BFM_AHBSLAVE
1721 
      generic map (
1722 
         awidth    => 16,
1723 
         depth     => 65536,
1724 
         initfile  => " ",
1725 
         id        => 1,
1726 
         enfunc    => 0,
1727 
         tpd       => 5,
1728 
         debug     => 0
1729 
      )
1730 
      port map (
1731 
         -- MP7Bridge interface
1732 
         -- Inputs
1733 
         hclk       => HCLK,
1734 
         hresetn    => HRESETN,
1735 
         -- AhbFabric interface
1736 
         -- Inputs
1737 
         hwrite     => HWRITE_S8,
1738 
         hsize      => HSIZE_S8,
1739 
         htrans     => HTRANS_S8,
1740 
         hwdata     => HWDATA_S8,
1741 
         hreadyin   => HREADYIN_S8,
1742 
         hsel       => HSEL_S8,
1743 
         haddr      => HADDR_S8(15 downto 0),
1744 
         hmastlock  => '0',
1745 
         hburst     => HBURST_S8,
1746 
         hprot      => HPROT_S8,
1747 
         -- Output
1748 
         hrdata     => HRDATA_S8,
1749 
         hresp      => HRESP_S8(0),
1750 
         hreadyout  => HREADY_S8
1751 
      );
1752 
 
1753 
 
1754 
 
1755 
   slave9 : BFM_AHBSLAVE
1756 
      generic map (
1757 
         awidth    => 16,
1758 
         depth     => 65536,
1759 
         initfile  => " ",
1760 
         id        => 1,
1761 
         enfunc    => 0,
1762 
         tpd       => 5,
1763 
         debug     => 0
1764 
      )
1765 
      port map (
1766 
         -- MP7Bridge interface
1767 
         -- Inputs
1768 
         hclk       => HCLK,
1769 
         hresetn    => HRESETN,
1770 
         -- AhbFabric interface
1771 
         -- Inputs
1772 
         hwrite     => HWRITE_S9,
1773 
         hsize      => HSIZE_S9,
1774 
         htrans     => HTRANS_S9,
1775 
         hwdata     => HWDATA_S9,
1776 
         hreadyin   => HREADYIN_S9,
1777 
         hsel       => HSEL_S9,
1778 
         haddr      => HADDR_S9(15 downto 0),
1779 
         hmastlock  => '0',
1780 
         hburst     => HBURST_S9,
1781 
         hprot      => HPROT_S9,
1782 
         -- Output
1783 
         hrdata     => HRDATA_S9,
1784 
         hresp      => HRESP_S9(0),
1785 
         hreadyout  => HREADY_S9
1786 
      );
1787 
 
1788 
 
1789 
 
1790 
   slave10 : BFM_AHBSLAVE
1791 
      generic map (
1792 
         awidth    => 16,
1793 
         depth     => 65536,
1794 
         initfile  => " ",
1795 
         id        => 1,
1796 
         enfunc    => 0,
1797 
         tpd       => 5,
1798 
         debug     => 0
1799 
      )
1800 
      port map (
1801 
         -- MP7Bridge interface
1802 
         -- Inputs
1803 
         hclk       => HCLK,
1804 
         hresetn    => HRESETN,
1805 
         -- AhbFabric interface
1806 
         -- Inputs
1807 
         hwrite     => HWRITE_S10,
1808 
         hsize      => HSIZE_S10,
1809 
         htrans     => HTRANS_S10,
1810 
         hwdata     => HWDATA_S10,
1811 
         hreadyin   => HREADYIN_S10,
1812 
         hsel       => HSEL_S10,
1813 
         haddr      => HADDR_S10(15 downto 0),
1814 
         hmastlock  => '0',
1815 
         hburst     => HBURST_S10,
1816 
         hprot      => HPROT_S10,
1817 
         -- Output
1818 
         hrdata     => HRDATA_S10,
1819 
         hresp      => HRESP_S10(0),
1820 
         hreadyout  => HREADY_S10
1821 
      );
1822 
 
1823 
 
1824 
 
1825 
   slave11 : BFM_AHBSLAVE
1826 
      generic map (
1827 
         awidth    => 16,
1828 
         depth     => 65536,
1829 
         initfile  => " ",
1830 
         id        => 1,
1831 
         enfunc    => 0,
1832 
         tpd       => 5,
1833 
         debug     => 0
1834 
      )
1835 
      port map (
1836 
         -- MP7Bridge interface
1837 
         -- Inputs
1838 
         hclk       => HCLK,
1839 
         hresetn    => HRESETN,
1840 
         -- AhbFabric interface
1841 
         -- Inputs
1842 
         hwrite     => HWRITE_S11,
1843 
         hsize      => HSIZE_S11,
1844 
         htrans     => HTRANS_S11,
1845 
         hwdata     => HWDATA_S11,
1846 
         hreadyin   => HREADYIN_S11,
1847 
         hsel       => HSEL_S11,
1848 
         haddr      => HADDR_S11(15 downto 0),
1849 
         hmastlock  => '0',
1850 
         hburst     => HBURST_S11,
1851 
         hprot      => HPROT_S11,
1852 
         -- Output
1853 
         hrdata     => HRDATA_S11,
1854 
         hresp      => HRESP_S11(0),
1855 
         hreadyout  => HREADY_S11
1856 
      );
1857 
 
1858 
 
1859 
 
1860 
   slave12 : BFM_AHBSLAVE
1861 
      generic map (
1862 
         awidth    => 16,
1863 
         depth     => 65536,
1864 
         initfile  => " ",
1865 
         id        => 1,
1866 
         enfunc    => 0,
1867 
         tpd       => 5,
1868 
         debug     => 0
1869 
      )
1870 
      port map (
1871 
         -- MP7Bridge interface
1872 
         -- Inputs
1873 
         hclk       => HCLK,
1874 
         hresetn    => HRESETN,
1875 
         -- AhbFabric interface
1876 
         -- Inputs
1877 
         hwrite     => HWRITE_S12,
1878 
         hsize      => HSIZE_S12,
1879 
         htrans     => HTRANS_S12,
1880 
         hwdata     => HWDATA_S12,
1881 
         hreadyin   => HREADYIN_S12,
1882 
         hsel       => HSEL_S12,
1883 
         haddr      => HADDR_S12(15 downto 0),
1884 
         hmastlock  => '0',
1885 
         hburst     => HBURST_S12,
1886 
         hprot      => HPROT_S12,
1887 
         -- Output
1888 
         hrdata     => HRDATA_S12,
1889 
         hresp      => HRESP_S12(0),
1890 
         hreadyout  => HREADY_S12
1891 
      );
1892 
 
1893 
 
1894 
 
1895 
   slave13 : BFM_AHBSLAVE
1896 
      generic map (
1897 
         awidth    => 16,
1898 
         depth     => 65536,
1899 
         initfile  => " ",
1900 
         id        => 1,
1901 
         enfunc    => 0,
1902 
         tpd       => 5,
1903 
         debug     => 0
1904 
      )
1905 
      port map (
1906 
         -- MP7Bridge interface
1907 
         -- Inputs
1908 
         hclk       => HCLK,
1909 
         hresetn    => HRESETN,
1910 
         -- AhbFabric interface
1911 
         -- Inputs
1912 
         hwrite     => HWRITE_S13,
1913 
         hsize      => HSIZE_S13,
1914 
         htrans     => HTRANS_S13,
1915 
         hwdata     => HWDATA_S13,
1916 
         hreadyin   => HREADYIN_S13,
1917 
         hsel       => HSEL_S13,
1918 
         haddr      => HADDR_S13(15 downto 0),
1919 
         hmastlock  => '0',
1920 
         hburst     => HBURST_S13,
1921 
         hprot      => HPROT_S13,
1922 
         -- Output
1923 
         hrdata     => HRDATA_S13,
1924 
         hresp      => HRESP_S13(0),
1925 
         hreadyout  => HREADY_S13
1926 
      );
1927 
 
1928 
 
1929 
 
1930 
   slave14 : BFM_AHBSLAVE
1931 
      generic map (
1932 
         awidth    => 16,
1933 
         depth     => 65536,
1934 
         initfile  => " ",
1935 
         id        => 1,
1936 
         enfunc    => 0,
1937 
         tpd       => 5,
1938 
         debug     => 0
1939 
      )
1940 
      port map (
1941 
         -- MP7Bridge interface
1942 
         -- Inputs
1943 
         hclk       => HCLK,
1944 
         hresetn    => HRESETN,
1945 
         -- AhbFabric interface
1946 
         -- Inputs
1947 
         hwrite     => HWRITE_S14,
1948 
         hsize      => HSIZE_S14,
1949 
         htrans     => HTRANS_S14,
1950 
         hwdata     => HWDATA_S14,
1951 
         hreadyin   => HREADYIN_S14,
1952 
         hsel       => HSEL_S14,
1953 
         haddr      => HADDR_S14(15 downto 0),
1954 
         hmastlock  => '0',
1955 
         hburst     => HBURST_S14,
1956 
         hprot      => HPROT_S14,
1957 
         -- Output
1958 
         hrdata     => HRDATA_S14,
1959 
         hresp      => HRESP_S14(0),
1960 
         hreadyout  => HREADY_S14
1961 
      );
1962 
 
1963 
 
1964 
 
1965 
   slave15 : BFM_AHBSLAVE
1966 
      generic map (
1967 
         awidth    => 16,
1968 
         depth     => 65536,
1969 
         initfile  => " ",
1970 
         id        => 1,
1971 
         enfunc    => 0,
1972 
         tpd       => 5,
1973 
         debug     => 0
1974 
      )
1975 
      port map (
1976 
         -- MP7Bridge interface
1977 
         -- Inputs
1978 
         hclk       => HCLK,
1979 
         hresetn    => HRESETN,
1980 
         -- AhbFabric interface
1981 
         -- Inputs
1982 
         hwrite     => HWRITE_S15,
1983 
         hsize      => HSIZE_S15,
1984 
         htrans     => HTRANS_S15,
1985 
         hwdata     => HWDATA_S15,
1986 
         hreadyin   => HREADYIN_S15,
1987 
         hsel       => HSEL_S15,
1988 
         haddr      => HADDR_S15(15 downto 0),
1989 
         hmastlock  => '0',
1990 
         hburst     => HBURST_S15,
1991 
         hprot      => HPROT_S15,
1992 
         -- Output
1993 
         hrdata     => HRDATA_S15,
1994 
         hresp      => HRESP_S15(0),
1995 
         hreadyout  => HREADY_S15
1996 
      );
1997 
 
1998 
 
1999 
        -- may need to make this bigger for 'huge' slave
2000 
   slave16 : BFM_AHBSLAVE
2001 
      generic map (
2002 
         awidth    => 16,
2003 
         depth     => 65536,
2004 
         initfile  => " ",
2005 
         id        => 1,
2006 
         enfunc    => 0,
2007 
         tpd       => 5,
2008 
         debug     => 0
2009 
      )
2010 
      port map (
2011 
         -- MP7Bridge interface
2012 
         -- Inputs
2013 
         hclk       => HCLK,
2014 
         hresetn    => HRESETN,
2015 
         -- AhbFabric interface
2016 
         -- Inputs
2017 
         hwrite     => HWRITE_S16,
2018 
         hsize      => HSIZE_S16,
2019 
         htrans     => HTRANS_S16,
2020 
         hwdata     => HWDATA_S16,
2021 
         hreadyin   => HREADYIN_S16,
2022 
         hsel       => HSEL_S16,
2023 
         haddr      => HADDR_S16(15 downto 0),
2024 
         hmastlock  => '0',
2025 
         hburst     => HBURST_S16,
2026 
         hprot      => HPROT_S16,
2027 
         -- Output
2028 
         hrdata     => HRDATA_S16,
2029 
         hresp      => HRESP_S16(0),
2030 
         hreadyout  => HREADY_S16
2031 
      );
2032 
 
2033 
    -----------------------------------------------------------------------
2034 
    -- Detect writes to individual slots
2035 
    -----------------------------------------------------------------------
2036 
    process (HCLK, HRESETN)
2037 
    begin
2038 
        if (HRESETN = '0') then
2039 
            s0_write  <= '0';
2040 
            s1_write  <= '0';
2041 
            s2_write  <= '0';
2042 
            s3_write  <= '0';
2043 
            s4_write  <= '0';
2044 
            s5_write  <= '0';
2045 
            s6_write  <= '0';
2046 
            s7_write  <= '0';
2047 
            s8_write  <= '0';
2048 
            s9_write  <= '0';
2049 
            s10_write <= '0';
2050 
            s11_write <= '0';
2051 
            s12_write <= '0';
2052 
            s13_write <= '0';
2053 
            s14_write <= '0';
2054 
            s15_write <= '0';
2055 
            s16_write <= '0';
2056 
        elsif (HCLK'event and HCLK = '1') then
2057 
            -- Set write indication bits
2058 
            if (HSEL_S0  = '1' and HTRANS_S0(1)  = '1' and HWRITE_S0  = '1') then s0_write  <= '1'; end if;
2059 
            if (HSEL_S1  = '1' and HTRANS_S1(1)  = '1' and HWRITE_S1  = '1') then s1_write  <= '1'; end if;
2060 
            if (HSEL_S2  = '1' and HTRANS_S2(1)  = '1' and HWRITE_S2  = '1') then s2_write  <= '1'; end if;
2061 
            if (HSEL_S3  = '1' and HTRANS_S3(1)  = '1' and HWRITE_S3  = '1') then s3_write  <= '1'; end if;
2062 
            if (HSEL_S4  = '1' and HTRANS_S4(1)  = '1' and HWRITE_S4  = '1') then s4_write  <= '1'; end if;
2063 
            if (HSEL_S5  = '1' and HTRANS_S5(1)  = '1' and HWRITE_S5  = '1') then s5_write  <= '1'; end if;
2064 
            if (HSEL_S6  = '1' and HTRANS_S6(1)  = '1' and HWRITE_S6  = '1') then s6_write  <= '1'; end if;
2065 
            if (HSEL_S7  = '1' and HTRANS_S7(1)  = '1' and HWRITE_S7  = '1') then s7_write  <= '1'; end if;
2066 
            if (HSEL_S8  = '1' and HTRANS_S8(1)  = '1' and HWRITE_S8  = '1') then s8_write  <= '1'; end if;
2067 
            if (HSEL_S9  = '1' and HTRANS_S9(1)  = '1' and HWRITE_S9  = '1') then s9_write  <= '1'; end if;
2068 
            if (HSEL_S10 = '1' and HTRANS_S10(1) = '1' and HWRITE_S10 = '1') then s10_write <= '1'; end if;
2069 
            if (HSEL_S11 = '1' and HTRANS_S11(1) = '1' and HWRITE_S11 = '1') then s11_write <= '1'; end if;
2070 
            if (HSEL_S12 = '1' and HTRANS_S12(1) = '1' and HWRITE_S12 = '1') then s12_write <= '1'; end if;
2071 
            if (HSEL_S13 = '1' and HTRANS_S13(1) = '1' and HWRITE_S13 = '1') then s13_write <= '1'; end if;
2072 
            if (HSEL_S14 = '1' and HTRANS_S14(1) = '1' and HWRITE_S14 = '1') then s14_write <= '1'; end if;
2073 
            if (HSEL_S15 = '1' and HTRANS_S15(1) = '1' and HWRITE_S15 = '1') then s15_write <= '1'; end if;
2074 
            if (HSEL_S16 = '1' and HTRANS_S16(1) = '1' and HWRITE_S16 = '1') then s16_write <= '1'; end if;
2075 
            -- Clear write indication bits
2076 
            if (GP_OUT_M0(0)  = '1') then s0_write  <= '0'; end if;
2077 
            if (GP_OUT_M0(1)  = '1') then s1_write  <= '0'; end if;
2078 
            if (GP_OUT_M0(2)  = '1') then s2_write  <= '0'; end if;
2079 
            if (GP_OUT_M0(3)  = '1') then s3_write  <= '0'; end if;
2080 
            if (GP_OUT_M0(4)  = '1') then s4_write  <= '0'; end if;
2081 
            if (GP_OUT_M0(5)  = '1') then s5_write  <= '0'; end if;
2082 
            if (GP_OUT_M0(6)  = '1') then s6_write  <= '0'; end if;
2083 
            if (GP_OUT_M0(7)  = '1') then s7_write  <= '0'; end if;
2084 
            if (GP_OUT_M0(8)  = '1') then s8_write  <= '0'; end if;
2085 
            if (GP_OUT_M0(9)  = '1') then s9_write  <= '0'; end if;
2086 
            if (GP_OUT_M0(10) = '1') then s10_write <= '0'; end if;
2087 
            if (GP_OUT_M0(11) = '1') then s11_write <= '0'; end if;
2088 
            if (GP_OUT_M0(12) = '1') then s12_write <= '0'; end if;
2089 
            if (GP_OUT_M0(13) = '1') then s13_write <= '0'; end if;
2090 
            if (GP_OUT_M0(14) = '1') then s14_write <= '0'; end if;
2091 
            if (GP_OUT_M0(15) = '1') then s15_write <= '0'; end if;
2092 
            if (GP_OUT_M0(16) = '1') then s16_write <= '0'; end if;
2093 
        end if;
2094 
    end process;
2095 
 
2096 
end architecture testbench_arch;

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