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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreUARTapb_0/] [rtl/] [vhdl/] [core/] [CoreUART.vhd] - Blame information for rev 3

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-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
--  Copyright 2008 Actel Corporation.  All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: top_CoreUARTapb_0_COREUART/ CoreUARTapb UART core
--
--
--  Revision Information:
-- Date     Description
-- Jun09    Revision 4.1
-- Aug10    Revision 4.2
 
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR      Date     Who   Description
-- 20741    2Sep10   AS    Increased baud rate by ensuring fifo ctrl runs off
--                         sys clk (not baud clock).  See note below.
 
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
use work.top_CoreUARTapb_0_coreuart_pkg.all;
 
ENTITY top_CoreUARTapb_0_COREUART IS
   GENERIC (
      FAMILY                         :  INTEGER := 15;    -- DEVICE FAMILY
      -- TX PARAMETERS
      TX_FIFO                        :  INTEGER := 0;     -- 0=WITHOUT TX FIFO, 1=WITH TX FIFO
      -- RX PARAMETERS
      RX_FIFO                        :  INTEGER := 0;     -- 0=WITHOUT RX FIFO, 1=WITH RX FIFO
      RX_LEGACY_MODE                 :  INTEGER := 0;
      --BAUD FRACTION PARAMETER
      BAUD_VAL_FRCTN_EN              :  INTEGER := 0     -- 0=DISABLE BAUD FRACTION, 1=ENABLE BAUD FRACTION
      );
   PORT (
      RESET_N                 : IN STD_LOGIC;
      CLK                     : IN STD_LOGIC;
      WEN                     : IN STD_LOGIC;
      OEN                     : IN STD_LOGIC;
      CSN                     : IN STD_LOGIC;
      DATA_IN                 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      RX                      : IN STD_LOGIC;
      BAUD_VAL                : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
      BIT8                    : IN STD_LOGIC;   --   IF SET TO ONE 8 DATA BITS OTHERWISE 7 DATA BITS
      PARITY_EN               : IN STD_LOGIC;   --   IF SET TO ONE PARITY IS ENABLED OTHERWISE DISABLED
      ODD_N_EVEN              : IN STD_LOGIC;   --   IF SET TO ONE ODD PARITY OTHERWISE EVEN PARITY
      BAUD_VAL_FRACTION       : IN STD_LOGIC_VECTOR(2 DOWNTO 0);  --USED TO ADD EXTRA PRECISION TO BAUD VALUE WHEN BAUD_VAL_FRCTN_EN = 1
      PARITY_ERR              : OUT STD_LOGIC;   --   PARITY ERROR INDICATOR ON RECIEVED DATA
      OVERFLOW                : OUT STD_LOGIC;   --   RECEIVER OVERFLOW
      TXRDY                   : OUT STD_LOGIC;   --   TRANSMIT READY FOR ANOTHER BYTE
      RXRDY                   : OUT STD_LOGIC;   --   RECEIVER HAS A BYTE READY
      DATA_OUT                : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      TX                      : OUT STD_LOGIC;
      FRAMING_ERR             : OUT STD_LOGIC);
END ENTITY top_CoreUARTapb_0_COREUART;
 
ARCHITECTURE translated OF top_CoreUARTapb_0_COREUART IS
 
   -- State name constant definitions
   CONSTANT S0  : std_logic_vector(1 DOWNTO 0) := "00";
   CONSTANT S1  : std_logic_vector(1 DOWNTO 0) := "01";
   CONSTANT S2  : std_logic_vector(1 DOWNTO 0) := "10";
   CONSTANT S3  : std_logic_vector(1 DOWNTO 0) := "11";
 
  -- Sync/Async Mode Select
  CONSTANT SYNC_RESET : INTEGER := SYNC_MODE_SEL(FAMILY);
 
   --  Configuration bits
   --  Status bits
   SIGNAL overflow_legacy          :  std_logic;
   SIGNAL receive_full             :  std_logic;
   SIGNAL fifo_write_rx            :  std_logic;
   SIGNAL fifo_write               :  std_logic;
   SIGNAL xmit_pulse               :  std_logic;   --   transmit pulse
   SIGNAL baud_clock               :  std_logic;   --   8x baud clock pulse
   SIGNAL rst_tx_empty             :  std_logic;   --   reset transmit empty
   SIGNAL tx_hold_reg              :  std_logic_vector(7 DOWNTO 0);   --   transmit byte hold register
   SIGNAL tx_dout_reg              :  std_logic_vector(7 DOWNTO 0);   --   transmit byte hold register
   SIGNAL rx_dout                  :  std_logic_vector(7 DOWNTO 0);   --   receive data out
   SIGNAL read_rx_byte             :  std_logic;   --   read rx byte register
   SIGNAL rx_dout_reg              :  std_logic_vector(7 DOWNTO 0);   --   receive data out
   SIGNAL rx_byte                  :  std_logic_vector(7 DOWNTO 0);   --   receive byte register
   SIGNAL rx_byte_in               :  std_logic_vector(7 DOWNTO 0);   --   receive byte register
   SIGNAL fifo_empty_tx            :  std_logic;
   SIGNAL fifo_empty_rx            :  std_logic;
   SIGNAL fifo_read_rx             :  std_logic;
   SIGNAL fifo_write_tx            :  std_logic;
   SIGNAL fifo_read_tx             :  std_logic;
   SIGNAL fifo_full_tx             :  std_logic;
   SIGNAL fifo_full_rx             :  std_logic;
   SIGNAL clear_parity             :  std_logic;
   SIGNAL clear_parity_en          :  std_logic;
   SIGNAL clear_parity_reg0        :  std_logic;
   SIGNAL clear_parity_reg         :  std_logic;
   SIGNAL data_en                  :  std_logic;
   SIGNAL stop_strobe              :  std_logic;
   SIGNAL clear_framing_error      :  std_logic;
   -- AS: added framing error self-clear mechanism (RX FIFO mode)
   SIGNAL clear_framing_error_en   :  std_logic;
   SIGNAL clear_framing_error_reg0 :  std_logic;
   SIGNAL clear_framing_error_reg  :  std_logic;
   signal rx_idle                  :  std_logic;    -- AS: Added this signal for proper framing_error sync
   SIGNAL framing_err_i            :  std_logic;    -- AS: Internal framing error, for reading
   -- AS: Added changed overflow operation (new signals required - see below)
   SIGNAL overflow_reg             :  std_logic;
   SIGNAL clear_overflow           :  std_logic;
   -- ----------------------------------------------------------------------------
   --  cpu reads from UART registers
   -- ----------------------------------------------------------------------------
   SIGNAL temp_xhdl7               :  std_logic;
   SIGNAL temp_xhdl10              :  std_logic;
   SIGNAL temp_xhdl11              :  std_logic;
   SIGNAL temp_xhdl12              :  std_logic;
   SIGNAL temp_xhdl13              :  std_logic;
   SIGNAL temp_xhdl14              :  std_logic_vector(7 DOWNTO 0);
   SIGNAL temp_xhdl16              :  std_logic;
   SIGNAL temp_xhdl17              :  std_logic;
   SIGNAL parity_err_xhdl1         :  std_logic;
   SIGNAL overflow_xhdl2           :  std_logic;
   SIGNAL txrdy_xhdl3              :  std_logic;
   SIGNAL rxrdy_xhdl4              :  std_logic;
   SIGNAL data_out_xhdl5           :  std_logic_vector(7 DOWNTO 0);
   SIGNAL tx_xhdl6                 :  std_logic;
 
   SIGNAL rx_dout_reg_empty        :  std_logic;
   SIGNAL rx_state                 :  std_logic_vector(1 DOWNTO 0);
   SIGNAL next_rx_state            :  std_logic_vector(1 DOWNTO 0);
   SIGNAL aresetn  : std_logic;
   SIGNAL sresetn  : std_logic;
 
   COMPONENT top_CoreUARTapb_0_Rx_async
      GENERIC (
         -- RX Parameters
         RX_FIFO    :  integer := 0;  --  0=without rx fifo   
                 SYNC_RESET :  integer := 0);
      PORT (
         clk                     : IN  std_logic;
         baud_clock              : IN  std_logic;
         reset_n                 : IN  std_logic;
         bit8                    : IN  std_logic;
         parity_en               : IN  std_logic;
         odd_n_even              : IN  std_logic;
         read_rx_byte            : IN  std_logic;
         clear_parity            : IN  std_logic;
         clear_framing_error     : IN  std_logic;
         rx                      : IN  std_logic;
         overflow                : OUT std_logic;
         parity_err              : OUT std_logic;
         framing_error           : OUT std_logic;
         rx_idle_out             : OUT std_logic;       -- AS: added this signal to sync framing error properly
         stop_strobe             : OUT std_logic;
         clear_parity_en         : OUT std_logic;
         clear_framing_error_en  : OUT std_logic;
         receive_full            : OUT std_logic;
         rx_byte                 : OUT std_logic_vector(7 DOWNTO 0);
         fifo_write              : OUT std_logic
    );
   END COMPONENT;
 
 
   COMPONENT top_CoreUARTapb_0_Tx_async
      GENERIC (
         -- TX Parameters
         TX_FIFO    :  integer := 0;    --  0=without tx fifo
                 SYNC_RESET :  integer := 0);
      PORT (
         clk                     : IN  std_logic;
         xmit_pulse              : IN  std_logic;
         reset_n                 : IN  std_logic;
         rst_tx_empty            : IN  std_logic;
         tx_hold_reg             : IN  std_logic_vector(7 DOWNTO 0);
         tx_dout_reg             : IN  std_logic_vector(7 DOWNTO 0);
         fifo_empty              : IN  std_logic;
         fifo_full               : IN  std_logic;
         bit8                    : IN  std_logic;
         parity_en               : IN  std_logic;
         odd_n_even              : IN  std_logic;
         txrdy                   : OUT std_logic;
         tx                      : OUT std_logic;
         fifo_read_tx            : OUT std_logic);
   END COMPONENT;
 
 
   COMPONENT top_CoreUARTapb_0_Clock_gen
      GENERIC(
        --BAUD FRACTION Parameter
        BAUD_VAL_FRCTN_EN              :  integer := 0; -- 0=disable baud fraction  
                SYNC_RESET                     :  integer := 0);
      port (
             clk                : in   std_logic;                      -- system clock
             reset_n            : in   std_logic;                      -- active low async reset
             baud_val           : in   std_logic_vector(12 downto 0);  -- value loaded into cntr
             BAUD_VAL_FRACTION  : in   std_logic_vector(2 downto 0);   -- handles fractional part of baud value 
 
             baud_clock         : out  std_logic;                      -- 8x baud clock pulse
             xmit_pulse         : out  std_logic                       -- transmit pulse
            );
   END COMPONENT;
 
   COMPONENT top_CoreUARTapb_0_fifo_256x8 IS
   GENERIC ( SYNC_RESET :  integer := 0);
    PORT (
      DO                      : OUT std_logic_vector(7 DOWNTO 0);
      RCLOCK                  : IN std_logic;
      WCLOCK                  : IN std_logic;
      DI                      : IN std_logic_vector(7 DOWNTO 0);
      WRB                     : IN std_logic;
      RDB                     : IN std_logic;
      RESET                   : IN std_logic;
      FULL                    : OUT std_logic;
      EMPTY                   : OUT std_logic);
   END COMPONENT;
 
BEGIN
   aresetn <= '1' WHEN (SYNC_RESET=1) ELSE RESET_N;
   sresetn <= RESET_N WHEN (SYNC_RESET=1) ELSE '1';
   FRAMING_ERR <= framing_err_i;
   PARITY_ERR <= parity_err_xhdl1;
   OVERFLOW <= overflow_xhdl2;
   TXRDY <= txrdy_xhdl3;
   RXRDY <= rxrdy_xhdl4;
   DATA_OUT <= data_out_xhdl5;
   TX <= tx_xhdl6;
 
 
   -- ---------------------------------------------------------
   --  COMPONENT DECLARATIONS
   -- ---------------------------------------------------------
   -- ----------------------------------------------------------------------------
   --  cpu writes to UART registers
   -- ----------------------------------------------------------------------------
 
   reg_write : PROCESS (CLK, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         tx_hold_reg <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
         fifo_write_tx <= '1';
      ELSIF (CLK'EVENT AND CLK = '1') THEN
          IF (sresetn = '0') THEN
             tx_hold_reg <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
             fifo_write_tx <= '1';
          ELSE
             fifo_write_tx <= '1';
             IF (csn = '0' AND WEn = '0') THEN
                tx_hold_reg <= DATA_IN;
                fifo_write_tx <= '0';
             END IF;
          END IF;
      END IF;
   END PROCESS reg_write;
   temp_xhdl7 <= '1' WHEN (WEn = '0' AND csn = '0') ELSE '0';
   rst_tx_empty <= temp_xhdl7 ;
 
 
   PROCESS (rx_byte, rx_dout_reg, parity_err_xhdl1)
   VARIABLE data_out_xhdl5_xhdl8  : std_logic_vector(7 DOWNTO 0);
   BEGIN
       IF (RX_FIFO = 2#0#) THEN
           data_out_xhdl5_xhdl8 := rx_byte;
       ELSE
           IF (parity_err_xhdl1 = '1') THEN
               data_out_xhdl5_xhdl8 := rx_byte;
           ELSE
               data_out_xhdl5_xhdl8 := rx_dout_reg;
           END IF;
       END IF;
       data_out_xhdl5 <= data_out_xhdl5_xhdl8;
   END PROCESS;
 
 
   temp_xhdl10 <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';
   temp_xhdl11 <= (temp_xhdl10) WHEN (RX_FIFO = 2#0#) ELSE NOT fifo_full_rx;
   read_rx_byte <= temp_xhdl11 ;
   temp_xhdl12 <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';
   temp_xhdl13 <= clear_parity_reg WHEN RX_FIFO /= 0 ELSE (temp_xhdl12);
   clear_parity <= temp_xhdl13 ;
   temp_xhdl14 <= rx_byte WHEN (parity_err_xhdl1 = '0') ELSE "00000000";
   rx_byte_in <= temp_xhdl14 ;
   --clear_framing_error <= clear_framing_error_reg WHEN RX_FIFO /= 0 ELSE (temp_xhdl12);
   clear_framing_error <= temp_xhdl12 WHEN (RX_FIFO = 0) ELSE '1' WHEN (temp_xhdl12 = '1') ELSE clear_framing_error_reg;
   clear_overflow <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';
 
 
   RXRDY_LEGACY: IF (RX_LEGACY_MODE = 1) GENERATE
     PROCESS (receive_full, rx_dout_reg_empty)
       VARIABLE rxrdy_xhdl4_xhdl15  : std_logic;
     BEGIN
       IF (RX_FIFO = 2#0#) THEN
         rxrdy_xhdl4_xhdl15 := receive_full;
       ELSE
         rxrdy_xhdl4_xhdl15 := NOT rx_dout_reg_empty;
       END IF;
       rxrdy_xhdl4 <= rxrdy_xhdl4_xhdl15;
     END PROCESS;
   END GENERATE;
 
   -- AS, added 11/17/08
   RXRDY_NEW: IF (RX_LEGACY_MODE = 0) GENERATE
    PROCESS (CLK, aresetn)
    BEGIN
      IF (aresetn = '0') THEN
        rxrdy_xhdl4 <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
        IF (sresetn = '0') THEN
          rxrdy_xhdl4 <= '0';
            ELSE
          IF (RX_FIFO = 0) THEN
            IF (stop_strobe = '1' OR receive_full = '0') THEN
              rxrdy_xhdl4 <= receive_full;
            END IF;
          ELSE
                    IF (stop_strobe = '1' OR rx_dout_reg_empty = '1' or (rx_dout_reg_empty = '0' and (rx_idle = '1' or RX_FIFO = 1))) THEN
              rxrdy_xhdl4 <= NOT rx_dout_reg_empty;
            END IF;
          END IF;
        END IF;
      END IF;
    END PROCESS;
   END GENERATE;
 
   PROCESS (CLK, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         clear_parity_reg <= '0';
         clear_parity_reg0 <= '0';
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (sresetn = '0') THEN
            clear_parity_reg <= '0';
            clear_parity_reg0 <= '0';
             ELSE
            clear_parity_reg0 <= clear_parity_en;
            clear_parity_reg <= clear_parity_reg0;
         END IF;
      END IF;
   END PROCESS;
 
   -- AS: added self-clearing framing error
   PROCESS (CLK, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         clear_framing_error_reg <= '0';
         clear_framing_error_reg0 <= '0';
      ELSIF (CLK'EVENT AND CLK = '1') THEN
          IF (sresetn = '0') THEN
             clear_framing_error_reg <= '0';
             clear_framing_error_reg0 <= '0';
              ELSE
             clear_framing_error_reg0 <= clear_framing_error_en;
             clear_framing_error_reg <= clear_framing_error_reg0;
          END IF;
      END IF;
   END PROCESS;
 
   -- state machine to control reading from the rx fifo
   PROCESS (CLK, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         rx_state <= S0;
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (sresetn = '0') THEN
            rx_state <= S0;
             ELSE
            rx_state <= next_rx_state;
         END IF;
      END IF;
   END PROCESS;
 
   PROCESS (rx_state, rx_dout_reg_empty, fifo_empty_rx)
   BEGIN
      next_rx_state <= rx_state;
      fifo_read_rx <= '1';
      data_en <= '0';
      CASE rx_state IS
         WHEN S0 => IF (rx_dout_reg_empty = '1' AND fifo_empty_rx = '0') THEN
                                                        next_rx_state <= S1;
                                                        fifo_read_rx <= '0';
                    END IF;
         WHEN S1 => next_rx_state <= S2;
         WHEN S2 => next_rx_state <= S3;
         WHEN S3 => next_rx_state <= S0;
                    data_en <= '1';
         WHEN others => next_rx_state <= rx_state;
      END CASE;
   END PROCESS;
 
 
   PROCESS (CLK, aresetn)
   BEGIN
      IF (aresetn = '0') THEN
         rx_dout_reg <= "00000000";
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (sresetn = '0') THEN
            rx_dout_reg <= "00000000";
             ELSE
            IF (data_en = '1') THEN
                rx_dout_reg <= rx_dout;
            END IF;
         END IF;
      END IF;
   END PROCESS;
 
   PROCESS (CLK, aresetn)
   BEGIN
       IF (aresetn = '0') THEN
           rx_dout_reg_empty <= '1';
       ELSIF (CLK'EVENT AND CLK = '1') THEN
           IF (sresetn = '0') THEN
               rx_dout_reg_empty <= '1';
               ELSE
               IF (data_en = '1') THEN
                   rx_dout_reg_empty <= '0';
               ELSE
                   IF (csn = '0' AND OEn = '0') THEN
                               IF (RX_FIFO = 1) THEN
                                   IF(parity_err_xhdl1 = '0') THEN
                                       rx_dout_reg_empty <= '1';
                                   END IF;
                                   ELSE
                                   rx_dout_reg_empty <= '1';
                                   END IF;
                   END IF;
               END IF;
           END IF;
       END IF;
   END PROCESS;
 
   PROCESS (CLK, aresetn)
   BEGIN
       IF (aresetn = '0') THEN
         overflow_reg <= '0';
       ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (sresetn = '0') THEN
           overflow_reg <= '0';
             ELSE
           IF (fifo_write = '0' AND fifo_full_rx = '1') THEN
             overflow_reg <= '1';
           ELSIF (clear_overflow = '1') THEN
             overflow_reg <= '0';
           ELSE
             overflow_reg <= overflow_reg;
           END IF;
         END IF;
       END IF;
   END PROCESS;
-- AS: Changed OVERFLOW condition
--     - We should not be assigning OVERFLOW to FIFO_FULL;
--       instead, we should be asserting OVERFLOW if a write is
--       requested while fifo_full_rx is high
   temp_xhdl16 <= overflow_reg WHEN RX_FIFO /= 0 ELSE overflow_legacy;
   overflow_xhdl2 <= temp_xhdl16 ;
 
   temp_xhdl17 <= '1' WHEN (parity_err_xhdl1 = '1' or fifo_full_rx = '1') ELSE fifo_write;
 
   fifo_write_rx <= temp_xhdl17 ;
 
      make_top_CoreUARTapb_0_Clock_gen : top_CoreUARTapb_0_Clock_gen
          GENERIC MAP (
            BAUD_VAL_FRCTN_EN => BAUD_VAL_FRCTN_EN,
                        SYNC_RESET => SYNC_RESET)
         PORT MAP (
            clk => CLK,
            reset_n => RESET_N,
            baud_val => BAUD_VAL,
            BAUD_VAL_FRACTION => BAUD_VAL_FRACTION,
            baud_clock => baud_clock,
            xmit_pulse => xmit_pulse);
 
      make_TX : top_CoreUARTapb_0_Tx_async
         GENERIC MAP (
            TX_FIFO => TX_FIFO,
                        SYNC_RESET => SYNC_RESET)
         PORT MAP (
            clk => CLK,
            xmit_pulse => xmit_pulse,
            reset_n => RESET_N,
            rst_tx_empty => rst_tx_empty,
            tx_hold_reg => tx_hold_reg,
            tx_dout_reg => tx_dout_reg,
            fifo_empty => fifo_empty_tx,
            fifo_full => fifo_full_tx,
            bit8 => bit8,
            parity_en => parity_en,
            odd_n_even => odd_n_even,
            txrdy => txrdy_xhdl3,
            tx => tx_xhdl6,
            fifo_read_tx => fifo_read_tx);
 
      make_RX : top_CoreUARTapb_0_Rx_async
         GENERIC MAP (
            RX_FIFO => RX_FIFO,
                        SYNC_RESET => SYNC_RESET)
         PORT MAP (
            clk => CLK,
            baud_clock => baud_clock,
            reset_n => RESET_N,
            bit8 => bit8,
            parity_en => parity_en,
            odd_n_even => odd_n_even,
            read_rx_byte => read_rx_byte,
            clear_parity => clear_parity,
            rx => RX,
            overflow => overflow_legacy,
            parity_err => parity_err_xhdl1,
            clear_parity_en => clear_parity_en,
            receive_full => receive_full,
            rx_byte => rx_byte,
            fifo_write => fifo_write,
            clear_framing_error => clear_framing_error,
            clear_framing_error_en => clear_framing_error_en,
            framing_error => framing_err_i,
            rx_idle_out => rx_idle,
            stop_strobe => stop_strobe);
 
   UG06a:IF (TX_FIFO = 2#1#) GENERATE
      tx_fifo_xhdl79 : top_CoreUARTapb_0_fifo_256x8
         GENERIC MAP ( SYNC_RESET => SYNC_RESET)
         PORT MAP (
            DO => tx_dout_reg,
            RCLOCK => clk,
            WCLOCK => clk,
-- AS: FIXED SARno 12821
--            DI => data_in,
            DI => tx_hold_reg,
            WRB => fifo_write_tx,
            RDB => fifo_read_tx,
            RESET => reset_n,
            FULL => fifo_full_tx,
            EMPTY => fifo_empty_tx);
   END GENERATE;
 
   UG06b:IF (TX_FIFO = 2#0#) GENERATE
             tx_dout_reg <= "00000000";
             fifo_full_tx <='0';
             fifo_empty_tx <='0';
   END GENERATE;
 
   UG07:IF (RX_FIFO = 2#1#) GENERATE
      rx_fifo_xhdl80 : top_CoreUARTapb_0_fifo_256x8
         GENERIC MAP ( SYNC_RESET => SYNC_RESET)
         PORT MAP (
            DO => rx_dout,
            RCLOCK => clk,
            WCLOCK => clk,
            DI => rx_byte_in,
            WRB => fifo_write_rx,
            RDB => fifo_read_rx,
            RESET => reset_n,
            FULL => fifo_full_rx,
            EMPTY => fifo_empty_rx);
   END GENERATE;
 
   UG07b:IF (RX_FIFO = 2#0#) GENERATE
             rx_dout <= "00000000";
             fifo_full_rx <='0';
             fifo_empty_rx <='0';
   END GENERATE;
 
END ARCHITECTURE translated;

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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreUARTapb_0/] [rtl/] [vhdl/] [core/] [CoreUART.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	uson	`-- ********************************************************************`
2			`-- Actel Corporation Proprietary and Confidential`
3			`-- Copyright 2008 Actel Corporation. All rights reserved.`
4			`--`
5			`-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN`
6			`-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED`
7			`-- IN ADVANCE IN WRITING.`
8			`--`
9			`-- Description: top_CoreUARTapb_0_COREUART/ CoreUARTapb UART core`
10			`--`
11			`--`
12			`-- Revision Information:`
13			`-- Date Description`
14			`-- Jun09 Revision 4.1`
15			`-- Aug10 Revision 4.2`
16
17			`-- SVN Revision Information:`
18			`-- SVN $Revision: 8508 $`
19			`-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $`
20			`--`
21			`-- Resolved SARs`
22			`-- SAR Date Who Description`
23			`-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off`
24			`-- sys clk (not baud clock). See note below.`
25
26			`-- Notes:`
27			`-- best viewed with tabstops set to "4"`
28			`LIBRARY IEEE;`
29			`USE IEEE.std_logic_1164.all;`
30			`USE IEEE.std_logic_arith.all;`
31			`USE IEEE.std_logic_unsigned.all;`
32			`use work.top_CoreUARTapb_0_coreuart_pkg.all;`
33
34			`ENTITY top_CoreUARTapb_0_COREUART IS`
35			`GENERIC (`
36			`FAMILY : INTEGER := 15; -- DEVICE FAMILY`
37			`-- TX PARAMETERS`
38			`TX_FIFO : INTEGER := 0; -- 0=WITHOUT TX FIFO, 1=WITH TX FIFO`
39			`-- RX PARAMETERS`
40			`RX_FIFO : INTEGER := 0; -- 0=WITHOUT RX FIFO, 1=WITH RX FIFO`
41			`RX_LEGACY_MODE : INTEGER := 0;`
42			`--BAUD FRACTION PARAMETER`
43			`BAUD_VAL_FRCTN_EN : INTEGER := 0 -- 0=DISABLE BAUD FRACTION, 1=ENABLE BAUD FRACTION`
44			`);`
45			`PORT (`
46			`RESET_N : IN STD_LOGIC;`
47			`CLK : IN STD_LOGIC;`
48			`WEN : IN STD_LOGIC;`
49			`OEN : IN STD_LOGIC;`
50			`CSN : IN STD_LOGIC;`
51			`DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
52			`RX : IN STD_LOGIC;`
53			`BAUD_VAL : IN STD_LOGIC_VECTOR(12 DOWNTO 0);`
54			`BIT8 : IN STD_LOGIC; -- IF SET TO ONE 8 DATA BITS OTHERWISE 7 DATA BITS`
55			`PARITY_EN : IN STD_LOGIC; -- IF SET TO ONE PARITY IS ENABLED OTHERWISE DISABLED`
56			`ODD_N_EVEN : IN STD_LOGIC; -- IF SET TO ONE ODD PARITY OTHERWISE EVEN PARITY`
57			`BAUD_VAL_FRACTION : IN STD_LOGIC_VECTOR(2 DOWNTO 0); --USED TO ADD EXTRA PRECISION TO BAUD VALUE WHEN BAUD_VAL_FRCTN_EN = 1`
58			`PARITY_ERR : OUT STD_LOGIC; -- PARITY ERROR INDICATOR ON RECIEVED DATA`
59			`OVERFLOW : OUT STD_LOGIC; -- RECEIVER OVERFLOW`
60			`TXRDY : OUT STD_LOGIC; -- TRANSMIT READY FOR ANOTHER BYTE`
61			`RXRDY : OUT STD_LOGIC; -- RECEIVER HAS A BYTE READY`
62			`DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
63			`TX : OUT STD_LOGIC;`
64			`FRAMING_ERR : OUT STD_LOGIC);`
65			`END ENTITY top_CoreUARTapb_0_COREUART;`
66
67			`ARCHITECTURE translated OF top_CoreUARTapb_0_COREUART IS`
68
69			`-- State name constant definitions`
70			`CONSTANT S0 : std_logic_vector(1 DOWNTO 0) := "00";`
71			`CONSTANT S1 : std_logic_vector(1 DOWNTO 0) := "01";`
72			`CONSTANT S2 : std_logic_vector(1 DOWNTO 0) := "10";`
73			`CONSTANT S3 : std_logic_vector(1 DOWNTO 0) := "11";`
74
75			`-- Sync/Async Mode Select`
76			`CONSTANT SYNC_RESET : INTEGER := SYNC_MODE_SEL(FAMILY);`
77
78			`-- Configuration bits`
79			`-- Status bits`
80			`SIGNAL overflow_legacy : std_logic;`
81			`SIGNAL receive_full : std_logic;`
82			`SIGNAL fifo_write_rx : std_logic;`
83			`SIGNAL fifo_write : std_logic;`
84			`SIGNAL xmit_pulse : std_logic; -- transmit pulse`
85			`SIGNAL baud_clock : std_logic; -- 8x baud clock pulse`
86			`SIGNAL rst_tx_empty : std_logic; -- reset transmit empty`
87			`SIGNAL tx_hold_reg : std_logic_vector(7 DOWNTO 0); -- transmit byte hold register`
88			`SIGNAL tx_dout_reg : std_logic_vector(7 DOWNTO 0); -- transmit byte hold register`
89			`SIGNAL rx_dout : std_logic_vector(7 DOWNTO 0); -- receive data out`
90			`SIGNAL read_rx_byte : std_logic; -- read rx byte register`
91			`SIGNAL rx_dout_reg : std_logic_vector(7 DOWNTO 0); -- receive data out`
92			`SIGNAL rx_byte : std_logic_vector(7 DOWNTO 0); -- receive byte register`
93			`SIGNAL rx_byte_in : std_logic_vector(7 DOWNTO 0); -- receive byte register`
94			`SIGNAL fifo_empty_tx : std_logic;`
95			`SIGNAL fifo_empty_rx : std_logic;`
96			`SIGNAL fifo_read_rx : std_logic;`
97			`SIGNAL fifo_write_tx : std_logic;`
98			`SIGNAL fifo_read_tx : std_logic;`
99			`SIGNAL fifo_full_tx : std_logic;`
100			`SIGNAL fifo_full_rx : std_logic;`
101			`SIGNAL clear_parity : std_logic;`
102			`SIGNAL clear_parity_en : std_logic;`
103			`SIGNAL clear_parity_reg0 : std_logic;`
104			`SIGNAL clear_parity_reg : std_logic;`
105			`SIGNAL data_en : std_logic;`
106			`SIGNAL stop_strobe : std_logic;`
107			`SIGNAL clear_framing_error : std_logic;`
108			`-- AS: added framing error self-clear mechanism (RX FIFO mode)`
109			`SIGNAL clear_framing_error_en : std_logic;`
110			`SIGNAL clear_framing_error_reg0 : std_logic;`
111			`SIGNAL clear_framing_error_reg : std_logic;`
112			`signal rx_idle : std_logic; -- AS: Added this signal for proper framing_error sync`
113			`SIGNAL framing_err_i : std_logic; -- AS: Internal framing error, for reading`
114			`-- AS: Added changed overflow operation (new signals required - see below)`
115			`SIGNAL overflow_reg : std_logic;`
116			`SIGNAL clear_overflow : std_logic;`
117			`-- ----------------------------------------------------------------------------`
118			`-- cpu reads from UART registers`
119			`-- ----------------------------------------------------------------------------`
120			`SIGNAL temp_xhdl7 : std_logic;`
121			`SIGNAL temp_xhdl10 : std_logic;`
122			`SIGNAL temp_xhdl11 : std_logic;`
123			`SIGNAL temp_xhdl12 : std_logic;`
124			`SIGNAL temp_xhdl13 : std_logic;`
125			`SIGNAL temp_xhdl14 : std_logic_vector(7 DOWNTO 0);`
126			`SIGNAL temp_xhdl16 : std_logic;`
127			`SIGNAL temp_xhdl17 : std_logic;`
128			`SIGNAL parity_err_xhdl1 : std_logic;`
129			`SIGNAL overflow_xhdl2 : std_logic;`
130			`SIGNAL txrdy_xhdl3 : std_logic;`
131			`SIGNAL rxrdy_xhdl4 : std_logic;`
132			`SIGNAL data_out_xhdl5 : std_logic_vector(7 DOWNTO 0);`
133			`SIGNAL tx_xhdl6 : std_logic;`
134
135			`SIGNAL rx_dout_reg_empty : std_logic;`
136			`SIGNAL rx_state : std_logic_vector(1 DOWNTO 0);`
137			`SIGNAL next_rx_state : std_logic_vector(1 DOWNTO 0);`
138			`SIGNAL aresetn : std_logic;`
139			`SIGNAL sresetn : std_logic;`
140
141			`COMPONENT top_CoreUARTapb_0_Rx_async`
142			`GENERIC (`
143			`-- RX Parameters`
144			`RX_FIFO : integer := 0; -- 0=without rx fifo`
145			`SYNC_RESET : integer := 0);`
146			`PORT (`
147			`clk : IN std_logic;`
148			`baud_clock : IN std_logic;`
149			`reset_n : IN std_logic;`
150			`bit8 : IN std_logic;`
151			`parity_en : IN std_logic;`
152			`odd_n_even : IN std_logic;`
153			`read_rx_byte : IN std_logic;`
154			`clear_parity : IN std_logic;`
155			`clear_framing_error : IN std_logic;`
156			`rx : IN std_logic;`
157			`overflow : OUT std_logic;`
158			`parity_err : OUT std_logic;`
159			`framing_error : OUT std_logic;`
160			`rx_idle_out : OUT std_logic; -- AS: added this signal to sync framing error properly`
161			`stop_strobe : OUT std_logic;`
162			`clear_parity_en : OUT std_logic;`
163			`clear_framing_error_en : OUT std_logic;`
164			`receive_full : OUT std_logic;`
165			`rx_byte : OUT std_logic_vector(7 DOWNTO 0);`
166			`fifo_write : OUT std_logic`
167			`);`
168			`END COMPONENT;`
169
170
171			`COMPONENT top_CoreUARTapb_0_Tx_async`
172			`GENERIC (`
173			`-- TX Parameters`
174			`TX_FIFO : integer := 0; -- 0=without tx fifo`
175			`SYNC_RESET : integer := 0);`
176			`PORT (`
177			`clk : IN std_logic;`
178			`xmit_pulse : IN std_logic;`
179			`reset_n : IN std_logic;`
180			`rst_tx_empty : IN std_logic;`
181			`tx_hold_reg : IN std_logic_vector(7 DOWNTO 0);`
182			`tx_dout_reg : IN std_logic_vector(7 DOWNTO 0);`
183			`fifo_empty : IN std_logic;`
184			`fifo_full : IN std_logic;`
185			`bit8 : IN std_logic;`
186			`parity_en : IN std_logic;`
187			`odd_n_even : IN std_logic;`
188			`txrdy : OUT std_logic;`
189			`tx : OUT std_logic;`
190			`fifo_read_tx : OUT std_logic);`
191			`END COMPONENT;`
192
193
194			`COMPONENT top_CoreUARTapb_0_Clock_gen`
195			`GENERIC(`
196			`--BAUD FRACTION Parameter`
197			`BAUD_VAL_FRCTN_EN : integer := 0; -- 0=disable baud fraction`
198			`SYNC_RESET : integer := 0);`
199			`port (`
200			`clk : in std_logic; -- system clock`
201			`reset_n : in std_logic; -- active low async reset`
202			`baud_val : in std_logic_vector(12 downto 0); -- value loaded into cntr`
203			`BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0); -- handles fractional part of baud value`
204
205			`baud_clock : out std_logic; -- 8x baud clock pulse`
206			`xmit_pulse : out std_logic -- transmit pulse`
207			`);`
208			`END COMPONENT;`
209
210			`COMPONENT top_CoreUARTapb_0_fifo_256x8 IS`
211			`GENERIC ( SYNC_RESET : integer := 0);`
212			`PORT (`
213			`DO : OUT std_logic_vector(7 DOWNTO 0);`
214			`RCLOCK : IN std_logic;`
215			`WCLOCK : IN std_logic;`
216			`DI : IN std_logic_vector(7 DOWNTO 0);`
217			`WRB : IN std_logic;`
218			`RDB : IN std_logic;`
219			`RESET : IN std_logic;`
220			`FULL : OUT std_logic;`
221			`EMPTY : OUT std_logic);`
222			`END COMPONENT;`
223
224			`BEGIN`
225			`aresetn <= '1' WHEN (SYNC_RESET=1) ELSE RESET_N;`
226			`sresetn <= RESET_N WHEN (SYNC_RESET=1) ELSE '1';`
227			`FRAMING_ERR <= framing_err_i;`
228			`PARITY_ERR <= parity_err_xhdl1;`
229			`OVERFLOW <= overflow_xhdl2;`
230			`TXRDY <= txrdy_xhdl3;`
231			`RXRDY <= rxrdy_xhdl4;`
232			`DATA_OUT <= data_out_xhdl5;`
233			`TX <= tx_xhdl6;`
234
235
236			`-- ---------------------------------------------------------`
237			`-- COMPONENT DECLARATIONS`
238			`-- ---------------------------------------------------------`
239			`-- ----------------------------------------------------------------------------`
240			`-- cpu writes to UART registers`
241			`-- ----------------------------------------------------------------------------`
242
243			`reg_write : PROCESS (CLK, aresetn)`
244			`BEGIN`
245			`IF (aresetn = '0') THEN`
246			`tx_hold_reg <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';`
247			`fifo_write_tx <= '1';`
248			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
249			`IF (sresetn = '0') THEN`
250			`tx_hold_reg <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';`
251			`fifo_write_tx <= '1';`
252			`ELSE`
253			`fifo_write_tx <= '1';`
254			`IF (csn = '0' AND WEn = '0') THEN`
255			`tx_hold_reg <= DATA_IN;`
256			`fifo_write_tx <= '0';`
257			`END IF;`
258			`END IF;`
259			`END IF;`
260			`END PROCESS reg_write;`
261			`temp_xhdl7 <= '1' WHEN (WEn = '0' AND csn = '0') ELSE '0';`
262			`rst_tx_empty <= temp_xhdl7 ;`
263
264
265			`PROCESS (rx_byte, rx_dout_reg, parity_err_xhdl1)`
266			`VARIABLE data_out_xhdl5_xhdl8 : std_logic_vector(7 DOWNTO 0);`
267			`BEGIN`
268			`IF (RX_FIFO = 2#0#) THEN`
269			`data_out_xhdl5_xhdl8 := rx_byte;`
270			`ELSE`
271			`IF (parity_err_xhdl1 = '1') THEN`
272			`data_out_xhdl5_xhdl8 := rx_byte;`
273			`ELSE`
274			`data_out_xhdl5_xhdl8 := rx_dout_reg;`
275			`END IF;`
276			`END IF;`
277			`data_out_xhdl5 <= data_out_xhdl5_xhdl8;`
278			`END PROCESS;`
279
280
281			`temp_xhdl10 <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';`
282			`temp_xhdl11 <= (temp_xhdl10) WHEN (RX_FIFO = 2#0#) ELSE NOT fifo_full_rx;`
283			`read_rx_byte <= temp_xhdl11 ;`
284			`temp_xhdl12 <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';`
285			`temp_xhdl13 <= clear_parity_reg WHEN RX_FIFO /= 0 ELSE (temp_xhdl12);`
286			`clear_parity <= temp_xhdl13 ;`
287			`temp_xhdl14 <= rx_byte WHEN (parity_err_xhdl1 = '0') ELSE "00000000";`
288			`rx_byte_in <= temp_xhdl14 ;`
289			`--clear_framing_error <= clear_framing_error_reg WHEN RX_FIFO /= 0 ELSE (temp_xhdl12);`
290			`clear_framing_error <= temp_xhdl12 WHEN (RX_FIFO = 0) ELSE '1' WHEN (temp_xhdl12 = '1') ELSE clear_framing_error_reg;`
291			`clear_overflow <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';`
292
293
294			`RXRDY_LEGACY: IF (RX_LEGACY_MODE = 1) GENERATE`
295			`PROCESS (receive_full, rx_dout_reg_empty)`
296			`VARIABLE rxrdy_xhdl4_xhdl15 : std_logic;`
297			`BEGIN`
298			`IF (RX_FIFO = 2#0#) THEN`
299			`rxrdy_xhdl4_xhdl15 := receive_full;`
300			`ELSE`
301			`rxrdy_xhdl4_xhdl15 := NOT rx_dout_reg_empty;`
302			`END IF;`
303			`rxrdy_xhdl4 <= rxrdy_xhdl4_xhdl15;`
304			`END PROCESS;`
305			`END GENERATE;`
306
307			`-- AS, added 11/17/08`
308			`RXRDY_NEW: IF (RX_LEGACY_MODE = 0) GENERATE`
309			`PROCESS (CLK, aresetn)`
310			`BEGIN`
311			`IF (aresetn = '0') THEN`
312			`rxrdy_xhdl4 <= '0';`
313			`ELSIF (clk'EVENT AND clk = '1') THEN`
314			`IF (sresetn = '0') THEN`
315			`rxrdy_xhdl4 <= '0';`
316			`ELSE`
317			`IF (RX_FIFO = 0) THEN`
318			`IF (stop_strobe = '1' OR receive_full = '0') THEN`
319			`rxrdy_xhdl4 <= receive_full;`
320			`END IF;`
321			`ELSE`
322			`IF (stop_strobe = '1' OR rx_dout_reg_empty = '1' or (rx_dout_reg_empty = '0' and (rx_idle = '1' or RX_FIFO = 1))) THEN`
323			`rxrdy_xhdl4 <= NOT rx_dout_reg_empty;`
324			`END IF;`
325			`END IF;`
326			`END IF;`
327			`END IF;`
328			`END PROCESS;`
329			`END GENERATE;`
330
331			`PROCESS (CLK, aresetn)`
332			`BEGIN`
333			`IF (aresetn = '0') THEN`
334			`clear_parity_reg <= '0';`
335			`clear_parity_reg0 <= '0';`
336			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
337			`IF (sresetn = '0') THEN`
338			`clear_parity_reg <= '0';`
339			`clear_parity_reg0 <= '0';`
340			`ELSE`
341			`clear_parity_reg0 <= clear_parity_en;`
342			`clear_parity_reg <= clear_parity_reg0;`
343			`END IF;`
344			`END IF;`
345			`END PROCESS;`
346
347			`-- AS: added self-clearing framing error`
348			`PROCESS (CLK, aresetn)`
349			`BEGIN`
350			`IF (aresetn = '0') THEN`
351			`clear_framing_error_reg <= '0';`
352			`clear_framing_error_reg0 <= '0';`
353			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
354			`IF (sresetn = '0') THEN`
355			`clear_framing_error_reg <= '0';`
356			`clear_framing_error_reg0 <= '0';`
357			`ELSE`
358			`clear_framing_error_reg0 <= clear_framing_error_en;`
359			`clear_framing_error_reg <= clear_framing_error_reg0;`
360			`END IF;`
361			`END IF;`
362			`END PROCESS;`
363
364			`-- state machine to control reading from the rx fifo`
365			`PROCESS (CLK, aresetn)`
366			`BEGIN`
367			`IF (aresetn = '0') THEN`
368			`rx_state <= S0;`
369			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
370			`IF (sresetn = '0') THEN`
371			`rx_state <= S0;`
372			`ELSE`
373			`rx_state <= next_rx_state;`
374			`END IF;`
375			`END IF;`
376			`END PROCESS;`
377
378			`PROCESS (rx_state, rx_dout_reg_empty, fifo_empty_rx)`
379			`BEGIN`
380			`next_rx_state <= rx_state;`
381			`fifo_read_rx <= '1';`
382			`data_en <= '0';`
383			`CASE rx_state IS`
384			`WHEN S0 => IF (rx_dout_reg_empty = '1' AND fifo_empty_rx = '0') THEN`
385			`next_rx_state <= S1;`
386			`fifo_read_rx <= '0';`
387			`END IF;`
388			`WHEN S1 => next_rx_state <= S2;`
389			`WHEN S2 => next_rx_state <= S3;`
390			`WHEN S3 => next_rx_state <= S0;`
391			`data_en <= '1';`
392			`WHEN others => next_rx_state <= rx_state;`
393			`END CASE;`
394			`END PROCESS;`
395
396
397			`PROCESS (CLK, aresetn)`
398			`BEGIN`
399			`IF (aresetn = '0') THEN`
400			`rx_dout_reg <= "00000000";`
401			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
402			`IF (sresetn = '0') THEN`
403			`rx_dout_reg <= "00000000";`
404			`ELSE`
405			`IF (data_en = '1') THEN`
406			`rx_dout_reg <= rx_dout;`
407			`END IF;`
408			`END IF;`
409			`END IF;`
410			`END PROCESS;`
411
412			`PROCESS (CLK, aresetn)`
413			`BEGIN`
414			`IF (aresetn = '0') THEN`
415			`rx_dout_reg_empty <= '1';`
416			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
417			`IF (sresetn = '0') THEN`
418			`rx_dout_reg_empty <= '1';`
419			`ELSE`
420			`IF (data_en = '1') THEN`
421			`rx_dout_reg_empty <= '0';`
422			`ELSE`
423			`IF (csn = '0' AND OEn = '0') THEN`
424			`IF (RX_FIFO = 1) THEN`
425			`IF(parity_err_xhdl1 = '0') THEN`
426			`rx_dout_reg_empty <= '1';`
427			`END IF;`
428			`ELSE`
429			`rx_dout_reg_empty <= '1';`
430			`END IF;`
431			`END IF;`
432			`END IF;`
433			`END IF;`
434			`END IF;`
435			`END PROCESS;`
436
437			`PROCESS (CLK, aresetn)`
438			`BEGIN`
439			`IF (aresetn = '0') THEN`
440			`overflow_reg <= '0';`
441			`ELSIF (CLK'EVENT AND CLK = '1') THEN`
442			`IF (sresetn = '0') THEN`
443			`overflow_reg <= '0';`
444			`ELSE`
445			`IF (fifo_write = '0' AND fifo_full_rx = '1') THEN`
446			`overflow_reg <= '1';`
447			`ELSIF (clear_overflow = '1') THEN`
448			`overflow_reg <= '0';`
449			`ELSE`
450			`overflow_reg <= overflow_reg;`
451			`END IF;`
452			`END IF;`
453			`END IF;`
454			`END PROCESS;`
455			`-- AS: Changed OVERFLOW condition`
456			`-- - We should not be assigning OVERFLOW to FIFO_FULL;`
457			`-- instead, we should be asserting OVERFLOW if a write is`
458			`-- requested while fifo_full_rx is high`
459			`temp_xhdl16 <= overflow_reg WHEN RX_FIFO /= 0 ELSE overflow_legacy;`
460			`overflow_xhdl2 <= temp_xhdl16 ;`
461
462			`temp_xhdl17 <= '1' WHEN (parity_err_xhdl1 = '1' or fifo_full_rx = '1') ELSE fifo_write;`
463
464			`fifo_write_rx <= temp_xhdl17 ;`
465
466			`make_top_CoreUARTapb_0_Clock_gen : top_CoreUARTapb_0_Clock_gen`
467			`GENERIC MAP (`
468			`BAUD_VAL_FRCTN_EN => BAUD_VAL_FRCTN_EN,`
469			`SYNC_RESET => SYNC_RESET)`
470			`PORT MAP (`
471			`clk => CLK,`
472			`reset_n => RESET_N,`
473			`baud_val => BAUD_VAL,`
474			`BAUD_VAL_FRACTION => BAUD_VAL_FRACTION,`
475			`baud_clock => baud_clock,`
476			`xmit_pulse => xmit_pulse);`
477
478			`make_TX : top_CoreUARTapb_0_Tx_async`
479			`GENERIC MAP (`
480			`TX_FIFO => TX_FIFO,`
481			`SYNC_RESET => SYNC_RESET)`
482			`PORT MAP (`
483			`clk => CLK,`
484			`xmit_pulse => xmit_pulse,`
485			`reset_n => RESET_N,`
486			`rst_tx_empty => rst_tx_empty,`
487			`tx_hold_reg => tx_hold_reg,`
488			`tx_dout_reg => tx_dout_reg,`
489			`fifo_empty => fifo_empty_tx,`
490			`fifo_full => fifo_full_tx,`
491			`bit8 => bit8,`
492			`parity_en => parity_en,`
493			`odd_n_even => odd_n_even,`
494			`txrdy => txrdy_xhdl3,`
495			`tx => tx_xhdl6,`
496			`fifo_read_tx => fifo_read_tx);`
497
498			`make_RX : top_CoreUARTapb_0_Rx_async`
499			`GENERIC MAP (`
500			`RX_FIFO => RX_FIFO,`
501			`SYNC_RESET => SYNC_RESET)`
502			`PORT MAP (`
503			`clk => CLK,`
504			`baud_clock => baud_clock,`
505			`reset_n => RESET_N,`
506			`bit8 => bit8,`
507			`parity_en => parity_en,`
508			`odd_n_even => odd_n_even,`
509			`read_rx_byte => read_rx_byte,`
510			`clear_parity => clear_parity,`
511			`rx => RX,`
512			`overflow => overflow_legacy,`
513			`parity_err => parity_err_xhdl1,`
514			`clear_parity_en => clear_parity_en,`
515			`receive_full => receive_full,`
516			`rx_byte => rx_byte,`
517			`fifo_write => fifo_write,`
518			`clear_framing_error => clear_framing_error,`
519			`clear_framing_error_en => clear_framing_error_en,`
520			`framing_error => framing_err_i,`
521			`rx_idle_out => rx_idle,`
522			`stop_strobe => stop_strobe);`
523
524			`UG06a:IF (TX_FIFO = 2#1#) GENERATE`
525			`tx_fifo_xhdl79 : top_CoreUARTapb_0_fifo_256x8`
526			`GENERIC MAP ( SYNC_RESET => SYNC_RESET)`
527			`PORT MAP (`
528			`DO => tx_dout_reg,`
529			`RCLOCK => clk,`
530			`WCLOCK => clk,`
531			`-- AS: FIXED SARno 12821`
532			`-- DI => data_in,`
533			`DI => tx_hold_reg,`
534			`WRB => fifo_write_tx,`
535			`RDB => fifo_read_tx,`
536			`RESET => reset_n,`
537			`FULL => fifo_full_tx,`
538			`EMPTY => fifo_empty_tx);`
539			`END GENERATE;`
540
541			`UG06b:IF (TX_FIFO = 2#0#) GENERATE`
542			`tx_dout_reg <= "00000000";`
543			`fifo_full_tx <='0';`
544			`fifo_empty_tx <='0';`
545			`END GENERATE;`
546
547			`UG07:IF (RX_FIFO = 2#1#) GENERATE`
548			`rx_fifo_xhdl80 : top_CoreUARTapb_0_fifo_256x8`
549			`GENERIC MAP ( SYNC_RESET => SYNC_RESET)`
550			`PORT MAP (`
551			`DO => rx_dout,`
552			`RCLOCK => clk,`
553			`WCLOCK => clk,`
554			`DI => rx_byte_in,`
555			`WRB => fifo_write_rx,`
556			`RDB => fifo_read_rx,`
557			`RESET => reset_n,`
558			`FULL => fifo_full_rx,`
559			`EMPTY => fifo_empty_rx);`
560			`END GENERATE;`
561
562			`UG07b:IF (RX_FIFO = 2#0#) GENERATE`
563			`rx_dout <= "00000000";`
564			`fifo_full_rx <='0';`
565			`fifo_empty_rx <='0';`
566			`END GENERATE;`
567
568			`END ARCHITECTURE translated;`