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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [CoreUARTapb_0/] [rtl/] [vhdl/] [core/] [fifo_256x8_pa3.vhd] - Blame information for rev 3

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1 3 uson 
-- ********************************************************************
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-- Actel Corporation Proprietary and Confidential
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--  Copyright 2008 Actel Corporation.  All rights reserved.
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--
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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--
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-- Description: CoreUART/ CoreUARTapb UART core
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--
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--
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--  Revision Information:
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-- Date     Description
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-- Jun09    Revision 4.1
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-- Aug10    Revision 4.2
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-- SVN Revision Information:
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-- SVN $Revision: 8508 $
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-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
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--
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-- Resolved SARs
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-- SAR      Date     Who   Description
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-- 20741    2Sep10   AS    Increased baud rate by ensuring fifo ctrl runs off
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--                         sys clk (not baud clock).  See note below.
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-- Notes:
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-- best viewed with tabstops set to "4"
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library ieee;
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use ieee.std_logic_1164.all;
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library proasic3;
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ENTITY top_CoreUARTapb_0_fifo_256x8 IS
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   GENERIC(SYNC_RESET: INTEGER := 0);
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   PORT (
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      DO                      : OUT std_logic_vector(7 DOWNTO 0);
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      RCLOCK                  : IN std_logic;
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      WCLOCK                  : IN std_logic;
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      DI                      : IN std_logic_vector(7 DOWNTO 0);
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      WRB                     : IN std_logic;
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      RDB                     : IN std_logic;
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      RESET                   : IN std_logic;
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      FULL                    : OUT std_logic;
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      EMPTY                   : OUT std_logic);
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END ENTITY top_CoreUARTapb_0_fifo_256x8;
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ARCHITECTURE translated OF top_CoreUARTapb_0_fifo_256x8 IS
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COMPONENT top_CoreUARTapb_0_fifo_256x8_pa3
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   PORT (
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      DATA                    : IN std_logic_vector(7 DOWNTO 0);
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      Q                       : OUT std_logic_vector(7 DOWNTO 0);
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      WE                      : IN std_logic;
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      RE                      : IN std_logic;
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      WCLOCK                  : IN std_logic;
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      RCLOCK                  : IN std_logic;
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      FULL                    : OUT std_logic;
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      EMPTY                   : OUT std_logic;
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      RESET                   : IN std_logic;
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      AEMPTY                  : OUT std_logic;
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      AFULL                   : OUT std_logic;
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      LEVEL                   : IN std_logic_vector(7 DOWNTO 0));
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END COMPONENT;
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   CONSTANT  LEVEL                 :  std_logic_vector(7 DOWNTO 0) := "11111111";
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   SIGNAL AEMPTY                   :  std_logic;
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   SIGNAL AFULL                    :  std_logic;
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   SIGNAL DO_0                     :  std_logic_vector(7 DOWNTO 0);
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   SIGNAL DO_xhdl1                 :  std_logic_vector(7 DOWNTO 0);
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   SIGNAL FULL_xhdl2               :  std_logic;
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   SIGNAL EMPTY_xhdl3              :  std_logic;
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   SIGNAL EQTH_xhdl4               :  std_logic;
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   SIGNAL GEQTH_xhdl5              :  std_logic;
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BEGIN
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   DO <= DO_xhdl1;
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   FULL <= FULL_xhdl2;
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   EMPTY <= EMPTY_xhdl3;
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   PROCESS (RCLOCK)
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   BEGIN
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      IF (RCLOCK'EVENT AND RCLOCK = '1') THEN
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         DO_xhdl1 <= DO_0;
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      END IF;
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   END PROCESS;
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   top_CoreUARTapb_0_fifo_256x8_pa3_xhdl14 : top_CoreUARTapb_0_fifo_256x8_pa3
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      PORT MAP (
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         DATA => DI,
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         Q => DO_0,
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         WE => WRB,
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         RE => RDB,
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         WCLOCK => WCLOCK,
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         RCLOCK => RCLOCK,
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         AEMPTY => AEMPTY,
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         AFULL => GEQTH_xhdl5,
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         FULL => FULL_xhdl2,
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         EMPTY => EMPTY_xhdl3,
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         RESET => RESET,
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         LEVEL => LEVEL);
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END ARCHITECTURE translated;
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library ieee;
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use ieee.std_logic_1164.all;
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library proasic3;
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ENTITY top_CoreUARTapb_0_fifo_256x8_pa3 IS
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   PORT (
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      DATA                    : IN std_logic_vector(7 DOWNTO 0);
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      Q                       : OUT std_logic_vector(7 DOWNTO 0);
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      WE                      : IN std_logic;
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      RE                      : IN std_logic;
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      WCLOCK                  : IN std_logic;
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      RCLOCK                  : IN std_logic;
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      FULL                    : OUT std_logic;
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      EMPTY                   : OUT std_logic;
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      RESET                   : IN std_logic;
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      AEMPTY                  : OUT std_logic;
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      AFULL                   : OUT std_logic;
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      LEVEL                   : IN std_logic_vector(7 DOWNTO 0));
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END ENTITY top_CoreUARTapb_0_fifo_256x8_pa3;
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ARCHITECTURE translated OF top_CoreUARTapb_0_fifo_256x8_pa3 IS
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    component INV
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        port(A : in std_logic := 'U'; Y : out std_logic) ;
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    end component;
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    component FIFO4K18
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        port(AEVAL11, AEVAL10, AEVAL9, AEVAL8, AEVAL7, AEVAL6,
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        AEVAL5, AEVAL4, AEVAL3, AEVAL2, AEVAL1, AEVAL0, AFVAL11,
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        AFVAL10, AFVAL9, AFVAL8, AFVAL7, AFVAL6, AFVAL5, AFVAL4,
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        AFVAL3, AFVAL2, AFVAL1, AFVAL0, WD17, WD16, WD15, WD14,
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        WD13, WD12, WD11, WD10, WD9, WD8, WD7, WD6, WD5, WD4, WD3,
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        WD2, WD1, WD0, WW0, WW1, WW2, RW0, RW1, RW2, RPIPE, WEN,
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        REN, WBLK, RBLK, WCLK, RCLK, RESET, ESTOP, FSTOP : in
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        std_logic := 'U'; RD17, RD16, RD15, RD14, RD13, RD12,
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        RD11, RD10, RD9, RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1,
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        RD0, FULL, AFULL, EMPTY, AEMPTY : out std_logic) ;
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    end component;
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    component VCC
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        port( Y : out std_logic);
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    end component;
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    component GND
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        port( Y : out std_logic);
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    end component;
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   SIGNAL WEAP                     :  std_logic;
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   SIGNAL VCC_0                      :  std_logic;
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   SIGNAL GND_0                      :  std_logic;
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   SIGNAL Q_xhdl1                  :  std_logic_vector(7 DOWNTO 0);
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   SIGNAL FULL_xhdl2               :  std_logic;
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   SIGNAL EMPTY_xhdl3              :  std_logic;
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   SIGNAL AEMPTY_xhdl4             :  std_logic;
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   SIGNAL AFULL_xhdl5              :  std_logic;
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BEGIN
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   Q <= Q_xhdl1;
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   FULL <= FULL_xhdl2;
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   EMPTY <= EMPTY_xhdl3;
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   AEMPTY <= AEMPTY_xhdl4;
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   AFULL <= AFULL_xhdl5;
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   VCC_1_net : VCC PORT MAP ( Y => VCC_0);
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   GND_1_net : GND PORT MAP ( Y => GND_0);
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   REBUBBLEA : INV PORT MAP ( A => RE, Y => WEAP);
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   FIFOBLOCK0 : FIFO4K18
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      PORT MAP (
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         AEVAL11 => GND_0,
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         AEVAL10 => GND_0,
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         AEVAL9 => GND_0,
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         AEVAL8 => GND_0,
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         AEVAL7 => GND_0,
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         AEVAL6 => GND_0,
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         AEVAL5 => GND_0,
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         AEVAL4 => GND_0,
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         AEVAL3 => VCC_0,
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         AEVAL2 => GND_0,
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         AEVAL1 => GND_0,
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         AEVAL0 => GND_0,
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         AFVAL11 => GND_0,
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         AFVAL10 => LEVEL(7),
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         AFVAL9 =>  LEVEL(6),
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         AFVAL8 => LEVEL(5),
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         AFVAL7 => LEVEL(4),
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         AFVAL6 =>  LEVEL(3),
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         AFVAL5 => LEVEL(2),
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         AFVAL4 => LEVEL(1),
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         AFVAL3 =>  LEVEL(0),
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         AFVAL2 => GND_0,
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         AFVAL1 => GND_0,
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         AFVAL0 => GND_0,
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         WD17 => GND_0,
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         WD16 => GND_0,
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         WD15 => GND_0,
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         WD14 => GND_0,
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         WD13 => GND_0,
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         WD12 => GND_0,
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         WD11 => GND_0,
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         WD10 => GND_0,
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         WD9 => GND_0,
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         WD8 => GND_0,
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         WD7 => DATA(7),
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         WD6 => DATA(6),
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         WD5 => DATA(5),
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         WD4 => DATA(4),
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         WD3 => DATA(3),
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         WD2 => DATA(2),
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         WD1 => DATA(1),
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         WD0 => DATA(0),
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         WW0 => VCC_0,
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         WW1 => VCC_0,
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         WW2 => GND_0,
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         RW0 => VCC_0,
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         RW1 => VCC_0,
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         RW2 => GND_0,
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         RPIPE => GND_0,
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         WEN => WE,
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         REN => WEAP,
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         WBLK => GND_0,
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         RBLK => GND_0,
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         WCLK => WCLOCK,
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         RCLK => RCLOCK,
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         RESET => RESET,
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         ESTOP => VCC_0,
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         FSTOP => VCC_0,
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         RD17 => open,
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         RD16 => open,
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         RD15 => open,
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         RD14 => open,
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         RD13 => open,
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         RD12 => open,
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         RD11 => open,
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         RD10 => open,
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         RD9 => open,
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         RD8 => open,
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         RD7 => Q_xhdl1(7),
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         RD6 => Q_xhdl1(6),
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         RD5 => Q_xhdl1(5),
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         RD4 => Q_xhdl1(4),
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         RD3 => Q_xhdl1(3),
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         RD2 => Q_xhdl1(2),
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         RD1 => Q_xhdl1(1),
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         RD0 => Q_xhdl1(0),
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         FULL => open,
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         AFULL => FULL_xhdl2,
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         EMPTY => EMPTY_xhdl3,
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         AEMPTY => AEMPTY_xhdl4);
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END ARCHITECTURE translated;

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