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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [top.vhd] - Blame information for rev 3

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1 3 uson 
----------------------------------------------------------------------
2 
-- Created by SmartDesign Sat Jun 02 22:52:57 2018
3 
-- Version: v11.8 SP3 11.8.3.6
4 
----------------------------------------------------------------------
5 
 
6 
----------------------------------------------------------------------
7 
-- Libraries
8 
----------------------------------------------------------------------
9 
library ieee;
10 
use ieee.std_logic_1164.all;
11 
 
12 
library proasic3;
13 
use proasic3.all;
14 
library COREAHBLITE_LIB;
15 
use COREAHBLITE_LIB.all;
16 
use COREAHBLITE_LIB.top_CoreAHBLite_0_components.all;
17 
library COREUARTAPB_LIB;
18 
use COREUARTAPB_LIB.all;
19 
use COREUARTAPB_LIB.top_CoreUARTapb_0_components.all;
20 
----------------------------------------------------------------------
21 
-- top entity declaration
22 
----------------------------------------------------------------------
23 
entity top is
24 
    -- Port list
25 
    port(
26 
        -- Inputs
27 
        ADDR     : in  std_logic_vector(31 downto 0);
28 
        DATAIN   : in  std_logic_vector(31 downto 0);
29 
        HCLK     : in  std_logic;
30 
        HRESETn  : in  std_logic;
31 
        LREAD    : in  std_logic;
32 
        LWRITE   : in  std_logic;
33 
        -- Outputs
34 
        DATAOUT  : out std_logic_vector(31 downto 0);
35 
        RESP_err : out std_logic_vector(1 downto 0);
36 
        TX       : out std_logic;
37 
        ahb_busy : out std_logic
38 
        );
39 
end top;
40 
----------------------------------------------------------------------
41 
-- top architecture body
42 
----------------------------------------------------------------------
43 
architecture RTL of top is
44 
----------------------------------------------------------------------
45 
-- Component declarations
46 
----------------------------------------------------------------------
47 
-- AHBMASTER_FIC
48 
-- using entity instantiation for component AHBMASTER_FIC
49 
-- CoreAHB2APB   -   Actel:DirectCore:CoreAHB2APB:1.1.101
50 
component CoreAHB2APB
51 
    -- Port list
52 
    port(
53 
        -- Inputs
54 
        HADDR     : in  std_logic_vector(27 downto 0);
55 
        HCLK      : in  std_logic;
56 
        HREADY    : in  std_logic;
57 
        HRESETn   : in  std_logic;
58 
        HSEL      : in  std_logic;
59 
        HTRANS    : in  std_logic_vector(1 downto 0);
60 
        HWDATA    : in  std_logic_vector(31 downto 0);
61 
        HWRITE    : in  std_logic;
62 
        PRDATA    : in  std_logic_vector(31 downto 0);
63 
        -- Outputs
64 
        HRDATA    : out std_logic_vector(31 downto 0);
65 
        HREADYOUT : out std_logic;
66 
        HRESP     : out std_logic_vector(1 downto 0);
67 
        PADDR     : out std_logic_vector(23 downto 0);
68 
        PENABLE   : out std_logic;
69 
        PSELECT   : out std_logic_vector(15 downto 0);
70 
        PWDATA    : out std_logic_vector(31 downto 0);
71 
        PWRITE    : out std_logic
72 
        );
73 
end component;
74 
-- top_CoreAHBLite_0_CoreAHBLite   -   Actel:DirectCore:CoreAHBLite:5.3.101
75 
component top_CoreAHBLite_0_CoreAHBLite
76 
    generic(
77 
        FAMILY             : integer := 15 ;
78 
        HADDR_SHG_CFG      : integer := 1 ;
79 
        M0_AHBSLOT0ENABLE  : integer := 1 ;
80 
        M0_AHBSLOT1ENABLE  : integer := 0 ;
81 
        M0_AHBSLOT2ENABLE  : integer := 0 ;
82 
        M0_AHBSLOT3ENABLE  : integer := 0 ;
83 
        M0_AHBSLOT4ENABLE  : integer := 0 ;
84 
        M0_AHBSLOT5ENABLE  : integer := 0 ;
85 
        M0_AHBSLOT6ENABLE  : integer := 0 ;
86 
        M0_AHBSLOT7ENABLE  : integer := 0 ;
87 
        M0_AHBSLOT8ENABLE  : integer := 0 ;
88 
        M0_AHBSLOT9ENABLE  : integer := 0 ;
89 
        M0_AHBSLOT10ENABLE : integer := 0 ;
90 
        M0_AHBSLOT11ENABLE : integer := 0 ;
91 
        M0_AHBSLOT12ENABLE : integer := 0 ;
92 
        M0_AHBSLOT13ENABLE : integer := 0 ;
93 
        M0_AHBSLOT14ENABLE : integer := 0 ;
94 
        M0_AHBSLOT15ENABLE : integer := 0 ;
95 
        M0_AHBSLOT16ENABLE : integer := 0 ;
96 
        M1_AHBSLOT0ENABLE  : integer := 0 ;
97 
        M1_AHBSLOT1ENABLE  : integer := 0 ;
98 
        M1_AHBSLOT2ENABLE  : integer := 0 ;
99 
        M1_AHBSLOT3ENABLE  : integer := 0 ;
100 
        M1_AHBSLOT4ENABLE  : integer := 0 ;
101 
        M1_AHBSLOT5ENABLE  : integer := 0 ;
102 
        M1_AHBSLOT6ENABLE  : integer := 0 ;
103 
        M1_AHBSLOT7ENABLE  : integer := 0 ;
104 
        M1_AHBSLOT8ENABLE  : integer := 0 ;
105 
        M1_AHBSLOT9ENABLE  : integer := 0 ;
106 
        M1_AHBSLOT10ENABLE : integer := 0 ;
107 
        M1_AHBSLOT11ENABLE : integer := 0 ;
108 
        M1_AHBSLOT12ENABLE : integer := 0 ;
109 
        M1_AHBSLOT13ENABLE : integer := 0 ;
110 
        M1_AHBSLOT14ENABLE : integer := 0 ;
111 
        M1_AHBSLOT15ENABLE : integer := 0 ;
112 
        M1_AHBSLOT16ENABLE : integer := 0 ;
113 
        M2_AHBSLOT0ENABLE  : integer := 0 ;
114 
        M2_AHBSLOT1ENABLE  : integer := 0 ;
115 
        M2_AHBSLOT2ENABLE  : integer := 0 ;
116 
        M2_AHBSLOT3ENABLE  : integer := 0 ;
117 
        M2_AHBSLOT4ENABLE  : integer := 0 ;
118 
        M2_AHBSLOT5ENABLE  : integer := 0 ;
119 
        M2_AHBSLOT6ENABLE  : integer := 0 ;
120 
        M2_AHBSLOT7ENABLE  : integer := 0 ;
121 
        M2_AHBSLOT8ENABLE  : integer := 0 ;
122 
        M2_AHBSLOT9ENABLE  : integer := 0 ;
123 
        M2_AHBSLOT10ENABLE : integer := 0 ;
124 
        M2_AHBSLOT11ENABLE : integer := 0 ;
125 
        M2_AHBSLOT12ENABLE : integer := 0 ;
126 
        M2_AHBSLOT13ENABLE : integer := 0 ;
127 
        M2_AHBSLOT14ENABLE : integer := 0 ;
128 
        M2_AHBSLOT15ENABLE : integer := 0 ;
129 
        M2_AHBSLOT16ENABLE : integer := 0 ;
130 
        M3_AHBSLOT0ENABLE  : integer := 0 ;
131 
        M3_AHBSLOT1ENABLE  : integer := 0 ;
132 
        M3_AHBSLOT2ENABLE  : integer := 0 ;
133 
        M3_AHBSLOT3ENABLE  : integer := 0 ;
134 
        M3_AHBSLOT4ENABLE  : integer := 0 ;
135 
        M3_AHBSLOT5ENABLE  : integer := 0 ;
136 
        M3_AHBSLOT6ENABLE  : integer := 0 ;
137 
        M3_AHBSLOT7ENABLE  : integer := 0 ;
138 
        M3_AHBSLOT8ENABLE  : integer := 0 ;
139 
        M3_AHBSLOT9ENABLE  : integer := 0 ;
140 
        M3_AHBSLOT10ENABLE : integer := 0 ;
141 
        M3_AHBSLOT11ENABLE : integer := 0 ;
142 
        M3_AHBSLOT12ENABLE : integer := 0 ;
143 
        M3_AHBSLOT13ENABLE : integer := 0 ;
144 
        M3_AHBSLOT14ENABLE : integer := 0 ;
145 
        M3_AHBSLOT15ENABLE : integer := 0 ;
146 
        M3_AHBSLOT16ENABLE : integer := 0 ;
147 
        MEMSPACE           : integer := 1 ;
148 
        SC_0               : integer := 0 ;
149 
        SC_1               : integer := 0 ;
150 
        SC_2               : integer := 0 ;
151 
        SC_3               : integer := 0 ;
152 
        SC_4               : integer := 0 ;
153 
        SC_5               : integer := 0 ;
154 
        SC_6               : integer := 0 ;
155 
        SC_7               : integer := 0 ;
156 
        SC_8               : integer := 0 ;
157 
        SC_9               : integer := 0 ;
158 
        SC_10              : integer := 0 ;
159 
        SC_11              : integer := 0 ;
160 
        SC_12              : integer := 0 ;
161 
        SC_13              : integer := 0 ;
162 
        SC_14              : integer := 0 ;
163 
        SC_15              : integer := 0
164 
        );
165 
    -- Port list
166 
    port(
167 
        -- Inputs
168 
        HADDR_M0      : in  std_logic_vector(31 downto 0);
169 
        HADDR_M1      : in  std_logic_vector(31 downto 0);
170 
        HADDR_M2      : in  std_logic_vector(31 downto 0);
171 
        HADDR_M3      : in  std_logic_vector(31 downto 0);
172 
        HBURST_M0     : in  std_logic_vector(2 downto 0);
173 
        HBURST_M1     : in  std_logic_vector(2 downto 0);
174 
        HBURST_M2     : in  std_logic_vector(2 downto 0);
175 
        HBURST_M3     : in  std_logic_vector(2 downto 0);
176 
        HCLK          : in  std_logic;
177 
        HMASTLOCK_M0  : in  std_logic;
178 
        HMASTLOCK_M1  : in  std_logic;
179 
        HMASTLOCK_M2  : in  std_logic;
180 
        HMASTLOCK_M3  : in  std_logic;
181 
        HPROT_M0      : in  std_logic_vector(3 downto 0);
182 
        HPROT_M1      : in  std_logic_vector(3 downto 0);
183 
        HPROT_M2      : in  std_logic_vector(3 downto 0);
184 
        HPROT_M3      : in  std_logic_vector(3 downto 0);
185 
        HRDATA_S0     : in  std_logic_vector(31 downto 0);
186 
        HRDATA_S1     : in  std_logic_vector(31 downto 0);
187 
        HRDATA_S10    : in  std_logic_vector(31 downto 0);
188 
        HRDATA_S11    : in  std_logic_vector(31 downto 0);
189 
        HRDATA_S12    : in  std_logic_vector(31 downto 0);
190 
        HRDATA_S13    : in  std_logic_vector(31 downto 0);
191 
        HRDATA_S14    : in  std_logic_vector(31 downto 0);
192 
        HRDATA_S15    : in  std_logic_vector(31 downto 0);
193 
        HRDATA_S16    : in  std_logic_vector(31 downto 0);
194 
        HRDATA_S2     : in  std_logic_vector(31 downto 0);
195 
        HRDATA_S3     : in  std_logic_vector(31 downto 0);
196 
        HRDATA_S4     : in  std_logic_vector(31 downto 0);
197 
        HRDATA_S5     : in  std_logic_vector(31 downto 0);
198 
        HRDATA_S6     : in  std_logic_vector(31 downto 0);
199 
        HRDATA_S7     : in  std_logic_vector(31 downto 0);
200 
        HRDATA_S8     : in  std_logic_vector(31 downto 0);
201 
        HRDATA_S9     : in  std_logic_vector(31 downto 0);
202 
        HREADYOUT_S0  : in  std_logic;
203 
        HREADYOUT_S1  : in  std_logic;
204 
        HREADYOUT_S10 : in  std_logic;
205 
        HREADYOUT_S11 : in  std_logic;
206 
        HREADYOUT_S12 : in  std_logic;
207 
        HREADYOUT_S13 : in  std_logic;
208 
        HREADYOUT_S14 : in  std_logic;
209 
        HREADYOUT_S15 : in  std_logic;
210 
        HREADYOUT_S16 : in  std_logic;
211 
        HREADYOUT_S2  : in  std_logic;
212 
        HREADYOUT_S3  : in  std_logic;
213 
        HREADYOUT_S4  : in  std_logic;
214 
        HREADYOUT_S5  : in  std_logic;
215 
        HREADYOUT_S6  : in  std_logic;
216 
        HREADYOUT_S7  : in  std_logic;
217 
        HREADYOUT_S8  : in  std_logic;
218 
        HREADYOUT_S9  : in  std_logic;
219 
        HRESETN       : in  std_logic;
220 
        HRESP_S0      : in  std_logic_vector(1 downto 0);
221 
        HRESP_S1      : in  std_logic_vector(1 downto 0);
222 
        HRESP_S10     : in  std_logic_vector(1 downto 0);
223 
        HRESP_S11     : in  std_logic_vector(1 downto 0);
224 
        HRESP_S12     : in  std_logic_vector(1 downto 0);
225 
        HRESP_S13     : in  std_logic_vector(1 downto 0);
226 
        HRESP_S14     : in  std_logic_vector(1 downto 0);
227 
        HRESP_S15     : in  std_logic_vector(1 downto 0);
228 
        HRESP_S16     : in  std_logic_vector(1 downto 0);
229 
        HRESP_S2      : in  std_logic_vector(1 downto 0);
230 
        HRESP_S3      : in  std_logic_vector(1 downto 0);
231 
        HRESP_S4      : in  std_logic_vector(1 downto 0);
232 
        HRESP_S5      : in  std_logic_vector(1 downto 0);
233 
        HRESP_S6      : in  std_logic_vector(1 downto 0);
234 
        HRESP_S7      : in  std_logic_vector(1 downto 0);
235 
        HRESP_S8      : in  std_logic_vector(1 downto 0);
236 
        HRESP_S9      : in  std_logic_vector(1 downto 0);
237 
        HSIZE_M0      : in  std_logic_vector(2 downto 0);
238 
        HSIZE_M1      : in  std_logic_vector(2 downto 0);
239 
        HSIZE_M2      : in  std_logic_vector(2 downto 0);
240 
        HSIZE_M3      : in  std_logic_vector(2 downto 0);
241 
        HTRANS_M0     : in  std_logic_vector(1 downto 0);
242 
        HTRANS_M1     : in  std_logic_vector(1 downto 0);
243 
        HTRANS_M2     : in  std_logic_vector(1 downto 0);
244 
        HTRANS_M3     : in  std_logic_vector(1 downto 0);
245 
        HWDATA_M0     : in  std_logic_vector(31 downto 0);
246 
        HWDATA_M1     : in  std_logic_vector(31 downto 0);
247 
        HWDATA_M2     : in  std_logic_vector(31 downto 0);
248 
        HWDATA_M3     : in  std_logic_vector(31 downto 0);
249 
        HWRITE_M0     : in  std_logic;
250 
        HWRITE_M1     : in  std_logic;
251 
        HWRITE_M2     : in  std_logic;
252 
        HWRITE_M3     : in  std_logic;
253 
        REMAP_M0      : in  std_logic;
254 
        -- Outputs
255 
        HADDR_S0      : out std_logic_vector(31 downto 0);
256 
        HADDR_S1      : out std_logic_vector(31 downto 0);
257 
        HADDR_S10     : out std_logic_vector(31 downto 0);
258 
        HADDR_S11     : out std_logic_vector(31 downto 0);
259 
        HADDR_S12     : out std_logic_vector(31 downto 0);
260 
        HADDR_S13     : out std_logic_vector(31 downto 0);
261 
        HADDR_S14     : out std_logic_vector(31 downto 0);
262 
        HADDR_S15     : out std_logic_vector(31 downto 0);
263 
        HADDR_S16     : out std_logic_vector(31 downto 0);
264 
        HADDR_S2      : out std_logic_vector(31 downto 0);
265 
        HADDR_S3      : out std_logic_vector(31 downto 0);
266 
        HADDR_S4      : out std_logic_vector(31 downto 0);
267 
        HADDR_S5      : out std_logic_vector(31 downto 0);
268 
        HADDR_S6      : out std_logic_vector(31 downto 0);
269 
        HADDR_S7      : out std_logic_vector(31 downto 0);
270 
        HADDR_S8      : out std_logic_vector(31 downto 0);
271 
        HADDR_S9      : out std_logic_vector(31 downto 0);
272 
        HBURST_S0     : out std_logic_vector(2 downto 0);
273 
        HBURST_S1     : out std_logic_vector(2 downto 0);
274 
        HBURST_S10    : out std_logic_vector(2 downto 0);
275 
        HBURST_S11    : out std_logic_vector(2 downto 0);
276 
        HBURST_S12    : out std_logic_vector(2 downto 0);
277 
        HBURST_S13    : out std_logic_vector(2 downto 0);
278 
        HBURST_S14    : out std_logic_vector(2 downto 0);
279 
        HBURST_S15    : out std_logic_vector(2 downto 0);
280 
        HBURST_S16    : out std_logic_vector(2 downto 0);
281 
        HBURST_S2     : out std_logic_vector(2 downto 0);
282 
        HBURST_S3     : out std_logic_vector(2 downto 0);
283 
        HBURST_S4     : out std_logic_vector(2 downto 0);
284 
        HBURST_S5     : out std_logic_vector(2 downto 0);
285 
        HBURST_S6     : out std_logic_vector(2 downto 0);
286 
        HBURST_S7     : out std_logic_vector(2 downto 0);
287 
        HBURST_S8     : out std_logic_vector(2 downto 0);
288 
        HBURST_S9     : out std_logic_vector(2 downto 0);
289 
        HMASTLOCK_S0  : out std_logic;
290 
        HMASTLOCK_S1  : out std_logic;
291 
        HMASTLOCK_S10 : out std_logic;
292 
        HMASTLOCK_S11 : out std_logic;
293 
        HMASTLOCK_S12 : out std_logic;
294 
        HMASTLOCK_S13 : out std_logic;
295 
        HMASTLOCK_S14 : out std_logic;
296 
        HMASTLOCK_S15 : out std_logic;
297 
        HMASTLOCK_S16 : out std_logic;
298 
        HMASTLOCK_S2  : out std_logic;
299 
        HMASTLOCK_S3  : out std_logic;
300 
        HMASTLOCK_S4  : out std_logic;
301 
        HMASTLOCK_S5  : out std_logic;
302 
        HMASTLOCK_S6  : out std_logic;
303 
        HMASTLOCK_S7  : out std_logic;
304 
        HMASTLOCK_S8  : out std_logic;
305 
        HMASTLOCK_S9  : out std_logic;
306 
        HPROT_S0      : out std_logic_vector(3 downto 0);
307 
        HPROT_S1      : out std_logic_vector(3 downto 0);
308 
        HPROT_S10     : out std_logic_vector(3 downto 0);
309 
        HPROT_S11     : out std_logic_vector(3 downto 0);
310 
        HPROT_S12     : out std_logic_vector(3 downto 0);
311 
        HPROT_S13     : out std_logic_vector(3 downto 0);
312 
        HPROT_S14     : out std_logic_vector(3 downto 0);
313 
        HPROT_S15     : out std_logic_vector(3 downto 0);
314 
        HPROT_S16     : out std_logic_vector(3 downto 0);
315 
        HPROT_S2      : out std_logic_vector(3 downto 0);
316 
        HPROT_S3      : out std_logic_vector(3 downto 0);
317 
        HPROT_S4      : out std_logic_vector(3 downto 0);
318 
        HPROT_S5      : out std_logic_vector(3 downto 0);
319 
        HPROT_S6      : out std_logic_vector(3 downto 0);
320 
        HPROT_S7      : out std_logic_vector(3 downto 0);
321 
        HPROT_S8      : out std_logic_vector(3 downto 0);
322 
        HPROT_S9      : out std_logic_vector(3 downto 0);
323 
        HRDATA_M0     : out std_logic_vector(31 downto 0);
324 
        HRDATA_M1     : out std_logic_vector(31 downto 0);
325 
        HRDATA_M2     : out std_logic_vector(31 downto 0);
326 
        HRDATA_M3     : out std_logic_vector(31 downto 0);
327 
        HREADY_M0     : out std_logic;
328 
        HREADY_M1     : out std_logic;
329 
        HREADY_M2     : out std_logic;
330 
        HREADY_M3     : out std_logic;
331 
        HREADY_S0     : out std_logic;
332 
        HREADY_S1     : out std_logic;
333 
        HREADY_S10    : out std_logic;
334 
        HREADY_S11    : out std_logic;
335 
        HREADY_S12    : out std_logic;
336 
        HREADY_S13    : out std_logic;
337 
        HREADY_S14    : out std_logic;
338 
        HREADY_S15    : out std_logic;
339 
        HREADY_S16    : out std_logic;
340 
        HREADY_S2     : out std_logic;
341 
        HREADY_S3     : out std_logic;
342 
        HREADY_S4     : out std_logic;
343 
        HREADY_S5     : out std_logic;
344 
        HREADY_S6     : out std_logic;
345 
        HREADY_S7     : out std_logic;
346 
        HREADY_S8     : out std_logic;
347 
        HREADY_S9     : out std_logic;
348 
        HRESP_M0      : out std_logic_vector(1 downto 0);
349 
        HRESP_M1      : out std_logic_vector(1 downto 0);
350 
        HRESP_M2      : out std_logic_vector(1 downto 0);
351 
        HRESP_M3      : out std_logic_vector(1 downto 0);
352 
        HSEL_S0       : out std_logic;
353 
        HSEL_S1       : out std_logic;
354 
        HSEL_S10      : out std_logic;
355 
        HSEL_S11      : out std_logic;
356 
        HSEL_S12      : out std_logic;
357 
        HSEL_S13      : out std_logic;
358 
        HSEL_S14      : out std_logic;
359 
        HSEL_S15      : out std_logic;
360 
        HSEL_S16      : out std_logic;
361 
        HSEL_S2       : out std_logic;
362 
        HSEL_S3       : out std_logic;
363 
        HSEL_S4       : out std_logic;
364 
        HSEL_S5       : out std_logic;
365 
        HSEL_S6       : out std_logic;
366 
        HSEL_S7       : out std_logic;
367 
        HSEL_S8       : out std_logic;
368 
        HSEL_S9       : out std_logic;
369 
        HSIZE_S0      : out std_logic_vector(2 downto 0);
370 
        HSIZE_S1      : out std_logic_vector(2 downto 0);
371 
        HSIZE_S10     : out std_logic_vector(2 downto 0);
372 
        HSIZE_S11     : out std_logic_vector(2 downto 0);
373 
        HSIZE_S12     : out std_logic_vector(2 downto 0);
374 
        HSIZE_S13     : out std_logic_vector(2 downto 0);
375 
        HSIZE_S14     : out std_logic_vector(2 downto 0);
376 
        HSIZE_S15     : out std_logic_vector(2 downto 0);
377 
        HSIZE_S16     : out std_logic_vector(2 downto 0);
378 
        HSIZE_S2      : out std_logic_vector(2 downto 0);
379 
        HSIZE_S3      : out std_logic_vector(2 downto 0);
380 
        HSIZE_S4      : out std_logic_vector(2 downto 0);
381 
        HSIZE_S5      : out std_logic_vector(2 downto 0);
382 
        HSIZE_S6      : out std_logic_vector(2 downto 0);
383 
        HSIZE_S7      : out std_logic_vector(2 downto 0);
384 
        HSIZE_S8      : out std_logic_vector(2 downto 0);
385 
        HSIZE_S9      : out std_logic_vector(2 downto 0);
386 
        HTRANS_S0     : out std_logic_vector(1 downto 0);
387 
        HTRANS_S1     : out std_logic_vector(1 downto 0);
388 
        HTRANS_S10    : out std_logic_vector(1 downto 0);
389 
        HTRANS_S11    : out std_logic_vector(1 downto 0);
390 
        HTRANS_S12    : out std_logic_vector(1 downto 0);
391 
        HTRANS_S13    : out std_logic_vector(1 downto 0);
392 
        HTRANS_S14    : out std_logic_vector(1 downto 0);
393 
        HTRANS_S15    : out std_logic_vector(1 downto 0);
394 
        HTRANS_S16    : out std_logic_vector(1 downto 0);
395 
        HTRANS_S2     : out std_logic_vector(1 downto 0);
396 
        HTRANS_S3     : out std_logic_vector(1 downto 0);
397 
        HTRANS_S4     : out std_logic_vector(1 downto 0);
398 
        HTRANS_S5     : out std_logic_vector(1 downto 0);
399 
        HTRANS_S6     : out std_logic_vector(1 downto 0);
400 
        HTRANS_S7     : out std_logic_vector(1 downto 0);
401 
        HTRANS_S8     : out std_logic_vector(1 downto 0);
402 
        HTRANS_S9     : out std_logic_vector(1 downto 0);
403 
        HWDATA_S0     : out std_logic_vector(31 downto 0);
404 
        HWDATA_S1     : out std_logic_vector(31 downto 0);
405 
        HWDATA_S10    : out std_logic_vector(31 downto 0);
406 
        HWDATA_S11    : out std_logic_vector(31 downto 0);
407 
        HWDATA_S12    : out std_logic_vector(31 downto 0);
408 
        HWDATA_S13    : out std_logic_vector(31 downto 0);
409 
        HWDATA_S14    : out std_logic_vector(31 downto 0);
410 
        HWDATA_S15    : out std_logic_vector(31 downto 0);
411 
        HWDATA_S16    : out std_logic_vector(31 downto 0);
412 
        HWDATA_S2     : out std_logic_vector(31 downto 0);
413 
        HWDATA_S3     : out std_logic_vector(31 downto 0);
414 
        HWDATA_S4     : out std_logic_vector(31 downto 0);
415 
        HWDATA_S5     : out std_logic_vector(31 downto 0);
416 
        HWDATA_S6     : out std_logic_vector(31 downto 0);
417 
        HWDATA_S7     : out std_logic_vector(31 downto 0);
418 
        HWDATA_S8     : out std_logic_vector(31 downto 0);
419 
        HWDATA_S9     : out std_logic_vector(31 downto 0);
420 
        HWRITE_S0     : out std_logic;
421 
        HWRITE_S1     : out std_logic;
422 
        HWRITE_S10    : out std_logic;
423 
        HWRITE_S11    : out std_logic;
424 
        HWRITE_S12    : out std_logic;
425 
        HWRITE_S13    : out std_logic;
426 
        HWRITE_S14    : out std_logic;
427 
        HWRITE_S15    : out std_logic;
428 
        HWRITE_S16    : out std_logic;
429 
        HWRITE_S2     : out std_logic;
430 
        HWRITE_S3     : out std_logic;
431 
        HWRITE_S4     : out std_logic;
432 
        HWRITE_S5     : out std_logic;
433 
        HWRITE_S6     : out std_logic;
434 
        HWRITE_S7     : out std_logic;
435 
        HWRITE_S8     : out std_logic;
436 
        HWRITE_S9     : out std_logic
437 
        );
438 
end component;
439 
-- CoreAPB   -   Actel:DirectCore:CoreAPB:1.1.101
440 
component CoreAPB
441 
    generic(
442 
        ApbSlot0Enable  : integer := 1 ;
443 
        ApbSlot1Enable  : integer := 0 ;
444 
        ApbSlot2Enable  : integer := 0 ;
445 
        ApbSlot3Enable  : integer := 0 ;
446 
        ApbSlot4Enable  : integer := 0 ;
447 
        ApbSlot5Enable  : integer := 0 ;
448 
        ApbSlot6Enable  : integer := 0 ;
449 
        ApbSlot7Enable  : integer := 0 ;
450 
        ApbSlot8Enable  : integer := 0 ;
451 
        ApbSlot9Enable  : integer := 0 ;
452 
        ApbSlot10Enable : integer := 0 ;
453 
        ApbSlot11Enable : integer := 0 ;
454 
        ApbSlot12Enable : integer := 0 ;
455 
        ApbSlot13Enable : integer := 0 ;
456 
        ApbSlot14Enable : integer := 0 ;
457 
        ApbSlot15Enable : integer := 0
458 
        );
459 
    -- Port list
460 
    port(
461 
        -- Inputs
462 
        PADDR     : in  std_logic_vector(23 downto 0);
463 
        PENABLE   : in  std_logic;
464 
        PRDATAS0  : in  std_logic_vector(31 downto 0);
465 
        PRDATAS1  : in  std_logic_vector(31 downto 0);
466 
        PRDATAS10 : in  std_logic_vector(31 downto 0);
467 
        PRDATAS11 : in  std_logic_vector(31 downto 0);
468 
        PRDATAS12 : in  std_logic_vector(31 downto 0);
469 
        PRDATAS13 : in  std_logic_vector(31 downto 0);
470 
        PRDATAS14 : in  std_logic_vector(31 downto 0);
471 
        PRDATAS15 : in  std_logic_vector(31 downto 0);
472 
        PRDATAS2  : in  std_logic_vector(31 downto 0);
473 
        PRDATAS3  : in  std_logic_vector(31 downto 0);
474 
        PRDATAS4  : in  std_logic_vector(31 downto 0);
475 
        PRDATAS5  : in  std_logic_vector(31 downto 0);
476 
        PRDATAS6  : in  std_logic_vector(31 downto 0);
477 
        PRDATAS7  : in  std_logic_vector(31 downto 0);
478 
        PRDATAS8  : in  std_logic_vector(31 downto 0);
479 
        PRDATAS9  : in  std_logic_vector(31 downto 0);
480 
        PSELECT   : in  std_logic_vector(15 downto 0);
481 
        PWDATA    : in  std_logic_vector(31 downto 0);
482 
        PWRITE    : in  std_logic;
483 
        -- Outputs
484 
        PADDRS    : out std_logic_vector(23 downto 0);
485 
        PENABLES  : out std_logic;
486 
        PRDATA    : out std_logic_vector(31 downto 0);
487 
        PSELS0    : out std_logic;
488 
        PSELS1    : out std_logic;
489 
        PSELS10   : out std_logic;
490 
        PSELS11   : out std_logic;
491 
        PSELS12   : out std_logic;
492 
        PSELS13   : out std_logic;
493 
        PSELS14   : out std_logic;
494 
        PSELS15   : out std_logic;
495 
        PSELS2    : out std_logic;
496 
        PSELS3    : out std_logic;
497 
        PSELS4    : out std_logic;
498 
        PSELS5    : out std_logic;
499 
        PSELS6    : out std_logic;
500 
        PSELS7    : out std_logic;
501 
        PSELS8    : out std_logic;
502 
        PSELS9    : out std_logic;
503 
        PWDATAS   : out std_logic_vector(31 downto 0);
504 
        PWRITES   : out std_logic
505 
        );
506 
end component;
507 
-- top_CoreUARTapb_0_CoreUARTapb   -   Actel:DirectCore:CoreUARTapb:5.6.102
508 
component top_CoreUARTapb_0_CoreUARTapb
509 
    generic(
510 
        BAUD_VAL_FRCTN    : integer := 0 ;
511 
        BAUD_VAL_FRCTN_EN : integer := 0 ;
512 
        BAUD_VALUE        : integer := 1 ;
513 
        FAMILY            : integer := 15 ;
514 
        FIXEDMODE         : integer := 1 ;
515 
        PRG_BIT8          : integer := 1 ;
516 
        PRG_PARITY        : integer := 0 ;
517 
        RX_FIFO           : integer := 0 ;
518 
        RX_LEGACY_MODE    : integer := 0 ;
519 
        TX_FIFO           : integer := 0
520 
        );
521 
    -- Port list
522 
    port(
523 
        -- Inputs
524 
        PADDR       : in  std_logic_vector(4 downto 0);
525 
        PCLK        : in  std_logic;
526 
        PENABLE     : in  std_logic;
527 
        PRESETN     : in  std_logic;
528 
        PSEL        : in  std_logic;
529 
        PWDATA      : in  std_logic_vector(7 downto 0);
530 
        PWRITE      : in  std_logic;
531 
        RX          : in  std_logic;
532 
        -- Outputs
533 
        FRAMING_ERR : out std_logic;
534 
        OVERFLOW    : out std_logic;
535 
        PARITY_ERR  : out std_logic;
536 
        PRDATA      : out std_logic_vector(7 downto 0);
537 
        PREADY      : out std_logic;
538 
        PSLVERR     : out std_logic;
539 
        RXRDY       : out std_logic;
540 
        TX          : out std_logic;
541 
        TXRDY       : out std_logic
542 
        );
543 
end component;
544 
----------------------------------------------------------------------
545 
-- Signal declarations
546 
----------------------------------------------------------------------
547 
signal ahb_busy_net_0                     : std_logic;
548 
signal AHBMASTER_FIC_0_AHBmaster_HADDR    : std_logic_vector(31 downto 0);
549 
signal AHBMASTER_FIC_0_AHBmaster_HBURST   : std_logic_vector(2 downto 0);
550 
signal AHBMASTER_FIC_0_AHBmaster_HPROT    : std_logic_vector(3 downto 0);
551 
signal AHBMASTER_FIC_0_AHBmaster_HRDATA   : std_logic_vector(31 downto 0);
552 
signal AHBMASTER_FIC_0_AHBmaster_HREADY   : std_logic;
553 
signal AHBMASTER_FIC_0_AHBmaster_HRESP    : std_logic_vector(1 downto 0);
554 
signal AHBMASTER_FIC_0_AHBmaster_HSIZE    : std_logic_vector(2 downto 0);
555 
signal AHBMASTER_FIC_0_AHBmaster_HTRANS   : std_logic_vector(1 downto 0);
556 
signal AHBMASTER_FIC_0_AHBmaster_HWDATA   : std_logic_vector(31 downto 0);
557 
signal AHBMASTER_FIC_0_AHBmaster_HWRITE   : std_logic;
558 
signal CoreAHB2APB_0_APBmaster_PADDR      : std_logic_vector(23 downto 0);
559 
signal CoreAHB2APB_0_APBmaster_PENABLE    : std_logic;
560 
signal CoreAHB2APB_0_APBmaster_PRDATA     : std_logic_vector(31 downto 0);
561 
signal CoreAHB2APB_0_APBmaster_PSELx      : std_logic_vector(15 downto 0);
562 
signal CoreAHB2APB_0_APBmaster_PWDATA     : std_logic_vector(31 downto 0);
563 
signal CoreAHB2APB_0_APBmaster_PWRITE     : std_logic;
564 
signal CoreAHBLite_0_AHBmslave0_HBURST    : std_logic_vector(2 downto 0);
565 
signal CoreAHBLite_0_AHBmslave0_HMASTLOCK : std_logic;
566 
signal CoreAHBLite_0_AHBmslave0_HPROT     : std_logic_vector(3 downto 0);
567 
signal CoreAHBLite_0_AHBmslave0_HRDATA    : std_logic_vector(31 downto 0);
568 
signal CoreAHBLite_0_AHBmslave0_HREADY    : std_logic;
569 
signal CoreAHBLite_0_AHBmslave0_HREADYOUT : std_logic;
570 
signal CoreAHBLite_0_AHBmslave0_HRESP     : std_logic_vector(1 downto 0);
571 
signal CoreAHBLite_0_AHBmslave0_HSELx     : std_logic;
572 
signal CoreAHBLite_0_AHBmslave0_HSIZE     : std_logic_vector(2 downto 0);
573 
signal CoreAHBLite_0_AHBmslave0_HTRANS    : std_logic_vector(1 downto 0);
574 
signal CoreAHBLite_0_AHBmslave0_HWDATA    : std_logic_vector(31 downto 0);
575 
signal CoreAHBLite_0_AHBmslave0_HWRITE    : std_logic;
576 
signal CoreAPB_0_APBmslave0_PENABLE       : std_logic;
577 
signal CoreAPB_0_APBmslave0_PREADY        : std_logic;
578 
signal CoreAPB_0_APBmslave0_PSELx         : std_logic;
579 
signal CoreAPB_0_APBmslave0_PSLVERR       : std_logic;
580 
signal CoreAPB_0_APBmslave0_PWRITE        : std_logic;
581 
signal DATAOUT_net_0                      : std_logic_vector(31 downto 0);
582 
signal RESP_err_net_0                     : std_logic_vector(1 downto 0);
583 
signal TX_net_0                           : std_logic;
584 
signal ahb_busy_net_1                     : std_logic;
585 
signal DATAOUT_net_1                      : std_logic_vector(31 downto 0);
586 
signal RESP_err_net_1                     : std_logic_vector(1 downto 0);
587 
signal TX_net_1                           : std_logic;
588 
----------------------------------------------------------------------
589 
-- TiedOff Signals
590 
----------------------------------------------------------------------
591 
signal GND_net                            : std_logic;
592 
signal VCC_net                            : std_logic;
593 
signal HADDR_M1_const_net_0               : std_logic_vector(31 downto 0);
594 
signal HTRANS_M1_const_net_0              : std_logic_vector(1 downto 0);
595 
signal HSIZE_M1_const_net_0               : std_logic_vector(2 downto 0);
596 
signal HBURST_M1_const_net_0              : std_logic_vector(2 downto 0);
597 
signal HPROT_M1_const_net_0               : std_logic_vector(3 downto 0);
598 
signal HWDATA_M1_const_net_0              : std_logic_vector(31 downto 0);
599 
signal HADDR_M2_const_net_0               : std_logic_vector(31 downto 0);
600 
signal HTRANS_M2_const_net_0              : std_logic_vector(1 downto 0);
601 
signal HSIZE_M2_const_net_0               : std_logic_vector(2 downto 0);
602 
signal HBURST_M2_const_net_0              : std_logic_vector(2 downto 0);
603 
signal HPROT_M2_const_net_0               : std_logic_vector(3 downto 0);
604 
signal HWDATA_M2_const_net_0              : std_logic_vector(31 downto 0);
605 
signal HADDR_M3_const_net_0               : std_logic_vector(31 downto 0);
606 
signal HTRANS_M3_const_net_0              : std_logic_vector(1 downto 0);
607 
signal HSIZE_M3_const_net_0               : std_logic_vector(2 downto 0);
608 
signal HBURST_M3_const_net_0              : std_logic_vector(2 downto 0);
609 
signal HPROT_M3_const_net_0               : std_logic_vector(3 downto 0);
610 
signal HWDATA_M3_const_net_0              : std_logic_vector(31 downto 0);
611 
signal HRDATA_S1_const_net_0              : std_logic_vector(31 downto 0);
612 
signal HRESP_S1_const_net_0               : std_logic_vector(1 downto 0);
613 
signal HRDATA_S2_const_net_0              : std_logic_vector(31 downto 0);
614 
signal HRESP_S2_const_net_0               : std_logic_vector(1 downto 0);
615 
signal HRDATA_S3_const_net_0              : std_logic_vector(31 downto 0);
616 
signal HRESP_S3_const_net_0               : std_logic_vector(1 downto 0);
617 
signal HRDATA_S4_const_net_0              : std_logic_vector(31 downto 0);
618 
signal HRESP_S4_const_net_0               : std_logic_vector(1 downto 0);
619 
signal HRDATA_S5_const_net_0              : std_logic_vector(31 downto 0);
620 
signal HRESP_S5_const_net_0               : std_logic_vector(1 downto 0);
621 
signal HRDATA_S6_const_net_0              : std_logic_vector(31 downto 0);
622 
signal HRESP_S6_const_net_0               : std_logic_vector(1 downto 0);
623 
signal HRDATA_S7_const_net_0              : std_logic_vector(31 downto 0);
624 
signal HRESP_S7_const_net_0               : std_logic_vector(1 downto 0);
625 
signal HRDATA_S8_const_net_0              : std_logic_vector(31 downto 0);
626 
signal HRESP_S8_const_net_0               : std_logic_vector(1 downto 0);
627 
signal HRDATA_S9_const_net_0              : std_logic_vector(31 downto 0);
628 
signal HRESP_S9_const_net_0               : std_logic_vector(1 downto 0);
629 
signal HRDATA_S10_const_net_0             : std_logic_vector(31 downto 0);
630 
signal HRESP_S10_const_net_0              : std_logic_vector(1 downto 0);
631 
signal HRDATA_S11_const_net_0             : std_logic_vector(31 downto 0);
632 
signal HRESP_S11_const_net_0              : std_logic_vector(1 downto 0);
633 
signal HRDATA_S12_const_net_0             : std_logic_vector(31 downto 0);
634 
signal HRESP_S12_const_net_0              : std_logic_vector(1 downto 0);
635 
signal HRDATA_S13_const_net_0             : std_logic_vector(31 downto 0);
636 
signal HRESP_S13_const_net_0              : std_logic_vector(1 downto 0);
637 
signal HRDATA_S14_const_net_0             : std_logic_vector(31 downto 0);
638 
signal HRESP_S14_const_net_0              : std_logic_vector(1 downto 0);
639 
signal HRDATA_S15_const_net_0             : std_logic_vector(31 downto 0);
640 
signal HRESP_S15_const_net_0              : std_logic_vector(1 downto 0);
641 
signal HRDATA_S16_const_net_0             : std_logic_vector(31 downto 0);
642 
signal HRESP_S16_const_net_0              : std_logic_vector(1 downto 0);
643 
signal PRDATAS1_const_net_0               : std_logic_vector(31 downto 0);
644 
signal PRDATAS2_const_net_0               : std_logic_vector(31 downto 0);
645 
signal PRDATAS3_const_net_0               : std_logic_vector(31 downto 0);
646 
signal PRDATAS4_const_net_0               : std_logic_vector(31 downto 0);
647 
signal PRDATAS5_const_net_0               : std_logic_vector(31 downto 0);
648 
signal PRDATAS6_const_net_0               : std_logic_vector(31 downto 0);
649 
signal PRDATAS7_const_net_0               : std_logic_vector(31 downto 0);
650 
signal PRDATAS8_const_net_0               : std_logic_vector(31 downto 0);
651 
signal PRDATAS9_const_net_0               : std_logic_vector(31 downto 0);
652 
signal PRDATAS10_const_net_0              : std_logic_vector(31 downto 0);
653 
signal PRDATAS11_const_net_0              : std_logic_vector(31 downto 0);
654 
signal PRDATAS12_const_net_0              : std_logic_vector(31 downto 0);
655 
signal PRDATAS13_const_net_0              : std_logic_vector(31 downto 0);
656 
signal PRDATAS14_const_net_0              : std_logic_vector(31 downto 0);
657 
signal PRDATAS15_const_net_0              : std_logic_vector(31 downto 0);
658 
----------------------------------------------------------------------
659 
-- Bus Interface Nets Declarations - Unequal Pin Widths
660 
----------------------------------------------------------------------
661 
signal CoreAHBLite_0_AHBmslave0_HADDR_0_27to0: std_logic_vector(27 downto 0);
662 
signal CoreAHBLite_0_AHBmslave0_HADDR_0   : std_logic_vector(27 downto 0);
663 
signal CoreAHBLite_0_AHBmslave0_HADDR     : std_logic_vector(31 downto 0);
664 
 
665 
signal CoreAPB_0_APBmslave0_PADDR         : std_logic_vector(23 downto 0);
666 
signal CoreAPB_0_APBmslave0_PADDR_0_4to0  : std_logic_vector(4 downto 0);
667 
signal CoreAPB_0_APBmslave0_PADDR_0       : std_logic_vector(4 downto 0);
668 
 
669 
signal CoreAPB_0_APBmslave0_PRDATA_0_31to8: std_logic_vector(31 downto 8);
670 
signal CoreAPB_0_APBmslave0_PRDATA_0_7to0 : std_logic_vector(7 downto 0);
671 
signal CoreAPB_0_APBmslave0_PRDATA_0      : std_logic_vector(31 downto 0);
672 
signal CoreAPB_0_APBmslave0_PRDATA        : std_logic_vector(7 downto 0);
673 
 
674 
signal CoreAPB_0_APBmslave0_PWDATA        : std_logic_vector(31 downto 0);
675 
signal CoreAPB_0_APBmslave0_PWDATA_0_7to0 : std_logic_vector(7 downto 0);
676 
signal CoreAPB_0_APBmslave0_PWDATA_0      : std_logic_vector(7 downto 0);
677 
 
678 
 
679 
begin
680 
----------------------------------------------------------------------
681 
-- Constant assignments
682 
----------------------------------------------------------------------
683 
 GND_net                <= '0';
684 
 VCC_net                <= '1';
685 
 HADDR_M1_const_net_0   <= B"00000000000000000000000000000000";
686 
 HTRANS_M1_const_net_0  <= B"00";
687 
 HSIZE_M1_const_net_0   <= B"000";
688 
 HBURST_M1_const_net_0  <= B"000";
689 
 HPROT_M1_const_net_0   <= B"0000";
690 
 HWDATA_M1_const_net_0  <= B"00000000000000000000000000000000";
691 
 HADDR_M2_const_net_0   <= B"00000000000000000000000000000000";
692 
 HTRANS_M2_const_net_0  <= B"00";
693 
 HSIZE_M2_const_net_0   <= B"000";
694 
 HBURST_M2_const_net_0  <= B"000";
695 
 HPROT_M2_const_net_0   <= B"0000";
696 
 HWDATA_M2_const_net_0  <= B"00000000000000000000000000000000";
697 
 HADDR_M3_const_net_0   <= B"00000000000000000000000000000000";
698 
 HTRANS_M3_const_net_0  <= B"00";
699 
 HSIZE_M3_const_net_0   <= B"000";
700 
 HBURST_M3_const_net_0  <= B"000";
701 
 HPROT_M3_const_net_0   <= B"0000";
702 
 HWDATA_M3_const_net_0  <= B"00000000000000000000000000000000";
703 
 HRDATA_S1_const_net_0  <= B"00000000000000000000000000000000";
704 
 HRESP_S1_const_net_0   <= B"00";
705 
 HRDATA_S2_const_net_0  <= B"00000000000000000000000000000000";
706 
 HRESP_S2_const_net_0   <= B"00";
707 
 HRDATA_S3_const_net_0  <= B"00000000000000000000000000000000";
708 
 HRESP_S3_const_net_0   <= B"00";
709 
 HRDATA_S4_const_net_0  <= B"00000000000000000000000000000000";
710 
 HRESP_S4_const_net_0   <= B"00";
711 
 HRDATA_S5_const_net_0  <= B"00000000000000000000000000000000";
712 
 HRESP_S5_const_net_0   <= B"00";
713 
 HRDATA_S6_const_net_0  <= B"00000000000000000000000000000000";
714 
 HRESP_S6_const_net_0   <= B"00";
715 
 HRDATA_S7_const_net_0  <= B"00000000000000000000000000000000";
716 
 HRESP_S7_const_net_0   <= B"00";
717 
 HRDATA_S8_const_net_0  <= B"00000000000000000000000000000000";
718 
 HRESP_S8_const_net_0   <= B"00";
719 
 HRDATA_S9_const_net_0  <= B"00000000000000000000000000000000";
720 
 HRESP_S9_const_net_0   <= B"00";
721 
 HRDATA_S10_const_net_0 <= B"00000000000000000000000000000000";
722 
 HRESP_S10_const_net_0  <= B"00";
723 
 HRDATA_S11_const_net_0 <= B"00000000000000000000000000000000";
724 
 HRESP_S11_const_net_0  <= B"00";
725 
 HRDATA_S12_const_net_0 <= B"00000000000000000000000000000000";
726 
 HRESP_S12_const_net_0  <= B"00";
727 
 HRDATA_S13_const_net_0 <= B"00000000000000000000000000000000";
728 
 HRESP_S13_const_net_0  <= B"00";
729 
 HRDATA_S14_const_net_0 <= B"00000000000000000000000000000000";
730 
 HRESP_S14_const_net_0  <= B"00";
731 
 HRDATA_S15_const_net_0 <= B"00000000000000000000000000000000";
732 
 HRESP_S15_const_net_0  <= B"00";
733 
 HRDATA_S16_const_net_0 <= B"00000000000000000000000000000000";
734 
 HRESP_S16_const_net_0  <= B"00";
735 
 PRDATAS1_const_net_0   <= B"00000000000000000000000000000000";
736 
 PRDATAS2_const_net_0   <= B"00000000000000000000000000000000";
737 
 PRDATAS3_const_net_0   <= B"00000000000000000000000000000000";
738 
 PRDATAS4_const_net_0   <= B"00000000000000000000000000000000";
739 
 PRDATAS5_const_net_0   <= B"00000000000000000000000000000000";
740 
 PRDATAS6_const_net_0   <= B"00000000000000000000000000000000";
741 
 PRDATAS7_const_net_0   <= B"00000000000000000000000000000000";
742 
 PRDATAS8_const_net_0   <= B"00000000000000000000000000000000";
743 
 PRDATAS9_const_net_0   <= B"00000000000000000000000000000000";
744 
 PRDATAS10_const_net_0  <= B"00000000000000000000000000000000";
745 
 PRDATAS11_const_net_0  <= B"00000000000000000000000000000000";
746 
 PRDATAS12_const_net_0  <= B"00000000000000000000000000000000";
747 
 PRDATAS13_const_net_0  <= B"00000000000000000000000000000000";
748 
 PRDATAS14_const_net_0  <= B"00000000000000000000000000000000";
749 
 PRDATAS15_const_net_0  <= B"00000000000000000000000000000000";
750 
----------------------------------------------------------------------
751 
-- Top level output port assignments
752 
----------------------------------------------------------------------
753 
 ahb_busy_net_1       <= ahb_busy_net_0;
754 
 ahb_busy             <= ahb_busy_net_1;
755 
 DATAOUT_net_1        <= DATAOUT_net_0;
756 
 DATAOUT(31 downto 0) <= DATAOUT_net_1;
757 
 RESP_err_net_1       <= RESP_err_net_0;
758 
 RESP_err(1 downto 0) <= RESP_err_net_1;
759 
 TX_net_1             <= TX_net_0;
760 
 TX                   <= TX_net_1;
761 
----------------------------------------------------------------------
762 
-- Bus Interface Nets Assignments - Unequal Pin Widths
763 
----------------------------------------------------------------------
764 
 CoreAHBLite_0_AHBmslave0_HADDR_0_27to0(27 downto 0) <= CoreAHBLite_0_AHBmslave0_HADDR(27 downto 0);
765 
 CoreAHBLite_0_AHBmslave0_HADDR_0 <= ( CoreAHBLite_0_AHBmslave0_HADDR_0_27to0(27 downto 0) );
766 
 
767 
 CoreAPB_0_APBmslave0_PADDR_0_4to0(4 downto 0) <= CoreAPB_0_APBmslave0_PADDR(4 downto 0);
768 
 CoreAPB_0_APBmslave0_PADDR_0 <= ( CoreAPB_0_APBmslave0_PADDR_0_4to0(4 downto 0) );
769 
 
770 
 CoreAPB_0_APBmslave0_PRDATA_0_31to8(31 downto 8) <= B"000000000000000000000000";
771 
 CoreAPB_0_APBmslave0_PRDATA_0_7to0(7 downto 0) <= CoreAPB_0_APBmslave0_PRDATA(7 downto 0);
772 
 CoreAPB_0_APBmslave0_PRDATA_0 <= ( CoreAPB_0_APBmslave0_PRDATA_0_31to8(31 downto 8) & CoreAPB_0_APBmslave0_PRDATA_0_7to0(7 downto 0) );
773 
 
774 
 CoreAPB_0_APBmslave0_PWDATA_0_7to0(7 downto 0) <= CoreAPB_0_APBmslave0_PWDATA(7 downto 0);
775 
 CoreAPB_0_APBmslave0_PWDATA_0 <= ( CoreAPB_0_APBmslave0_PWDATA_0_7to0(7 downto 0) );
776 
 
777 
----------------------------------------------------------------------
778 
-- Component instances
779 
----------------------------------------------------------------------
780 
-- AHBMASTER_FIC_0
781 
AHBMASTER_FIC_0 : entity work.AHBMASTER_FIC
782 
    port map(
783 
        -- Inputs
784 
        HCLK     => HCLK,
785 
        HRESETn  => HRESETn,
786 
        LREAD    => LREAD,
787 
        LWRITE   => LWRITE,
788 
        HREADY   => AHBMASTER_FIC_0_AHBmaster_HREADY,
789 
        ADDR     => ADDR,
790 
        DATAIN   => DATAIN,
791 
        HRDATA   => AHBMASTER_FIC_0_AHBmaster_HRDATA,
792 
        HRESP    => AHBMASTER_FIC_0_AHBmaster_HRESP,
793 
        -- Outputs
794 
        HWRITE   => AHBMASTER_FIC_0_AHBmaster_HWRITE,
795 
        ahb_busy => ahb_busy_net_0,
796 
        DATAOUT  => DATAOUT_net_0,
797 
        HADDR    => AHBMASTER_FIC_0_AHBmaster_HADDR,
798 
        HTRANS   => AHBMASTER_FIC_0_AHBmaster_HTRANS,
799 
        HSIZE    => AHBMASTER_FIC_0_AHBmaster_HSIZE,
800 
        HBURST   => AHBMASTER_FIC_0_AHBmaster_HBURST,
801 
        HPROT    => AHBMASTER_FIC_0_AHBmaster_HPROT,
802 
        HWDATA   => AHBMASTER_FIC_0_AHBmaster_HWDATA,
803 
        RESP_err => RESP_err_net_0
804 
        );
805 
-- CoreAHB2APB_0   -   Actel:DirectCore:CoreAHB2APB:1.1.101
806 
CoreAHB2APB_0 : CoreAHB2APB
807 
    port map(
808 
        -- Inputs
809 
        HCLK      => HCLK,
810 
        HRESETn   => HRESETn,
811 
        HWRITE    => CoreAHBLite_0_AHBmslave0_HWRITE,
812 
        HSEL      => CoreAHBLite_0_AHBmslave0_HSELx,
813 
        HREADY    => CoreAHBLite_0_AHBmslave0_HREADY,
814 
        HADDR     => CoreAHBLite_0_AHBmslave0_HADDR_0,
815 
        HTRANS    => CoreAHBLite_0_AHBmslave0_HTRANS,
816 
        HWDATA    => CoreAHBLite_0_AHBmslave0_HWDATA,
817 
        PRDATA    => CoreAHB2APB_0_APBmaster_PRDATA,
818 
        -- Outputs
819 
        HREADYOUT => CoreAHBLite_0_AHBmslave0_HREADYOUT,
820 
        PENABLE   => CoreAHB2APB_0_APBmaster_PENABLE,
821 
        PWRITE    => CoreAHB2APB_0_APBmaster_PWRITE,
822 
        HRDATA    => CoreAHBLite_0_AHBmslave0_HRDATA,
823 
        HRESP     => CoreAHBLite_0_AHBmslave0_HRESP,
824 
        PWDATA    => CoreAHB2APB_0_APBmaster_PWDATA,
825 
        PADDR     => CoreAHB2APB_0_APBmaster_PADDR,
826 
        PSELECT   => CoreAHB2APB_0_APBmaster_PSELx
827 
        );
828 
-- CoreAHBLite_0   -   Actel:DirectCore:CoreAHBLite:5.3.101
829 
CoreAHBLite_0 : top_CoreAHBLite_0_CoreAHBLite
830 
    generic map(
831 
        FAMILY             => ( 15 ),
832 
        HADDR_SHG_CFG      => ( 1 ),
833 
        M0_AHBSLOT0ENABLE  => ( 1 ),
834 
        M0_AHBSLOT1ENABLE  => ( 0 ),
835 
        M0_AHBSLOT2ENABLE  => ( 0 ),
836 
        M0_AHBSLOT3ENABLE  => ( 0 ),
837 
        M0_AHBSLOT4ENABLE  => ( 0 ),
838 
        M0_AHBSLOT5ENABLE  => ( 0 ),
839 
        M0_AHBSLOT6ENABLE  => ( 0 ),
840 
        M0_AHBSLOT7ENABLE  => ( 0 ),
841 
        M0_AHBSLOT8ENABLE  => ( 0 ),
842 
        M0_AHBSLOT9ENABLE  => ( 0 ),
843 
        M0_AHBSLOT10ENABLE => ( 0 ),
844 
        M0_AHBSLOT11ENABLE => ( 0 ),
845 
        M0_AHBSLOT12ENABLE => ( 0 ),
846 
        M0_AHBSLOT13ENABLE => ( 0 ),
847 
        M0_AHBSLOT14ENABLE => ( 0 ),
848 
        M0_AHBSLOT15ENABLE => ( 0 ),
849 
        M0_AHBSLOT16ENABLE => ( 0 ),
850 
        M1_AHBSLOT0ENABLE  => ( 0 ),
851 
        M1_AHBSLOT1ENABLE  => ( 0 ),
852 
        M1_AHBSLOT2ENABLE  => ( 0 ),
853 
        M1_AHBSLOT3ENABLE  => ( 0 ),
854 
        M1_AHBSLOT4ENABLE  => ( 0 ),
855 
        M1_AHBSLOT5ENABLE  => ( 0 ),
856 
        M1_AHBSLOT6ENABLE  => ( 0 ),
857 
        M1_AHBSLOT7ENABLE  => ( 0 ),
858 
        M1_AHBSLOT8ENABLE  => ( 0 ),
859 
        M1_AHBSLOT9ENABLE  => ( 0 ),
860 
        M1_AHBSLOT10ENABLE => ( 0 ),
861 
        M1_AHBSLOT11ENABLE => ( 0 ),
862 
        M1_AHBSLOT12ENABLE => ( 0 ),
863 
        M1_AHBSLOT13ENABLE => ( 0 ),
864 
        M1_AHBSLOT14ENABLE => ( 0 ),
865 
        M1_AHBSLOT15ENABLE => ( 0 ),
866 
        M1_AHBSLOT16ENABLE => ( 0 ),
867 
        M2_AHBSLOT0ENABLE  => ( 0 ),
868 
        M2_AHBSLOT1ENABLE  => ( 0 ),
869 
        M2_AHBSLOT2ENABLE  => ( 0 ),
870 
        M2_AHBSLOT3ENABLE  => ( 0 ),
871 
        M2_AHBSLOT4ENABLE  => ( 0 ),
872 
        M2_AHBSLOT5ENABLE  => ( 0 ),
873 
        M2_AHBSLOT6ENABLE  => ( 0 ),
874 
        M2_AHBSLOT7ENABLE  => ( 0 ),
875 
        M2_AHBSLOT8ENABLE  => ( 0 ),
876 
        M2_AHBSLOT9ENABLE  => ( 0 ),
877 
        M2_AHBSLOT10ENABLE => ( 0 ),
878 
        M2_AHBSLOT11ENABLE => ( 0 ),
879 
        M2_AHBSLOT12ENABLE => ( 0 ),
880 
        M2_AHBSLOT13ENABLE => ( 0 ),
881 
        M2_AHBSLOT14ENABLE => ( 0 ),
882 
        M2_AHBSLOT15ENABLE => ( 0 ),
883 
        M2_AHBSLOT16ENABLE => ( 0 ),
884 
        M3_AHBSLOT0ENABLE  => ( 0 ),
885 
        M3_AHBSLOT1ENABLE  => ( 0 ),
886 
        M3_AHBSLOT2ENABLE  => ( 0 ),
887 
        M3_AHBSLOT3ENABLE  => ( 0 ),
888 
        M3_AHBSLOT4ENABLE  => ( 0 ),
889 
        M3_AHBSLOT5ENABLE  => ( 0 ),
890 
        M3_AHBSLOT6ENABLE  => ( 0 ),
891 
        M3_AHBSLOT7ENABLE  => ( 0 ),
892 
        M3_AHBSLOT8ENABLE  => ( 0 ),
893 
        M3_AHBSLOT9ENABLE  => ( 0 ),
894 
        M3_AHBSLOT10ENABLE => ( 0 ),
895 
        M3_AHBSLOT11ENABLE => ( 0 ),
896 
        M3_AHBSLOT12ENABLE => ( 0 ),
897 
        M3_AHBSLOT13ENABLE => ( 0 ),
898 
        M3_AHBSLOT14ENABLE => ( 0 ),
899 
        M3_AHBSLOT15ENABLE => ( 0 ),
900 
        M3_AHBSLOT16ENABLE => ( 0 ),
901 
        MEMSPACE           => ( 1 ),
902 
        SC_0               => ( 0 ),
903 
        SC_1               => ( 0 ),
904 
        SC_2               => ( 0 ),
905 
        SC_3               => ( 0 ),
906 
        SC_4               => ( 0 ),
907 
        SC_5               => ( 0 ),
908 
        SC_6               => ( 0 ),
909 
        SC_7               => ( 0 ),
910 
        SC_8               => ( 0 ),
911 
        SC_9               => ( 0 ),
912 
        SC_10              => ( 0 ),
913 
        SC_11              => ( 0 ),
914 
        SC_12              => ( 0 ),
915 
        SC_13              => ( 0 ),
916 
        SC_14              => ( 0 ),
917 
        SC_15              => ( 0 )
918 
        )
919 
    port map(
920 
        -- Inputs
921 
        HCLK          => HCLK,
922 
        HRESETN       => HRESETn,
923 
        REMAP_M0      => GND_net,
924 
        HMASTLOCK_M0  => GND_net, -- tied to '0' from definition
925 
        HWRITE_M0     => AHBMASTER_FIC_0_AHBmaster_HWRITE,
926 
        HMASTLOCK_M1  => GND_net, -- tied to '0' from definition
927 
        HWRITE_M1     => GND_net, -- tied to '0' from definition
928 
        HMASTLOCK_M2  => GND_net, -- tied to '0' from definition
929 
        HWRITE_M2     => GND_net, -- tied to '0' from definition
930 
        HMASTLOCK_M3  => GND_net, -- tied to '0' from definition
931 
        HWRITE_M3     => GND_net, -- tied to '0' from definition
932 
        HREADYOUT_S0  => CoreAHBLite_0_AHBmslave0_HREADYOUT,
933 
        HREADYOUT_S1  => VCC_net, -- tied to '1' from definition
934 
        HREADYOUT_S2  => VCC_net, -- tied to '1' from definition
935 
        HREADYOUT_S3  => VCC_net, -- tied to '1' from definition
936 
        HREADYOUT_S4  => VCC_net, -- tied to '1' from definition
937 
        HREADYOUT_S5  => VCC_net, -- tied to '1' from definition
938 
        HREADYOUT_S6  => VCC_net, -- tied to '1' from definition
939 
        HREADYOUT_S7  => VCC_net, -- tied to '1' from definition
940 
        HREADYOUT_S8  => VCC_net, -- tied to '1' from definition
941 
        HREADYOUT_S9  => VCC_net, -- tied to '1' from definition
942 
        HREADYOUT_S10 => VCC_net, -- tied to '1' from definition
943 
        HREADYOUT_S11 => VCC_net, -- tied to '1' from definition
944 
        HREADYOUT_S12 => VCC_net, -- tied to '1' from definition
945 
        HREADYOUT_S13 => VCC_net, -- tied to '1' from definition
946 
        HREADYOUT_S14 => VCC_net, -- tied to '1' from definition
947 
        HREADYOUT_S15 => VCC_net, -- tied to '1' from definition
948 
        HREADYOUT_S16 => VCC_net, -- tied to '1' from definition
949 
        HADDR_M0      => AHBMASTER_FIC_0_AHBmaster_HADDR,
950 
        HSIZE_M0      => AHBMASTER_FIC_0_AHBmaster_HSIZE,
951 
        HTRANS_M0     => AHBMASTER_FIC_0_AHBmaster_HTRANS,
952 
        HWDATA_M0     => AHBMASTER_FIC_0_AHBmaster_HWDATA,
953 
        HBURST_M0     => AHBMASTER_FIC_0_AHBmaster_HBURST,
954 
        HPROT_M0      => AHBMASTER_FIC_0_AHBmaster_HPROT,
955 
        HADDR_M1      => HADDR_M1_const_net_0, -- tied to X"0" from definition
956 
        HSIZE_M1      => HSIZE_M1_const_net_0, -- tied to X"0" from definition
957 
        HTRANS_M1     => HTRANS_M1_const_net_0, -- tied to X"0" from definition
958 
        HWDATA_M1     => HWDATA_M1_const_net_0, -- tied to X"0" from definition
959 
        HBURST_M1     => HBURST_M1_const_net_0, -- tied to X"0" from definition
960 
        HPROT_M1      => HPROT_M1_const_net_0, -- tied to X"0" from definition
961 
        HADDR_M2      => HADDR_M2_const_net_0, -- tied to X"0" from definition
962 
        HSIZE_M2      => HSIZE_M2_const_net_0, -- tied to X"0" from definition
963 
        HTRANS_M2     => HTRANS_M2_const_net_0, -- tied to X"0" from definition
964 
        HWDATA_M2     => HWDATA_M2_const_net_0, -- tied to X"0" from definition
965 
        HBURST_M2     => HBURST_M2_const_net_0, -- tied to X"0" from definition
966 
        HPROT_M2      => HPROT_M2_const_net_0, -- tied to X"0" from definition
967 
        HADDR_M3      => HADDR_M3_const_net_0, -- tied to X"0" from definition
968 
        HSIZE_M3      => HSIZE_M3_const_net_0, -- tied to X"0" from definition
969 
        HTRANS_M3     => HTRANS_M3_const_net_0, -- tied to X"0" from definition
970 
        HWDATA_M3     => HWDATA_M3_const_net_0, -- tied to X"0" from definition
971 
        HBURST_M3     => HBURST_M3_const_net_0, -- tied to X"0" from definition
972 
        HPROT_M3      => HPROT_M3_const_net_0, -- tied to X"0" from definition
973 
        HRDATA_S0     => CoreAHBLite_0_AHBmslave0_HRDATA,
974 
        HRESP_S0      => CoreAHBLite_0_AHBmslave0_HRESP,
975 
        HRDATA_S1     => HRDATA_S1_const_net_0, -- tied to X"0" from definition
976 
        HRESP_S1      => HRESP_S1_const_net_0, -- tied to X"0" from definition
977 
        HRDATA_S2     => HRDATA_S2_const_net_0, -- tied to X"0" from definition
978 
        HRESP_S2      => HRESP_S2_const_net_0, -- tied to X"0" from definition
979 
        HRDATA_S3     => HRDATA_S3_const_net_0, -- tied to X"0" from definition
980 
        HRESP_S3      => HRESP_S3_const_net_0, -- tied to X"0" from definition
981 
        HRDATA_S4     => HRDATA_S4_const_net_0, -- tied to X"0" from definition
982 
        HRESP_S4      => HRESP_S4_const_net_0, -- tied to X"0" from definition
983 
        HRDATA_S5     => HRDATA_S5_const_net_0, -- tied to X"0" from definition
984 
        HRESP_S5      => HRESP_S5_const_net_0, -- tied to X"0" from definition
985 
        HRDATA_S6     => HRDATA_S6_const_net_0, -- tied to X"0" from definition
986 
        HRESP_S6      => HRESP_S6_const_net_0, -- tied to X"0" from definition
987 
        HRDATA_S7     => HRDATA_S7_const_net_0, -- tied to X"0" from definition
988 
        HRESP_S7      => HRESP_S7_const_net_0, -- tied to X"0" from definition
989 
        HRDATA_S8     => HRDATA_S8_const_net_0, -- tied to X"0" from definition
990 
        HRESP_S8      => HRESP_S8_const_net_0, -- tied to X"0" from definition
991 
        HRDATA_S9     => HRDATA_S9_const_net_0, -- tied to X"0" from definition
992 
        HRESP_S9      => HRESP_S9_const_net_0, -- tied to X"0" from definition
993 
        HRDATA_S10    => HRDATA_S10_const_net_0, -- tied to X"0" from definition
994 
        HRESP_S10     => HRESP_S10_const_net_0, -- tied to X"0" from definition
995 
        HRDATA_S11    => HRDATA_S11_const_net_0, -- tied to X"0" from definition
996 
        HRESP_S11     => HRESP_S11_const_net_0, -- tied to X"0" from definition
997 
        HRDATA_S12    => HRDATA_S12_const_net_0, -- tied to X"0" from definition
998 
        HRESP_S12     => HRESP_S12_const_net_0, -- tied to X"0" from definition
999 
        HRDATA_S13    => HRDATA_S13_const_net_0, -- tied to X"0" from definition
1000 
        HRESP_S13     => HRESP_S13_const_net_0, -- tied to X"0" from definition
1001 
        HRDATA_S14    => HRDATA_S14_const_net_0, -- tied to X"0" from definition
1002 
        HRESP_S14     => HRESP_S14_const_net_0, -- tied to X"0" from definition
1003 
        HRDATA_S15    => HRDATA_S15_const_net_0, -- tied to X"0" from definition
1004 
        HRESP_S15     => HRESP_S15_const_net_0, -- tied to X"0" from definition
1005 
        HRDATA_S16    => HRDATA_S16_const_net_0, -- tied to X"0" from definition
1006 
        HRESP_S16     => HRESP_S16_const_net_0, -- tied to X"0" from definition
1007 
        -- Outputs
1008 
        HREADY_M0     => AHBMASTER_FIC_0_AHBmaster_HREADY,
1009 
        HREADY_M1     => OPEN,
1010 
        HREADY_M2     => OPEN,
1011 
        HREADY_M3     => OPEN,
1012 
        HSEL_S0       => CoreAHBLite_0_AHBmslave0_HSELx,
1013 
        HWRITE_S0     => CoreAHBLite_0_AHBmslave0_HWRITE,
1014 
        HREADY_S0     => CoreAHBLite_0_AHBmslave0_HREADY,
1015 
        HMASTLOCK_S0  => CoreAHBLite_0_AHBmslave0_HMASTLOCK,
1016 
        HSEL_S1       => OPEN,
1017 
        HWRITE_S1     => OPEN,
1018 
        HREADY_S1     => OPEN,
1019 
        HMASTLOCK_S1  => OPEN,
1020 
        HSEL_S2       => OPEN,
1021 
        HWRITE_S2     => OPEN,
1022 
        HREADY_S2     => OPEN,
1023 
        HMASTLOCK_S2  => OPEN,
1024 
        HSEL_S3       => OPEN,
1025 
        HWRITE_S3     => OPEN,
1026 
        HREADY_S3     => OPEN,
1027 
        HMASTLOCK_S3  => OPEN,
1028 
        HSEL_S4       => OPEN,
1029 
        HWRITE_S4     => OPEN,
1030 
        HREADY_S4     => OPEN,
1031 
        HMASTLOCK_S4  => OPEN,
1032 
        HSEL_S5       => OPEN,
1033 
        HWRITE_S5     => OPEN,
1034 
        HREADY_S5     => OPEN,
1035 
        HMASTLOCK_S5  => OPEN,
1036 
        HSEL_S6       => OPEN,
1037 
        HWRITE_S6     => OPEN,
1038 
        HREADY_S6     => OPEN,
1039 
        HMASTLOCK_S6  => OPEN,
1040 
        HSEL_S7       => OPEN,
1041 
        HWRITE_S7     => OPEN,
1042 
        HREADY_S7     => OPEN,
1043 
        HMASTLOCK_S7  => OPEN,
1044 
        HSEL_S8       => OPEN,
1045 
        HWRITE_S8     => OPEN,
1046 
        HREADY_S8     => OPEN,
1047 
        HMASTLOCK_S8  => OPEN,
1048 
        HSEL_S9       => OPEN,
1049 
        HWRITE_S9     => OPEN,
1050 
        HREADY_S9     => OPEN,
1051 
        HMASTLOCK_S9  => OPEN,
1052 
        HSEL_S10      => OPEN,
1053 
        HWRITE_S10    => OPEN,
1054 
        HREADY_S10    => OPEN,
1055 
        HMASTLOCK_S10 => OPEN,
1056 
        HSEL_S11      => OPEN,
1057 
        HWRITE_S11    => OPEN,
1058 
        HREADY_S11    => OPEN,
1059 
        HMASTLOCK_S11 => OPEN,
1060 
        HSEL_S12      => OPEN,
1061 
        HWRITE_S12    => OPEN,
1062 
        HREADY_S12    => OPEN,
1063 
        HMASTLOCK_S12 => OPEN,
1064 
        HSEL_S13      => OPEN,
1065 
        HWRITE_S13    => OPEN,
1066 
        HREADY_S13    => OPEN,
1067 
        HMASTLOCK_S13 => OPEN,
1068 
        HSEL_S14      => OPEN,
1069 
        HWRITE_S14    => OPEN,
1070 
        HREADY_S14    => OPEN,
1071 
        HMASTLOCK_S14 => OPEN,
1072 
        HSEL_S15      => OPEN,
1073 
        HWRITE_S15    => OPEN,
1074 
        HREADY_S15    => OPEN,
1075 
        HMASTLOCK_S15 => OPEN,
1076 
        HSEL_S16      => OPEN,
1077 
        HWRITE_S16    => OPEN,
1078 
        HREADY_S16    => OPEN,
1079 
        HMASTLOCK_S16 => OPEN,
1080 
        HRESP_M0      => AHBMASTER_FIC_0_AHBmaster_HRESP,
1081 
        HRDATA_M0     => AHBMASTER_FIC_0_AHBmaster_HRDATA,
1082 
        HRESP_M1      => OPEN,
1083 
        HRDATA_M1     => OPEN,
1084 
        HRESP_M2      => OPEN,
1085 
        HRDATA_M2     => OPEN,
1086 
        HRESP_M3      => OPEN,
1087 
        HRDATA_M3     => OPEN,
1088 
        HADDR_S0      => CoreAHBLite_0_AHBmslave0_HADDR,
1089 
        HSIZE_S0      => CoreAHBLite_0_AHBmslave0_HSIZE,
1090 
        HTRANS_S0     => CoreAHBLite_0_AHBmslave0_HTRANS,
1091 
        HWDATA_S0     => CoreAHBLite_0_AHBmslave0_HWDATA,
1092 
        HBURST_S0     => CoreAHBLite_0_AHBmslave0_HBURST,
1093 
        HPROT_S0      => CoreAHBLite_0_AHBmslave0_HPROT,
1094 
        HADDR_S1      => OPEN,
1095 
        HSIZE_S1      => OPEN,
1096 
        HTRANS_S1     => OPEN,
1097 
        HWDATA_S1     => OPEN,
1098 
        HBURST_S1     => OPEN,
1099 
        HPROT_S1      => OPEN,
1100 
        HADDR_S2      => OPEN,
1101 
        HSIZE_S2      => OPEN,
1102 
        HTRANS_S2     => OPEN,
1103 
        HWDATA_S2     => OPEN,
1104 
        HBURST_S2     => OPEN,
1105 
        HPROT_S2      => OPEN,
1106 
        HADDR_S3      => OPEN,
1107 
        HSIZE_S3      => OPEN,
1108 
        HTRANS_S3     => OPEN,
1109 
        HWDATA_S3     => OPEN,
1110 
        HBURST_S3     => OPEN,
1111 
        HPROT_S3      => OPEN,
1112 
        HADDR_S4      => OPEN,
1113 
        HSIZE_S4      => OPEN,
1114 
        HTRANS_S4     => OPEN,
1115 
        HWDATA_S4     => OPEN,
1116 
        HBURST_S4     => OPEN,
1117 
        HPROT_S4      => OPEN,
1118 
        HADDR_S5      => OPEN,
1119 
        HSIZE_S5      => OPEN,
1120 
        HTRANS_S5     => OPEN,
1121 
        HWDATA_S5     => OPEN,
1122 
        HBURST_S5     => OPEN,
1123 
        HPROT_S5      => OPEN,
1124 
        HADDR_S6      => OPEN,
1125 
        HSIZE_S6      => OPEN,
1126 
        HTRANS_S6     => OPEN,
1127 
        HWDATA_S6     => OPEN,
1128 
        HBURST_S6     => OPEN,
1129 
        HPROT_S6      => OPEN,
1130 
        HADDR_S7      => OPEN,
1131 
        HSIZE_S7      => OPEN,
1132 
        HTRANS_S7     => OPEN,
1133 
        HWDATA_S7     => OPEN,
1134 
        HBURST_S7     => OPEN,
1135 
        HPROT_S7      => OPEN,
1136 
        HADDR_S8      => OPEN,
1137 
        HSIZE_S8      => OPEN,
1138 
        HTRANS_S8     => OPEN,
1139 
        HWDATA_S8     => OPEN,
1140 
        HBURST_S8     => OPEN,
1141 
        HPROT_S8      => OPEN,
1142 
        HADDR_S9      => OPEN,
1143 
        HSIZE_S9      => OPEN,
1144 
        HTRANS_S9     => OPEN,
1145 
        HWDATA_S9     => OPEN,
1146 
        HBURST_S9     => OPEN,
1147 
        HPROT_S9      => OPEN,
1148 
        HADDR_S10     => OPEN,
1149 
        HSIZE_S10     => OPEN,
1150 
        HTRANS_S10    => OPEN,
1151 
        HWDATA_S10    => OPEN,
1152 
        HBURST_S10    => OPEN,
1153 
        HPROT_S10     => OPEN,
1154 
        HADDR_S11     => OPEN,
1155 
        HSIZE_S11     => OPEN,
1156 
        HTRANS_S11    => OPEN,
1157 
        HWDATA_S11    => OPEN,
1158 
        HBURST_S11    => OPEN,
1159 
        HPROT_S11     => OPEN,
1160 
        HADDR_S12     => OPEN,
1161 
        HSIZE_S12     => OPEN,
1162 
        HTRANS_S12    => OPEN,
1163 
        HWDATA_S12    => OPEN,
1164 
        HBURST_S12    => OPEN,
1165 
        HPROT_S12     => OPEN,
1166 
        HADDR_S13     => OPEN,
1167 
        HSIZE_S13     => OPEN,
1168 
        HTRANS_S13    => OPEN,
1169 
        HWDATA_S13    => OPEN,
1170 
        HBURST_S13    => OPEN,
1171 
        HPROT_S13     => OPEN,
1172 
        HADDR_S14     => OPEN,
1173 
        HSIZE_S14     => OPEN,
1174 
        HTRANS_S14    => OPEN,
1175 
        HWDATA_S14    => OPEN,
1176 
        HBURST_S14    => OPEN,
1177 
        HPROT_S14     => OPEN,
1178 
        HADDR_S15     => OPEN,
1179 
        HSIZE_S15     => OPEN,
1180 
        HTRANS_S15    => OPEN,
1181 
        HWDATA_S15    => OPEN,
1182 
        HBURST_S15    => OPEN,
1183 
        HPROT_S15     => OPEN,
1184 
        HADDR_S16     => OPEN,
1185 
        HSIZE_S16     => OPEN,
1186 
        HTRANS_S16    => OPEN,
1187 
        HWDATA_S16    => OPEN,
1188 
        HBURST_S16    => OPEN,
1189 
        HPROT_S16     => OPEN
1190 
        );
1191 
-- CoreAPB_0   -   Actel:DirectCore:CoreAPB:1.1.101
1192 
CoreAPB_0 : CoreAPB
1193 
    generic map(
1194 
        ApbSlot0Enable  => ( 1 ),
1195 
        ApbSlot1Enable  => ( 0 ),
1196 
        ApbSlot2Enable  => ( 0 ),
1197 
        ApbSlot3Enable  => ( 0 ),
1198 
        ApbSlot4Enable  => ( 0 ),
1199 
        ApbSlot5Enable  => ( 0 ),
1200 
        ApbSlot6Enable  => ( 0 ),
1201 
        ApbSlot7Enable  => ( 0 ),
1202 
        ApbSlot8Enable  => ( 0 ),
1203 
        ApbSlot9Enable  => ( 0 ),
1204 
        ApbSlot10Enable => ( 0 ),
1205 
        ApbSlot11Enable => ( 0 ),
1206 
        ApbSlot12Enable => ( 0 ),
1207 
        ApbSlot13Enable => ( 0 ),
1208 
        ApbSlot14Enable => ( 0 ),
1209 
        ApbSlot15Enable => ( 0 )
1210 
        )
1211 
    port map(
1212 
        -- Inputs
1213 
        PWRITE    => CoreAHB2APB_0_APBmaster_PWRITE,
1214 
        PENABLE   => CoreAHB2APB_0_APBmaster_PENABLE,
1215 
        PADDR     => CoreAHB2APB_0_APBmaster_PADDR,
1216 
        PWDATA    => CoreAHB2APB_0_APBmaster_PWDATA,
1217 
        PSELECT   => CoreAHB2APB_0_APBmaster_PSELx,
1218 
        PRDATAS0  => CoreAPB_0_APBmslave0_PRDATA_0,
1219 
        PRDATAS1  => PRDATAS1_const_net_0, -- tied to X"0" from definition
1220 
        PRDATAS2  => PRDATAS2_const_net_0, -- tied to X"0" from definition
1221 
        PRDATAS3  => PRDATAS3_const_net_0, -- tied to X"0" from definition
1222 
        PRDATAS4  => PRDATAS4_const_net_0, -- tied to X"0" from definition
1223 
        PRDATAS5  => PRDATAS5_const_net_0, -- tied to X"0" from definition
1224 
        PRDATAS6  => PRDATAS6_const_net_0, -- tied to X"0" from definition
1225 
        PRDATAS7  => PRDATAS7_const_net_0, -- tied to X"0" from definition
1226 
        PRDATAS8  => PRDATAS8_const_net_0, -- tied to X"0" from definition
1227 
        PRDATAS9  => PRDATAS9_const_net_0, -- tied to X"0" from definition
1228 
        PRDATAS10 => PRDATAS10_const_net_0, -- tied to X"0" from definition
1229 
        PRDATAS11 => PRDATAS11_const_net_0, -- tied to X"0" from definition
1230 
        PRDATAS12 => PRDATAS12_const_net_0, -- tied to X"0" from definition
1231 
        PRDATAS13 => PRDATAS13_const_net_0, -- tied to X"0" from definition
1232 
        PRDATAS14 => PRDATAS14_const_net_0, -- tied to X"0" from definition
1233 
        PRDATAS15 => PRDATAS15_const_net_0, -- tied to X"0" from definition
1234 
        -- Outputs
1235 
        PWRITES   => CoreAPB_0_APBmslave0_PWRITE,
1236 
        PENABLES  => CoreAPB_0_APBmslave0_PENABLE,
1237 
        PSELS0    => CoreAPB_0_APBmslave0_PSELx,
1238 
        PSELS1    => OPEN,
1239 
        PSELS2    => OPEN,
1240 
        PSELS3    => OPEN,
1241 
        PSELS4    => OPEN,
1242 
        PSELS5    => OPEN,
1243 
        PSELS6    => OPEN,
1244 
        PSELS7    => OPEN,
1245 
        PSELS8    => OPEN,
1246 
        PSELS9    => OPEN,
1247 
        PSELS10   => OPEN,
1248 
        PSELS11   => OPEN,
1249 
        PSELS12   => OPEN,
1250 
        PSELS13   => OPEN,
1251 
        PSELS14   => OPEN,
1252 
        PSELS15   => OPEN,
1253 
        PRDATA    => CoreAHB2APB_0_APBmaster_PRDATA,
1254 
        PADDRS    => CoreAPB_0_APBmslave0_PADDR,
1255 
        PWDATAS   => CoreAPB_0_APBmslave0_PWDATA
1256 
        );
1257 
-- CoreUARTapb_0   -   Actel:DirectCore:CoreUARTapb:5.6.102
1258 
CoreUARTapb_0 : top_CoreUARTapb_0_CoreUARTapb
1259 
    generic map(
1260 
        BAUD_VAL_FRCTN    => ( 0 ),
1261 
        BAUD_VAL_FRCTN_EN => ( 0 ),
1262 
        BAUD_VALUE        => ( 1 ),
1263 
        FAMILY            => ( 15 ),
1264 
        FIXEDMODE         => ( 1 ),
1265 
        PRG_BIT8          => ( 1 ),
1266 
        PRG_PARITY        => ( 0 ),
1267 
        RX_FIFO           => ( 0 ),
1268 
        RX_LEGACY_MODE    => ( 0 ),
1269 
        TX_FIFO           => ( 0 )
1270 
        )
1271 
    port map(
1272 
        -- Inputs
1273 
        PCLK        => HCLK,
1274 
        PRESETN     => HRESETn,
1275 
        PSEL        => CoreAPB_0_APBmslave0_PSELx,
1276 
        PENABLE     => CoreAPB_0_APBmslave0_PENABLE,
1277 
        PWRITE      => CoreAPB_0_APBmslave0_PWRITE,
1278 
        RX          => VCC_net,
1279 
        PADDR       => CoreAPB_0_APBmslave0_PADDR_0,
1280 
        PWDATA      => CoreAPB_0_APBmslave0_PWDATA_0,
1281 
        -- Outputs
1282 
        TXRDY       => OPEN,
1283 
        RXRDY       => OPEN,
1284 
        PARITY_ERR  => OPEN,
1285 
        OVERFLOW    => OPEN,
1286 
        TX          => TX_net_0,
1287 
        PREADY      => CoreAPB_0_APBmslave0_PREADY,
1288 
        PSLVERR     => CoreAPB_0_APBmslave0_PSLVERR,
1289 
        FRAMING_ERR => OPEN,
1290 
        PRDATA      => CoreAPB_0_APBmslave0_PRDATA
1291 
        );
1292 
 
1293 
end RTL;

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