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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [simulation/] [modelsim.ini.sav] - Blame information for rev 3

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[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = C:/Microsemi/Libero_SoC_v11.8/Designer/lib/modelsim/precompiled/vhdl/proasic3
postsynth = postsynth
COREAHBLITE_LIB = ../component/Actel/DirectCore/CoreAHBLite/5.3.101/mti/user_vhdl/COREAHBLITE_LIB
COREUARTAPB_LIB = COREUARTAPB_LIB
syncad_vhdl_lib = C:\Microsemi\Libero_SoC_v11.8\Designer/lib/actel/syncad_vhdl_lib
 
[vcom]
VHDL93 = 1
 
[vsim]
IterationLimit = 5000

Line No.	Rev	Author	Line
1	3	uson	`[Library]`
2			`others = $MODEL_TECH/../modelsim.ini`
3			`proasic3 = C:/Microsemi/Libero_SoC_v11.8/Designer/lib/modelsim/precompiled/vhdl/proasic3`
4			`postsynth = postsynth`
5			`COREAHBLITE_LIB = ../component/Actel/DirectCore/CoreAHBLite/5.3.101/mti/user_vhdl/COREAHBLITE_LIB`
6			`COREUARTAPB_LIB = COREUARTAPB_LIB`
7			`syncad_vhdl_lib = C:\Microsemi\Libero_SoC_v11.8\Designer/lib/actel/syncad_vhdl_lib`
8
9			`[vcom]`
10			`VHDL93 = 1`
11
12			`[vsim]`
13			`IterationLimit = 5000`

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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [simulation/] [modelsim.ini.sav] - Blame information for rev 3