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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synlog/] [report/] [top_premap_warnings.txt] - Blame information for rev 3

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1 3 uson
@W: MT530 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Found inferred clock top|HCLK which controls 472 sequential elements including AHBMASTER_FIC_0.HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance.

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