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URL https://opencores.org/ocsvn/ahbmaster/ahbmaster/trunk

Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synwork/] [layer0.fdeporig] - Blame information for rev 3

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1 3 uson
#defaultlanguage:vhdl
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#OPTIONS:"|-layerid|0|-orig_srs|C:\\Actelprj\\test79_AHBmaster\\synthesis\\synwork\\top_comp.srs|-top|work.top|-prodtype|synplify_pro|-nram|-fixsmult|-divnmod|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREAHBLITE_LIB|-lib|COREUARTAPB_LIB|-lib|work"
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\bin64\\c_vhdl.exe":1479949892
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\location.map":1478775588
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std.vhd":1487912986
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\snps_haps_pkg.vhd":1487912854
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std1164.vhd":1487912986
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std_textio.vhd":1487912986
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\numeric.vhd":1487912986
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\umr_capim.vhd":1487912854
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\arith.vhd":1487912986
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\unsigned.vhd":1487912986
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#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\hyperents.vhd":1487912854
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\hdl\\AHBMASTER_FIC.vhd":1527947376
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHB2APB\\1.1.101\\rtl\\vhdl\\u\\CoreAHB2APB.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAPB\\1.1.101\\rtl\\vhdl\\o\\MuxP2B.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAPB\\1.1.101\\rtl\\vhdl\\o\\CoreAPB.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_addrdec.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_defaultslavesm.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_masterstage.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_slavearbiter.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_slavestage.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_matrix4x16.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_pkg.vhd":1527947216
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreAHBLite_0\\rtl\\vhdl\\core\\coreahblite.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Clock_gen.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Rx_async.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Tx_async.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\fifo_256x8_pa3.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\coreuart_pkg.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\CoreUART.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\CoreUARTapb.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreAHBLite_0\\rtl\\vhdl\\core\\components.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\components.vhd":1527947577
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#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\top.vhd":1527947577
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1 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd" vhdl
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2 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd" vhdl
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3 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd" vhdl
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4 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd" vhdl
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5 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd" vhdl
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6 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd" vhdl
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7 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd" vhdl
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8 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd" vhdl
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9 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd" vhdl
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10 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd" vhdl
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11 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd" vhdl
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12 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd" vhdl
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13 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd" vhdl
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14 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd" vhdl
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15 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd" vhdl
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16 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd" vhdl
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17 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd" vhdl
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18 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd" vhdl
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19 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd" vhdl
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20 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd" vhdl
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21 "C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd" vhdl
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# Dependency Lists (Uses list)
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1 -1
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2 -1
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3 2
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4 -1
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5 -1
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6 4 5
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7 -1
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8 7
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9 6 8
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10 -1
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11 9 10
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12 -1
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13 -1
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14 -1
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15 -1
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16 -1
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17 12 14 13 15 16
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18 17 16
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19 -1
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20 -1
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21 0 1 11 3 18 19 20
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# Dependency Lists (Users Of)
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1 21
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2 3
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3 21
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4 6
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5 6
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6 9
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7 8
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8 9
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9 11
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10 11
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11 21
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12 17
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13 17
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14 17
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15 17
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16 18 17
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17 18
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18 21
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19 21
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20 21
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21 -1
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# Design Unit to File Association
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arch work ahbmaster_fic rtl 0
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module work ahbmaster_fic 0
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arch work coreahb2apb synth 1
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module work coreahb2apb 1
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arch work coreapb_l coreapb_li0 2
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module work coreapb_l 2
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arch work coreapb coreapb_o 3
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module work coreapb 3
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arch coreahblite_lib coreahblite_addrdec coreahblite_addrdec_arch 4
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module coreahblite_lib coreahblite_addrdec 4
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arch coreahblite_lib coreahblite_defaultslavesm coreahblite_defaultslavesm_arch 5
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module coreahblite_lib coreahblite_defaultslavesm 5
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arch coreahblite_lib coreahblite_masterstage coreahblite_masterstage_arch 6
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module coreahblite_lib coreahblite_masterstage 6
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arch coreahblite_lib coreahblite_slavearbiter coreahblite_slavearbiter_arch 7
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module coreahblite_lib coreahblite_slavearbiter 7
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arch coreahblite_lib coreahblite_slavestage trans 8
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module coreahblite_lib coreahblite_slavestage 8
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arch coreahblite_lib coreahblite_matrix4x16 coreahblite_matrix4x16_arch 9
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module coreahblite_lib coreahblite_matrix4x16 9
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arch coreahblite_lib top_coreahblite_0_coreahblite coreahblite_arch 11
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module coreahblite_lib top_coreahblite_0_coreahblite 11
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arch coreuartapb_lib top_coreuartapb_0_clock_gen rtl 12
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module coreuartapb_lib top_coreuartapb_0_clock_gen 12
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arch coreuartapb_lib top_coreuartapb_0_rx_async translated 13
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module coreuartapb_lib top_coreuartapb_0_rx_async 13
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arch coreuartapb_lib top_coreuartapb_0_tx_async translated 14
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module coreuartapb_lib top_coreuartapb_0_tx_async 14
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arch coreuartapb_lib top_coreuartapb_0_fifo_256x8_pa3 translated 15
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module coreuartapb_lib top_coreuartapb_0_fifo_256x8_pa3 15
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arch coreuartapb_lib top_coreuartapb_0_fifo_256x8 translated 15
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module coreuartapb_lib top_coreuartapb_0_fifo_256x8 15
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arch coreuartapb_lib top_coreuartapb_0_coreuart translated 17
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module coreuartapb_lib top_coreuartapb_0_coreuart 17
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arch coreuartapb_lib top_coreuartapb_0_coreuartapb translated 18
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module coreuartapb_lib top_coreuartapb_0_coreuartapb 18
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arch work top rtl 21
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module work top 21

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