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[/] [altor32/] [trunk/] [docs/] [altor_spr.md] - Blame information for rev 41

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1 41 ultra_embe 
AltOR32 SPR Registers
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=====================
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### SPR_REG_VR
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##### Description
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Version register.
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##### Encoding
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`SPR_ADDR = 0x0000`
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### SPR_REG_SR
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##### Description
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Status register (SR)
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##### Encoding
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`SPR_ADDR = 0x0011`
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### SPR_REG_EPC
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##### Description
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Saved (prior to exception) PC register (EPC).
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##### Encoding
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`SPR_ADDR = 0x0020`
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### SPR_REG_ESR
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##### Description
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Saved (prior to exception) status (SR) register (ESR).
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##### Encoding
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`SPR_ADDR = 0x0040`
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### SR - Status Register
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| Bit    | Description                    |
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| ------ | -------------------------------|
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| 2      | Interrupt enable.              |
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| 9      | Flag status.                   |
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| 10     | Carry out status.              |
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| 17     | Instruction cache flush.       |
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| 18     | Data cache flush.              |

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