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[/] [altor32/] [trunk/] [or1k-sim/] [or32_inst_dump.cpp] - Blame information for rev 30

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1 28 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4
//                            V2.0
5
//                     Ultra-Embedded.com
6
//                   Copyright 2011 - 2013
7
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
14
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
#include <stdio.h>
38
#include <string.h>
39
#include <stdlib.h>
40
#include <assert.h>
41
#include "or32_isa.h"
42
#include "or32_inst_dump.h"
43
 
44
//-----------------------------------------------------------------
45
// or32_instruction_to_string: Decode instruction to string
46
//-----------------------------------------------------------------
47
int or32_instruction_to_string(TRegister opcode, char *output, int max_len)
48
{
49
    TRegister v_ra = 0;
50
    TRegister v_rb = 0;
51
    TRegister v_rd = 0;
52
    TRegister v_inst = 0;
53
    TRegister v_op = 0;
54
    TRegister v_target = 0;
55
    TRegister v_pc = 0;
56
    TRegister v_pc_next = 0;
57
    TRegister v_imm = 0;
58
    TRegister v_imm_uint32 = 0;
59
    TRegister v_imm_int32 = 0;
60
    TRegister v_offset = 0;
61
    TRegister v_store_imm = 0;
62
    int v_branch = 0;
63
    int v_jmp = 0;
64
 
65
    TRegister v_alu_op = 0;
66
    TRegister v_shift_op = 0;
67
    TRegister v_sfxx_op = 0;
68
 
69
    // Decode opcode
70
    v_inst      = (opcode >> OR32_OPCODE_SHIFT) & OR32_OPCODE_MASK;
71
    v_rd        = (opcode >> OR32_REG_D_SHIFT) & OR32_REG_D_MASK;
72
    v_ra        = (opcode >> OR32_REG_A_SHIFT) & OR32_REG_A_MASK;
73
    v_rb        = (opcode >> OR32_REG_B_SHIFT) & OR32_REG_B_MASK;
74
    v_imm       = (opcode >> OR32_IMM16_SHIFT) & OR32_IMM16_MASK;
75
    v_target    = (opcode >> OR32_ADDR_SHIFT) & OR32_ADDR_MASK;
76
    v_sfxx_op   = (opcode >> OR32_SFXXX_OP_SHIFT) & OR32_SFXXX_OP_MASK;
77
    v_alu_op    = (opcode >> OR32_ALU_OP_L_SHIFT) & OR32_ALU_OP_L_MASK;
78
    v_alu_op   |= (opcode >> OR32_ALU_OP_H_SHIFT) & OR32_ALU_OP_H_MASK;
79
    v_shift_op  = (opcode >> OR32_SHIFT_OP_SHIFT) & OR32_SHIFT_OP_MASK;
80
    v_store_imm = (opcode >> OR32_STORE_IMM_L_SHIFT) & OR32_STORE_IMM_L_MASK;
81
    v_store_imm|= (opcode >> OR32_STORE_IMM_H_SHIFT) & OR32_STORE_IMM_H_MASK;
82
 
83
    // Sign extend store immediate
84
    v_store_imm = (unsigned int)(signed short)v_store_imm;
85
 
86
    // Sign extend target immediate
87
    if (v_target & (1 << 25))
88
        v_target |= ~OR32_ADDR_MASK;
89
 
90
    // Signed & unsigned imm -> 32-bits
91
    v_imm_int32 = (unsigned int)(signed short)v_imm;
92
    v_imm_uint32 = v_imm;
93
 
94
    output[0] = 0;
95
 
96
    // Execute instruction
97
    switch(v_inst)
98
    {
99
        case INST_OR32_ALU:
100
            switch (v_alu_op)
101
            {
102
                case INST_OR32_ADD: // l.add
103
                    sprintf(output, "l.add   r%d,r%d,r%d", v_rd, v_ra, v_rb);
104
                break;
105
                case INST_OR32_ADDC: // l.addc
106
                    sprintf(output, "l.addc  r%d,r%d,r%d", v_rd, v_ra, v_rb);
107
                break;
108
                case INST_OR32_AND: // l.and
109
                    sprintf(output, "l.and   r%d,r%d,r%d", v_rd, v_ra, v_rb);
110
                break;
111
                case INST_OR32_OR: // l.or
112
                    sprintf(output, "l.or    r%d,r%d,r%d", v_rd, v_ra, v_rb);
113
                break;
114
                case INST_OR32_SLL: // l.sll
115
                    sprintf(output, "l.sll   r%d,r%d,r%d", v_rd, v_ra, v_rb);
116
                break;
117
                case INST_OR32_SRA: // l.sra
118
                    sprintf(output, "l.sra   r%d,r%d,r%d", v_rd, v_ra, v_rb);
119
                break;
120
                case INST_OR32_SRL: // l.srl
121
                    sprintf(output, "l.srl   r%d,r%d,r%d", v_rd, v_ra, v_rb);
122
                break;
123
                case INST_OR32_SUB: // l.sub
124
                    sprintf(output, "l.sub   r%d,r%d,r%d", v_rd, v_ra, v_rb);
125
                break;
126
                case INST_OR32_XOR: // l.xor
127
                    sprintf(output, "l.xor   r%d,r%d,r%d", v_rd, v_ra, v_rb);
128
                break;
129
                case INST_OR32_MUL: // l.mul
130
                    sprintf(output, "l.mul   r%d,r%d,r%d", v_rd, v_ra, v_rb);
131
                break;
132
                case INST_OR32_MULU: // l.mulu
133
                    sprintf(output, "l.mulu  r%d,r%d,r%d", v_rd, v_ra, v_rb);
134
                break;
135
            }
136
        break;
137
 
138
        case INST_OR32_ADDI: // l.addi 
139
            if ((int)v_imm_int32 < 0)
140
                sprintf(output, "l.addi  r%d,r%d,%d", v_rd, v_ra, v_imm_int32);
141
            else
142
                sprintf(output, "l.addi  r%d,r%d,0x%x", v_rd, v_ra, v_imm_int32);
143
        break;
144
 
145
        case INST_OR32_ANDI: // l.andi
146
            sprintf(output, "l.andi  r%d,r%d,0x%x", v_rd, v_ra, v_imm_uint32);
147
        break;
148
 
149
        case INST_OR32_BF: // l.bf
150
            if ((int)v_target <= 0)
151
                sprintf(output, "l.bf    %d", (int)v_target);
152
            else
153
                sprintf(output, "l.bf    0x%x", (int)v_target);
154
        break;
155
 
156
        case INST_OR32_BNF: // l.bnf
157
            if ((int)v_target <= 0)
158
                sprintf(output, "l.bnf   %d", (int)v_target);
159
            else
160
                sprintf(output, "l.bnf   0x%x", (int)v_target);
161
        break;
162
 
163
        case INST_OR32_J: // l.j
164
            if ((int)v_target <= 0)
165
                sprintf(output, "l.j     %d", (int)v_target);
166
            else
167
                sprintf(output, "l.j     0x%x", (int)v_target);
168
        break;
169
 
170
        case INST_OR32_JAL: // l.jal
171
            if ((int)v_target <= 0)
172
                sprintf(output, "l.jal   %d", (int)v_target);
173
            else
174
                sprintf(output, "l.jal   0x%x", (int)v_target);
175
        break;
176
 
177
        case INST_OR32_JALR: // l.jalr
178
            sprintf(output, "l.jalr  r%d", v_rb);
179
        break;
180
 
181
        case INST_OR32_JR: // l.jr
182
            sprintf(output, "l.jr    r%d", v_rb);
183
        break;
184
 
185
        case INST_OR32_LBS: // l.lbs
186
            if ((int)v_imm_int32 < 0)
187
                sprintf(output, "l.lbs   r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
188
            else
189
                sprintf(output, "l.lbs   r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
190
        break;
191
 
192
        case INST_OR32_LHS: // l.lhs
193
            if ((int)v_imm_int32 < 0)
194
                sprintf(output, "l.lhs   r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
195
            else
196
                sprintf(output, "l.lhs   r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
197
        break;
198
 
199
        case INST_OR32_LWS: // l.lws
200
            if ((int)v_imm_int32 < 0)
201
                sprintf(output, "l.lws   r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
202
            else
203
                sprintf(output, "l.lws   r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
204
        break;
205
 
206
        case INST_OR32_LBZ: // l.lbz
207
            if ((int)v_imm_int32 < 0)
208
                sprintf(output, "l.lbz   r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
209
            else
210
                sprintf(output, "l.lbz   r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
211
        break;
212
 
213
        case INST_OR32_LHZ: // l.lhz
214
            if ((int)v_imm_int32 < 0)
215
                sprintf(output, "l.lhz   r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
216
            else
217
                sprintf(output, "l.lhz   r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
218
        break;
219
 
220
        case INST_OR32_LWZ: // l.lwz
221
            if ((int)v_imm_int32 < 0)
222
                sprintf(output, "l.lwz   r%d,%d(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
223
            else
224
                sprintf(output, "l.lwz   r%d,0x%x(r%d)", v_rd, (int)v_imm_int32, v_ra, v_rd);
225
        break;
226
 
227
        case INST_OR32_MFSPR: // l.mfspr
228
        break;
229
 
230
        case INST_OR32_MOVHI: // l.movhi
231
            if (v_imm_uint32 == 0)
232
                sprintf(output, "l.movhi r%d,%d", v_rd, v_imm_uint32);
233
            else
234
                sprintf(output, "l.movhi r%d,0x%x", v_rd, v_imm_uint32);
235
        break;
236
 
237
        case INST_OR32_MTSPR: // l.mtspr
238
        break;
239
 
240
        case INST_OR32_NOP: // l.nop
241
            if (v_imm != 0)
242
                sprintf(output, "l.nop   0x%x", v_imm);
243
            else
244
                sprintf(output, "l.nop   0");
245
        break;
246
 
247
        case INST_OR32_ORI: // l.ori
248
            if (v_imm_uint32 == 0)
249
                sprintf(output, "l.ori   r%d,r%d,%d", v_rd, v_ra, v_imm_uint32);
250
            else
251
                sprintf(output, "l.ori   r%d,r%d,0x%x", v_rd, v_ra, v_imm_uint32);
252
        break;
253
 
254
        case INST_OR32_RFE: // l.rfe
255
            sprintf(output, "l.rfe");
256
        break;
257
 
258
        case INST_OR32_SHIFTI:
259
            switch (v_shift_op)
260
            {
261
                case INST_OR32_SLLI: // l.slli
262
                    sprintf(output, "l.slli  r%d,r%d,0x%x", v_rd, v_ra, (opcode & 0x3F));
263
                break;
264
                case INST_OR32_SRAI: // l.srai
265
                    sprintf(output, "l.srai  r%d,r%d,0x%x", v_rd, v_ra, (opcode & 0x3F));
266
                break;
267
                case INST_OR32_SRLI: // l.srli
268
                    sprintf(output, "l.srli  r%d,r%d,0x%x", v_rd, v_ra, (opcode & 0x3F));
269
                break;
270
            }
271
        break;
272
 
273
        case INST_OR32_SB: // l.sb
274
            if ((int)v_store_imm < 0)
275
                sprintf(output, "l.sb    %d(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
276
            else
277
                sprintf(output, "l.sb    0x%x(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
278
        break;
279
 
280
        case INST_OR32_SFXX:
281
        case INST_OR32_SFXXI:
282
            switch (v_sfxx_op)
283
            {
284
                case INST_OR32_SFEQ: // l.sfeq
285
                    sprintf(output, "l.sfeq  r%d,r%d", v_ra, v_rb);
286
                break;
287
                case INST_OR32_SFEQI: // l.sfeqi
288
                    sprintf(output, "l.sfeqi r%d,0x%x", v_ra, (int)v_imm_int32);
289
                break;
290
                case INST_OR32_SFGES: // l.sfges
291
                    sprintf(output, "l.sfges r%d,r%d", v_ra, v_rb);
292
                break;
293
                case INST_OR32_SFGESI: // l.sfgesi
294
                    sprintf(output, "l.sfgesi r%d,0x%x", v_ra, (int)v_imm_int32);
295
                break;
296
                case INST_OR32_SFGEU: // l.sfgeu
297
                    sprintf(output, "l.sfgeu r%d,r%d", v_ra, v_rb);
298
                break;
299
                case INST_OR32_SFGEUI: // l.sfgeui
300
                    sprintf(output, "l.sfgeui r%d,0x%x", v_ra, v_imm_uint32);
301
                break;
302
                case INST_OR32_SFGTS: // l.sfgts
303
                    sprintf(output, "l.sfgts r%d,r%d", v_ra, v_rb);
304
                break;
305
                case INST_OR32_SFGTSI: // l.sfgtsi
306
                    sprintf(output, "l.sfgtsi r%d,0x%x", v_ra, (int)v_imm_int32);
307
                break;
308
                case INST_OR32_SFGTU: // l.sfgtu
309
                    sprintf(output, "l.sfgtu r%d,r%d", v_ra, v_rb);
310
                break;
311
                case INST_OR32_SFGTUI: // l.sfgtui
312
                    sprintf(output, "l.sfgtui r%d,0x%x", v_ra, v_imm_uint32);
313
                break;
314
                case INST_OR32_SFLES: // l.sfles
315
                    sprintf(output, "l.sfles r%d,r%d", v_ra, v_rb);
316
                break;
317
                case INST_OR32_SFLESI: // l.sflesi
318
                    sprintf(output, "l.sflesi r%d,0x%x", v_ra, (int)v_imm_int32);
319
                break;
320
                case INST_OR32_SFLEU: // l.sfleu
321
                    sprintf(output, "l.sfleu r%d,r%d", v_ra, v_rb);
322
                break;
323
                case INST_OR32_SFLEUI: // l.sfleui
324
                    sprintf(output, "l.sfleui r%d,0x%x", v_ra, v_imm_uint32);
325
                break;
326
                case INST_OR32_SFLTS: // l.sflts
327
                    sprintf(output, "l.sflts r%d,r%d", v_ra, v_rb);
328
                break;
329
                case INST_OR32_SFLTSI: // l.sfltsi
330
                    sprintf(output, "l.sfltsi r%d,0x%x", v_ra, (int)v_imm_int32);
331
                break;
332
                case INST_OR32_SFLTU: // l.sfltu
333
                    sprintf(output, "l.sfltu r%d,r%d", v_ra, v_rb);
334
                break;
335
                case INST_OR32_SFLTUI: // l.sfltui
336
                    sprintf(output, "l.sfltui r%d,0x%x", v_ra, v_imm_uint32);
337
                break;
338
                case INST_OR32_SFNE: // l.sfne
339
                    sprintf(output, "l.sfne  r%d,r%d", v_ra, v_rb);
340
                break;
341
                case INST_OR32_SFNEI: // l.sfnei
342
                    sprintf(output, "l.sfnei  r%d,0x%x", v_ra, v_imm_uint32);
343
                break;
344
            }
345
        break;
346
 
347
        case INST_OR32_SH: // l.sh
348
            if ((int)v_store_imm < 0)
349
                sprintf(output, "l.sh    %d(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
350
            else
351
                sprintf(output, "l.sh    0x%x(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
352
        break;
353
 
354
        case INST_OR32_SW: // l.sw
355
            if ((int)v_store_imm < 0)
356
                sprintf(output, "l.sw    %d(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
357
            else
358
                sprintf(output, "l.sw    0x%x(r%d),r%d", (int)v_store_imm, v_ra, v_rb);
359
        break;
360
 
361
        case INST_OR32_MISC:
362
            switch (opcode >> 24)
363
            {
364
                case INST_OR32_SYS: // l.sys
365
                    sprintf(output, "l.sys");
366
                break;
367
 
368
                case INST_OR32_TRAP: // l.trap
369
                    sprintf(output, "l.trap");
370
                break;
371
            }
372
        break;
373
 
374
        case INST_OR32_XORI: // l.xori
375
            if ((int)v_imm_int32 < 0)
376
                sprintf(output, "l.xori  r%d,r%d,%d", v_rd, v_ra, v_imm_int32);
377
            else
378
                sprintf(output, "l.xori  r%d,r%d,0x%x", v_rd, v_ra, v_imm_int32);
379
        break;
380
   }
381
 
382
   return (output[0] != 0);
383
}
384
//-----------------------------------------------------------------
385
// or32_instruction_to_string: Decode instruction to string
386
//-----------------------------------------------------------------
387
void or32_instruction_dump(TRegister pc, TRegister opcode, TRegister gpr[REGISTERS], TRegister rd, TRegister result, TRegister sr)
388
{
389
    char output[1024];
390
 
391
    // Decode opcode in-order to perform register reads
392
    TRegister ra = (opcode >> OR32_REG_A_SHIFT) & OR32_REG_A_MASK;
393
    TRegister rb = (opcode >> OR32_REG_B_SHIFT) & OR32_REG_B_MASK;
394
    TRegister v_inst = (opcode >> OR32_OPCODE_SHIFT) & OR32_OPCODE_MASK;
395
 
396
    TRegister v_store_imm = (opcode >> OR32_STORE_IMM_L_SHIFT) & OR32_STORE_IMM_L_MASK;
397
    v_store_imm|= (opcode >> OR32_STORE_IMM_H_SHIFT) & OR32_STORE_IMM_H_MASK;
398
    v_store_imm = (unsigned int)(signed short)v_store_imm;
399
 
400
    // Decode instruction in or1ksim trace format
401
    or32_instruction_to_string(opcode, output, sizeof(output)-1);
402
 
403
    if (rd != 0 && v_inst != INST_OR32_JAL && v_inst != INST_OR32_JALR)
404
        printf("S %08x: %08x %-23s r%d         = %08x  flag: %d\n", pc, opcode, output, rd, result, sr & OR32_SR_F_BIT ? 1: 0);
405
    else if (v_inst == INST_OR32_SB || v_inst == INST_OR32_SH || v_inst == INST_OR32_SW)
406
    {
407
        if (v_inst == INST_OR32_SB)
408
            printf("S %08x: %08x %-23s [%08x] = %02x  flag: %d\n", pc, opcode, output, gpr[ra] + (int)v_store_imm, gpr[rb], sr & OR32_SR_F_BIT ? 1: 0);
409
        else if (v_inst == INST_OR32_SH)
410
            printf("S %08x: %08x %-23s [%08x] = %04x  flag: %d\n", pc, opcode, output, gpr[ra] + (int)v_store_imm, gpr[rb], sr & OR32_SR_F_BIT ? 1: 0);
411
        else
412
            printf("S %08x: %08x %-23s [%08x] = %08x  flag: %d\n", pc, opcode, output, gpr[ra] + (int)v_store_imm, gpr[rb], sr & OR32_SR_F_BIT ? 1: 0);
413
    }
414
    else
415
        printf("S %08x: %08x %-45s  flag: %d\n", pc, opcode, output, sr & OR32_SR_F_BIT ? 1: 0);
416
}

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