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//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.0
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2013
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
 
//-----------------------------------------------------------------
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
//-----------------------------------------------------------------
module cpu
(
    // General
    input               clk_i /*verilator public*/,
    input               rst_i /*verilator public*/,
 
    input               intr_i /*verilator public*/,
    input               nmi_i /*verilator public*/,
    output              fault_o /*verilator public*/,
    output              break_o /*verilator public*/,
 
    // Instruction memory
    output [31:0]       imem_addr_o /*verilator public*/,
    input [31:0]        imem_dat_i /*verilator public*/,
    output [2:0]        imem_cti_o /*verilator public*/,
    output              imem_cyc_o /*verilator public*/,
    output              imem_stb_o /*verilator public*/,
    input               imem_stall_i/*verilator public*/,
    input               imem_ack_i/*verilator public*/,
 
    // Data memory
    output [31:0]       dmem_addr_o /*verilator public*/,
    output [31:0]       dmem_dat_o /*verilator public*/,
    input [31:0]        dmem_dat_i /*verilator public*/,
    output [3:0]        dmem_sel_o /*verilator public*/,
    output [2:0]        dmem_cti_o /*verilator public*/,
    output              dmem_cyc_o /*verilator public*/,
    output              dmem_we_o /*verilator public*/,
    output              dmem_stb_o /*verilator public*/,
    input               dmem_stall_i/*verilator public*/,
    input               dmem_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter           BOOT_VECTOR         = 32'h00000000;
parameter           ISR_VECTOR          = 32'h00000000;
parameter           REGISTER_FILE_TYPE  = "SIMULATION";
parameter           ENABLE_ICACHE       = "ENABLED";
parameter           ENABLE_DCACHE       = "DISABLED";
parameter           SUPPORT_32REGS      = "ENABLED";
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
// Register number (rA)
wire [4:0]  w_ra;
 
// Register number (rB)
wire [4:0]  w_rb;
 
// Destination register number (pre execute stage)
wire [4:0]  w_rd;
 
// Destination register number (post execute stage)
wire [4:0]  w_e_rd;
 
// Register value (rA)
wire [31:0] w_reg_ra;
 
// Register value (rB)
wire [31:0] w_reg_rb;
 
// Current opcode
wire [31:0] w_d_opcode;
wire [31:0] w_d_pc;
wire        w_d_valid;
 
wire [31:0] w_e_opcode;
 
// Register writeback value
wire [4:0]  w_wb_rd;
wire [31:0] w_wb_reg_rd;
 
// Register writeback enable
wire        w_wb_write_rd;
 
// Result from execute
wire [31:0] w_e_result;
wire        w_e_mult;
wire [31:0] w_e_mult_result;
 
// Branch request
wire        w_e_branch;
wire [31:0] w_e_branch_pc;
wire        w_e_stall;
 
wire        icache_rd;
wire [31:0] icache_pc;
wire [31:0] icache_inst;
wire        icache_miss;
wire        icache_valid;
wire        icache_busy;
wire        icache_invalidate;
 
wire [31:0] dcache_addr;
wire [31:0] dcache_data_o;
wire [31:0] dcache_data_i;
wire [3:0]  dcache_sel;
wire        dcache_we;
wire        dcache_stb;
wire        dcache_cyc;
wire        dcache_ack;
wire        dcache_stall;
wire        dcache_flush;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
// Instruction Cache
generate
if (ENABLE_ICACHE == "ENABLED")
begin : ICACHE
    // Instruction cache
    altor32_icache
    #(
        .BOOT_VECTOR(BOOT_VECTOR)
    )
    u_icache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        // Processor interface
        .rd_i(icache_rd),
        .pc_i(icache_pc),
        .instruction_o(icache_inst),
        .valid_o(icache_valid),
        .invalidate_i(icache_invalidate),
 
        // Status
        .miss_o(icache_miss),
        .busy_o(icache_busy),
 
        // Instruction memory
        .wbm_addr_o(imem_addr_o),
        .wbm_dat_i(imem_dat_i),
        .wbm_cti_o(imem_cti_o),
        .wbm_cyc_o(imem_cyc_o),
        .wbm_stb_o(imem_stb_o),
        .wbm_stall_i(imem_stall_i),
        .wbm_ack_i(imem_ack_i)
    );
end
else
begin : NO_ICACHE
    // No instruction cache
    altor32_noicache
    u_icache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        // Processor interface
        .rd_i(icache_rd),
        .pc_i(icache_pc),
        .instruction_o(icache_inst),
        .valid_o(icache_valid),
 
        // Instruction memory
        .wbm_addr_o(imem_addr_o),
        .wbm_dat_i(imem_dat_i),
        .wbm_cti_o(imem_cti_o),
        .wbm_cyc_o(imem_cyc_o),
        .wbm_stb_o(imem_stb_o),
        .wbm_stall_i(imem_stall_i),
        .wbm_ack_i(imem_ack_i)
    );
end
endgenerate
 
// Instruction Fetch
altor32_fetch
#(
    .BOOT_VECTOR(BOOT_VECTOR)
)
u_fetch
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Instruction memory
    .pc_o(icache_pc),
    .data_i(icache_inst),
    .fetch_o(icache_rd),
    .data_valid_i(icache_valid),
 
    // Fetched opcode
    .opcode_o(w_d_opcode),
    .opcode_pc_o(w_d_pc),
    .opcode_valid_o(w_d_valid),
 
    // Branch target
    .branch_i(w_e_branch),
    .branch_pc_i(w_e_branch_pc),
    .stall_i(w_e_stall),
 
    // Decoded register details
    .ra_o(w_ra),
    .rb_o(w_rb),
    .rd_o(w_rd)
);
 
// Register file
generate
if (REGISTER_FILE_TYPE == "XILINX")
begin : REGFILE_XIL
    altor32_regfile_xil
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    reg_bank
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(w_wb_write_rd),
 
        // Tri-port
        .rs_i(w_ra),
        .rt_i(w_rb),
        .rd_i(w_wb_rd),
        .reg_rs_o(w_reg_ra),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
    );
end
else if (REGISTER_FILE_TYPE == "ALTERA")
begin : REGFILE_ALT
    altor32_regfile_alt
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    reg_bank
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(w_wb_write_rd),
 
        // Tri-port
        .rs_i(w_ra),
        .rt_i(w_rb),
        .rd_i(w_wb_rd),
        .reg_rs_o(w_reg_ra),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
    );
end
else
begin : REGFILE_SIM
    altor32_regfile_sim
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    reg_bank
    (
        // Clocking
        .clk_i(clk_i),
        .rst_i(rst_i),
        .wr_i(w_wb_write_rd),
 
        // Tri-port
        .rs_i(w_ra),
        .rt_i(w_rb),
        .rd_i(w_wb_rd),
        .reg_rs_o(w_reg_ra),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
    );
end
endgenerate
 
generate
if (ENABLE_DCACHE == "ENABLED")
begin : DCACHE
    // Data cache
    altor32_dcache
    u_dcache
    (
        .clk_i(clk_i),
        .rst_i(rst_i),
 
        .flush_i(dcache_flush),
 
        // Processor interface
        .address_i({dcache_addr[31:2], 2'b00}),
        .data_o(dcache_data_i),
        .data_i(dcache_data_o),
        .we_i(dcache_we),
        .stb_i(dcache_stb),
        .sel_i(dcache_sel),
        .stall_o(dcache_stall),
        .ack_o(dcache_ack),
 
        // Memory interface (slave)
        .mem_addr_o(dmem_addr_o),
        .mem_data_i(dmem_dat_i),
        .mem_data_o(dmem_dat_o),
        .mem_sel_o(dmem_sel_o),
        .mem_we_o(dmem_we_o),
        .mem_stb_o(dmem_stb_o),
        .mem_cyc_o(dmem_cyc_o),
        .mem_cti_o(dmem_cti_o),
        .mem_stall_i(dmem_stall_i),
        .mem_ack_i(dmem_ack_i)
    );
end
else
begin: NO_DCACHE
 
    // No data cache
    assign dmem_addr_o      = {dcache_addr[31:2], 2'b00};
    assign dmem_dat_o       = dcache_data_o;
    assign dcache_data_i    = dmem_dat_i;
    assign dmem_sel_o       = dcache_sel;
    assign dmem_cyc_o       = dcache_cyc;
    assign dmem_we_o        = dcache_we;
    assign dmem_stb_o       = dcache_stb;
    assign dmem_cti_o       = 3'b111;
    assign dcache_ack       = dmem_ack_i;
    assign dcache_stall     = dmem_stall_i;
end
endgenerate
 
// Execution unit
altor32_exec
#(
    .BOOT_VECTOR(BOOT_VECTOR),
    .ISR_VECTOR(ISR_VECTOR)
)
u_exec
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    .intr_i(intr_i),
    .nmi_i(nmi_i),
 
    // Status
    .fault_o(fault_o),
    .break_o(break_o),
 
    // Cache control
    .icache_flush_o(icache_invalidate),
    .dcache_flush_o(dcache_flush),
 
    // Branch target
    .branch_o(w_e_branch),
    .branch_pc_o(w_e_branch_pc),
    .stall_o(w_e_stall),
 
    // Opcode & arguments
    .opcode_i(w_d_opcode),
    .opcode_pc_i(w_d_pc),
    .opcode_valid_i(w_d_valid),
 
    .reg_ra_i(w_ra),
    .reg_ra_value_i(w_reg_ra),
 
    .reg_rb_i(w_rb),
    .reg_rb_value_i(w_reg_rb),
 
    .reg_rd_i(w_rd),
 
    // Output
    .opcode_o(w_e_opcode),
    .reg_rd_o(w_e_rd),
    .reg_rd_value_o(w_e_result),
    .mult_o(w_e_mult),
    .mult_res_o(w_e_mult_result),
 
    // Register write back bypass
    .wb_rd_i(w_wb_rd),
    .wb_rd_value_i(w_wb_reg_rd),
 
    // Memory Interface
    .dmem_addr_o(dcache_addr),
    .dmem_data_out_o(dcache_data_o),
    .dmem_data_in_i(dcache_data_i),
    .dmem_sel_o(dcache_sel),
    .dmem_we_o(dcache_we),
    .dmem_stb_o(dcache_stb),
    .dmem_cyc_o(dcache_cyc),
    .dmem_stall_i(dcache_stall),
    .dmem_ack_i(dcache_ack)
);
 
// Register file writeback
altor32_writeback
u_wb
(
    // General
    .clk_i(clk_i),
    .rst_i(rst_i),
 
    // Opcode
    .opcode_i(w_e_opcode),
 
    // Register target
    .rd_i(w_e_rd),
 
    // ALU result
    .alu_result_i(w_e_result),
 
    // Memory load result
    .mem_result_i(dcache_data_i),
    .mem_offset_i(dcache_addr[1:0]),
    .mem_ready_i(dcache_ack),
 
    // Multiplier result
    .mult_i(w_e_mult),
    .mult_result_i(w_e_mult_result),
 
    // Outputs
    .write_enable_o(w_wb_write_rd),
    .write_addr_o(w_wb_rd),
    .write_data_o(w_wb_reg_rd)
);
 
//-------------------------------------------------------------------
// Hooks for debug
//-------------------------------------------------------------------
`ifdef verilator
   function [31:0] get_pc;
      // verilator public
      get_pc = w_d_pc;
   endfunction
   function get_fault;
      // verilator public
      get_fault = fault_o;
   endfunction
   function get_break;
      // verilator public
      get_break = break_o;
   endfunction
`endif
 
endmodule

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// AltOR32`
3			`// Alternative Lightweight OpenRisc`
4			`// V2.0`
5			`// Ultra-Embedded.com`
6			`// Copyright 2011 - 2013`
7			`//`
8			`// Email: admin@ultra-embedded.com`
9			`//`
10			`// License: LGPL`
11			`//-----------------------------------------------------------------`
12			`//`
13			`// Copyright (C) 2011 - 2013 Ultra-Embedded.com`
14			`//`
15			`// This source file may be used and distributed without`
16			`// restriction provided that this copyright statement is not`
17			`// removed from the file and that any derivative work contains`
18			`// the original copyright notice and the associated disclaimer.`
19			`//`
20			`// This source file is free software; you can redistribute it`
21			`// and/or modify it under the terms of the GNU Lesser General`
22			`// Public License as published by the Free Software Foundation;`
23			`// either version 2.1 of the License, or (at your option) any`
24			`// later version.`
25			`//`
26			`// This source is distributed in the hope that it will be`
27			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
28			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
29			`// PURPOSE. See the GNU Lesser General Public License for more`
30			`// details.`
31			`//`
32			`// You should have received a copy of the GNU Lesser General`
33			`// Public License along with this source; if not, write to the`
34			`// Free Software Foundation, Inc., 59 Temple Place, Suite 330,`
35			`// Boston, MA 02111-1307 USA`
36			`//-----------------------------------------------------------------`
37
38			`//-----------------------------------------------------------------`
39			`// Includes`
40			`//-----------------------------------------------------------------`
41			`include "altor32_defs.v"
42
43			`//-----------------------------------------------------------------`
44	32	ultra_embe	`// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)`
45	27	ultra_embe	`//-----------------------------------------------------------------`
46			`module cpu`
47			`(`
48			`// General`
49			`input clk_i /verilator public/,`
50			`input rst_i /verilator public/,`
51
52			`input intr_i /verilator public/,`
53			`input nmi_i /verilator public/,`
54			`output fault_o /verilator public/,`
55			`output break_o /verilator public/,`
56
57			`// Instruction memory`
58			`output [31:0] imem_addr_o /verilator public/,`
59	32	ultra_embe	`input [31:0] imem_dat_i /verilator public/,`
60			`output [2:0] imem_cti_o /verilator public/,`
61			`output imem_cyc_o /verilator public/,`
62			`output imem_stb_o /verilator public/,`
63			`input imem_stall_i/verilator public/,`
64			`input imem_ack_i/verilator public/,`
65	27	ultra_embe
66			`// Data memory`
67			`output [31:0] dmem_addr_o /verilator public/,`
68	32	ultra_embe	`output [31:0] dmem_dat_o /verilator public/,`
69			`input [31:0] dmem_dat_i /verilator public/,`
70			`output [3:0] dmem_sel_o /verilator public/,`
71			`output [2:0] dmem_cti_o /verilator public/,`
72			`output dmem_cyc_o /verilator public/,`
73			`output dmem_we_o /verilator public/,`
74			`output dmem_stb_o /verilator public/,`
75			`input dmem_stall_i/verilator public/,`
76			`input dmem_ack_i/verilator public/`
77	27	ultra_embe	`);`
78
79			`//-----------------------------------------------------------------`
80			`// Params`
81			`//-----------------------------------------------------------------`
82			`parameter BOOT_VECTOR = 32'h00000000;`
83			`parameter ISR_VECTOR = 32'h00000000;`
84			`parameter REGISTER_FILE_TYPE = "SIMULATION";`
85			`parameter ENABLE_ICACHE = "ENABLED";`
86			`parameter ENABLE_DCACHE = "DISABLED";`
87			`parameter SUPPORT_32REGS = "ENABLED";`
88
89			`//-----------------------------------------------------------------`
90			`// Registers / Wires`
91			`//-----------------------------------------------------------------`
92
93			`// Register number (rA)`
94			`wire [4:0] w_ra;`
95
96			`// Register number (rB)`
97			`wire [4:0] w_rb;`
98
99			`// Destination register number (pre execute stage)`
100			`wire [4:0] w_rd;`
101
102			`// Destination register number (post execute stage)`
103			`wire [4:0] w_e_rd;`
104
105			`// Register value (rA)`
106			`wire [31:0] w_reg_ra;`
107
108			`// Register value (rB)`
109			`wire [31:0] w_reg_rb;`
110
111			`// Current opcode`
112			`wire [31:0] w_d_opcode;`
113			`wire [31:0] w_d_pc;`
114			`wire w_d_valid;`
115
116			`wire [31:0] w_e_opcode;`
117
118			`// Register writeback value`
119			`wire [4:0] w_wb_rd;`
120			`wire [31:0] w_wb_reg_rd;`
121
122			`// Register writeback enable`
123			`wire w_wb_write_rd;`
124
125			`// Result from execute`
126			`wire [31:0] w_e_result;`
127			`wire w_e_mult;`
128			`wire [31:0] w_e_mult_result;`
129
130			`// Branch request`
131			`wire w_e_branch;`
132			`wire [31:0] w_e_branch_pc;`
133			`wire w_e_stall;`
134
135			`wire icache_rd;`
136			`wire [31:0] icache_pc;`
137			`wire [31:0] icache_inst;`
138			`wire icache_miss;`
139			`wire icache_valid;`
140			`wire icache_busy;`
141			`wire icache_invalidate;`
142
143			`wire [31:0] dcache_addr;`
144			`wire [31:0] dcache_data_o;`
145			`wire [31:0] dcache_data_i;`
146	32	ultra_embe	`wire [3:0] dcache_sel;`
147			`wire dcache_we;`
148			`wire dcache_stb;`
149			`wire dcache_cyc;`
150	27	ultra_embe	`wire dcache_ack;`
151	32	ultra_embe	`wire dcache_stall;`
152	27	ultra_embe	`wire dcache_flush;`
153
154			`//-----------------------------------------------------------------`
155			`// Instantiation`
156			`//-----------------------------------------------------------------`
157
158			`// Instruction Cache`
159			`generate`
160			`if (ENABLE_ICACHE == "ENABLED")`
161			`begin : ICACHE`
162			`// Instruction cache`
163			`altor32_icache`
164			`#(`
165			`.BOOT_VECTOR(BOOT_VECTOR)`
166			`)`
167			`u_icache`
168			`(`
169			`.clk_i(clk_i),`
170			`.rst_i(rst_i),`
171
172			`// Processor interface`
173			`.rd_i(icache_rd),`
174			`.pc_i(icache_pc),`
175			`.instruction_o(icache_inst),`
176			`.valid_o(icache_valid),`
177			`.invalidate_i(icache_invalidate),`
178
179			`// Status`
180			`.miss_o(icache_miss),`
181			`.busy_o(icache_busy),`
182
183			`// Instruction memory`
184	32	ultra_embe	`.wbm_addr_o(imem_addr_o),`
185			`.wbm_dat_i(imem_dat_i),`
186			`.wbm_cti_o(imem_cti_o),`
187			`.wbm_cyc_o(imem_cyc_o),`
188			`.wbm_stb_o(imem_stb_o),`
189			`.wbm_stall_i(imem_stall_i),`
190			`.wbm_ack_i(imem_ack_i)`
191	27	ultra_embe	`);`
192			`end`
193			`else`
194	32	ultra_embe	`begin : NO_ICACHE`
195	27	ultra_embe	`// No instruction cache`
196			`altor32_noicache`
197			`u_icache`
198			`(`
199			`.clk_i(clk_i),`
200			`.rst_i(rst_i),`
201
202			`// Processor interface`
203			`.rd_i(icache_rd),`
204			`.pc_i(icache_pc),`
205			`.instruction_o(icache_inst),`
206			`.valid_o(icache_valid),`
207
208			`// Instruction memory`
209	32	ultra_embe	`.wbm_addr_o(imem_addr_o),`
210			`.wbm_dat_i(imem_dat_i),`
211			`.wbm_cti_o(imem_cti_o),`
212			`.wbm_cyc_o(imem_cyc_o),`
213			`.wbm_stb_o(imem_stb_o),`
214			`.wbm_stall_i(imem_stall_i),`
215			`.wbm_ack_i(imem_ack_i)`
216	27	ultra_embe	`);`
217			`end`
218			`endgenerate`
219
220			`// Instruction Fetch`
221			`altor32_fetch`
222			`#(`
223			`.BOOT_VECTOR(BOOT_VECTOR)`
224			`)`
225			`u_fetch`
226			`(`
227			`// General`
228			`.clk_i(clk_i),`
229			`.rst_i(rst_i),`
230
231			`// Instruction memory`
232			`.pc_o(icache_pc),`
233			`.data_i(icache_inst),`
234			`.fetch_o(icache_rd),`
235			`.data_valid_i(icache_valid),`
236
237			`// Fetched opcode`
238			`.opcode_o(w_d_opcode),`
239			`.opcode_pc_o(w_d_pc),`
240			`.opcode_valid_o(w_d_valid),`
241
242			`// Branch target`
243			`.branch_i(w_e_branch),`
244			`.branch_pc_i(w_e_branch_pc),`
245			`.stall_i(w_e_stall),`
246
247			`// Decoded register details`
248			`.ra_o(w_ra),`
249			`.rb_o(w_rb),`
250			`.rd_o(w_rd)`
251			`);`
252
253			`// Register file`
254			`generate`
255			`if (REGISTER_FILE_TYPE == "XILINX")`
256	32	ultra_embe	`begin : REGFILE_XIL`
257	27	ultra_embe	`altor32_regfile_xil`
258			`#(`
259			`.SUPPORT_32REGS(SUPPORT_32REGS)`
260			`)`
261			`reg_bank`
262			`(`
263			`// Clocking`
264			`.clk_i(clk_i),`
265			`.rst_i(rst_i),`
266			`.wr_i(w_wb_write_rd),`
267
268			`// Tri-port`
269			`.rs_i(w_ra),`
270			`.rt_i(w_rb),`
271			`.rd_i(w_wb_rd),`
272			`.reg_rs_o(w_reg_ra),`
273			`.reg_rt_o(w_reg_rb),`
274			`.reg_rd_i(w_wb_reg_rd)`
275			`);`
276			`end`
277			`else if (REGISTER_FILE_TYPE == "ALTERA")`
278	32	ultra_embe	`begin : REGFILE_ALT`
279	27	ultra_embe	`altor32_regfile_alt`
280			`#(`
281			`.SUPPORT_32REGS(SUPPORT_32REGS)`
282			`)`
283			`reg_bank`
284			`(`
285			`// Clocking`
286			`.clk_i(clk_i),`
287			`.rst_i(rst_i),`
288			`.wr_i(w_wb_write_rd),`
289
290			`// Tri-port`
291			`.rs_i(w_ra),`
292			`.rt_i(w_rb),`
293			`.rd_i(w_wb_rd),`
294			`.reg_rs_o(w_reg_ra),`
295			`.reg_rt_o(w_reg_rb),`
296			`.reg_rd_i(w_wb_reg_rd)`
297			`);`
298			`end`
299			`else`
300	32	ultra_embe	`begin : REGFILE_SIM`
301	27	ultra_embe	`altor32_regfile_sim`
302			`#(`
303			`.SUPPORT_32REGS(SUPPORT_32REGS)`
304			`)`
305			`reg_bank`
306			`(`
307			`// Clocking`
308			`.clk_i(clk_i),`
309			`.rst_i(rst_i),`
310			`.wr_i(w_wb_write_rd),`
311
312			`// Tri-port`
313			`.rs_i(w_ra),`
314			`.rt_i(w_rb),`
315			`.rd_i(w_wb_rd),`
316			`.reg_rs_o(w_reg_ra),`
317			`.reg_rt_o(w_reg_rb),`
318			`.reg_rd_i(w_wb_reg_rd)`
319			`);`
320			`end`
321			`endgenerate`
322
323			`generate`
324			`if (ENABLE_DCACHE == "ENABLED")`
325	32	ultra_embe	`begin : DCACHE`
326	27	ultra_embe	`// Data cache`
327			`altor32_dcache`
328			`u_dcache`
329			`(`
330			`.clk_i(clk_i),`
331			`.rst_i(rst_i),`
332
333			`.flush_i(dcache_flush),`
334
335			`// Processor interface`
336			`.address_i({dcache_addr[31:2], 2'b00}),`
337			`.data_o(dcache_data_i),`
338			`.data_i(dcache_data_o),`
339	32	ultra_embe	`.we_i(dcache_we),`
340			`.stb_i(dcache_stb),`
341			`.sel_i(dcache_sel),`
342			`.stall_o(dcache_stall),`
343	27	ultra_embe	`.ack_o(dcache_ack),`
344
345			`// Memory interface (slave)`
346			`.mem_addr_o(dmem_addr_o),`
347	32	ultra_embe	`.mem_data_i(dmem_dat_i),`
348			`.mem_data_o(dmem_dat_o),`
349			`.mem_sel_o(dmem_sel_o),`
350			`.mem_we_o(dmem_we_o),`
351			`.mem_stb_o(dmem_stb_o),`
352			`.mem_cyc_o(dmem_cyc_o),`
353			`.mem_cti_o(dmem_cti_o),`
354			`.mem_stall_i(dmem_stall_i),`
355	27	ultra_embe	`.mem_ack_i(dmem_ack_i)`
356			`);`
357			`end`
358			`else`
359	32	ultra_embe	`begin: NO_DCACHE`
360	27	ultra_embe
361			`// No data cache`
362			`assign dmem_addr_o = {dcache_addr[31:2], 2'b00};`
363	32	ultra_embe	`assign dmem_dat_o = dcache_data_o;`
364			`assign dcache_data_i = dmem_dat_i;`
365			`assign dmem_sel_o = dcache_sel;`
366			`assign dmem_cyc_o = dcache_cyc;`
367			`assign dmem_we_o = dcache_we;`
368			`assign dmem_stb_o = dcache_stb;`
369			`assign dmem_cti_o = 3'b111;`
370	27	ultra_embe	`assign dcache_ack = dmem_ack_i;`
371	32	ultra_embe	`assign dcache_stall = dmem_stall_i;`
372	27	ultra_embe	`end`
373			`endgenerate`
374
375			`// Execution unit`
376			`altor32_exec`
377			`#(`
378			`.BOOT_VECTOR(BOOT_VECTOR),`
379			`.ISR_VECTOR(ISR_VECTOR)`
380			`)`
381			`u_exec`
382			`(`
383			`// General`
384			`.clk_i(clk_i),`
385			`.rst_i(rst_i),`
386
387			`.intr_i(intr_i),`
388			`.nmi_i(nmi_i),`
389
390			`// Status`
391			`.fault_o(fault_o),`
392			`.break_o(break_o),`
393
394			`// Cache control`
395			`.icache_flush_o(icache_invalidate),`
396			`.dcache_flush_o(dcache_flush),`
397
398			`// Branch target`
399			`.branch_o(w_e_branch),`
400			`.branch_pc_o(w_e_branch_pc),`
401			`.stall_o(w_e_stall),`
402
403			`// Opcode & arguments`
404			`.opcode_i(w_d_opcode),`
405			`.opcode_pc_i(w_d_pc),`
406			`.opcode_valid_i(w_d_valid),`
407
408			`.reg_ra_i(w_ra),`
409			`.reg_ra_value_i(w_reg_ra),`
410
411			`.reg_rb_i(w_rb),`
412			`.reg_rb_value_i(w_reg_rb),`
413
414			`.reg_rd_i(w_rd),`
415
416			`// Output`
417			`.opcode_o(w_e_opcode),`
418			`.reg_rd_o(w_e_rd),`
419			`.reg_rd_value_o(w_e_result),`
420			`.mult_o(w_e_mult),`
421			`.mult_res_o(w_e_mult_result),`
422
423			`// Register write back bypass`
424			`.wb_rd_i(w_wb_rd),`
425			`.wb_rd_value_i(w_wb_reg_rd),`
426
427			`// Memory Interface`
428			`.dmem_addr_o(dcache_addr),`
429			`.dmem_data_out_o(dcache_data_o),`
430			`.dmem_data_in_i(dcache_data_i),`
431	32	ultra_embe	`.dmem_sel_o(dcache_sel),`
432			`.dmem_we_o(dcache_we),`
433			`.dmem_stb_o(dcache_stb),`
434			`.dmem_cyc_o(dcache_cyc),`
435			`.dmem_stall_i(dcache_stall),`
436	27	ultra_embe	`.dmem_ack_i(dcache_ack)`
437			`);`
438
439			`// Register file writeback`
440			`altor32_writeback`
441			`u_wb`
442			`(`
443			`// General`
444			`.clk_i(clk_i),`
445			`.rst_i(rst_i),`
446
447			`// Opcode`
448			`.opcode_i(w_e_opcode),`
449
450			`// Register target`
451			`.rd_i(w_e_rd),`
452
453			`// ALU result`
454			`.alu_result_i(w_e_result),`
455
456			`// Memory load result`
457			`.mem_result_i(dcache_data_i),`
458			`.mem_offset_i(dcache_addr[1:0]),`
459			`.mem_ready_i(dcache_ack),`
460
461			`// Multiplier result`
462			`.mult_i(w_e_mult),`
463			`.mult_result_i(w_e_mult_result),`
464
465			`// Outputs`
466			`.write_enable_o(w_wb_write_rd),`
467			`.write_addr_o(w_wb_rd),`
468			`.write_data_o(w_wb_reg_rd)`
469			`);`
470
471			`//-------------------------------------------------------------------`
472			`// Hooks for debug`
473			`//-------------------------------------------------------------------`
474			`ifdef verilator
475			`function [31:0] get_pc;`
476			`// verilator public`
477			`get_pc = w_d_pc;`
478			`endfunction`
479			`function get_fault;`
480			`// verilator public`
481			`get_fault = fault_o;`
482			`endfunction`
483			`function get_break;`
484			`// verilator public`
485			`get_break = break_o;`
486			`endfunction`
487			`endif
488
489			`endmodule`

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