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[/] [altor32/] [trunk/] [rtl/] [sim/] [ram.v] - Blame information for rev 27

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//-----------------------------------------------------------------
// Module: ram - dual port block RAM
//-----------------------------------------------------------------
module ram
(
    // Port A
    input clka_i /*verilator public*/,
    input ena_i /*verilator public*/,
    input [3:0] wea_i /*verilator public*/,
    input [31:2] addra_i /*verilator public*/,
    input [31:0] dataa_i /*verilator public*/,
    output [31:0] dataa_o /*verilator public*/,
 
    // Port B
    input clkb_i /*verilator public*/,
    input enb_i /*verilator public*/,
    input [3:0] web_i /*verilator public*/,
    input [31:2] addrb_i /*verilator public*/,
    input [31:0] datab_i /*verilator public*/,
    output [31:0] datab_o /*verilator public*/
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter  [31:0]       block_count  = 6;
parameter  [31:0]       SIZE         = 14;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
ram_dp8
#(
    .WIDTH(8),
    .SIZE(SIZE)
)
u0
(
    .aclk_i(clka_i),
    .aadr_i(addra_i[SIZE+2-1:2]),
    .adat_o(dataa_o[7:0]),
    .adat_i(dataa_i[7:0]),
    .awr_i(wea_i[0]),
 
    .bclk_i(clkb_i),
    .badr_i(addrb_i[SIZE+2-1:2]),
    .bdat_o(datab_o[7:0]),
    .bdat_i(datab_i[7:0]),
    .bwr_i(web_i[0])
);
 
ram_dp8
#(
    .WIDTH(8),
    .SIZE(SIZE)
)
u1
(
    .aclk_i(clka_i),
    .aadr_i(addra_i[SIZE+2-1:2]),
    .adat_o(dataa_o[15:8]),
    .adat_i(dataa_i[15:8]),
    .awr_i(wea_i[1]),
 
    .bclk_i(clkb_i),
    .badr_i(addrb_i[SIZE+2-1:2]),
    .bdat_o(datab_o[15:8]),
    .bdat_i(datab_i[15:8]),
    .bwr_i(web_i[1])
);
 
ram_dp8
#(
    .WIDTH(8),
    .SIZE(SIZE)
)
u2
(
    .aclk_i(clka_i),
    .aadr_i(addra_i[SIZE+2-1:2]),
    .adat_o(dataa_o[23:16]),
    .adat_i(dataa_i[23:16]),
    .awr_i(wea_i[2]),
 
    .bclk_i(clkb_i),
    .badr_i(addrb_i[SIZE+2-1:2]),
    .bdat_o(datab_o[23:16]),
    .bdat_i(datab_i[23:16]),
    .bwr_i(web_i[2])
);
 
ram_dp8
#(
    .WIDTH(8),
    .SIZE(SIZE)
)
u3
(
    .aclk_i(clka_i),
    .aadr_i(addra_i[SIZE+2-1:2]),
    .adat_o(dataa_o[31:24]),
    .adat_i(dataa_i[31:24]),
    .awr_i(wea_i[3]),
 
    .bclk_i(clkb_i),
    .badr_i(addrb_i[SIZE+2-1:2]),
    .bdat_o(datab_o[31:24]),
    .bdat_i(datab_i[31:24]),
    .bwr_i(web_i[3])
);
 
endmodule

Line No.	Rev	Author	Line
1	27	ultra_embe	`//-----------------------------------------------------------------`
2			`// Module: ram - dual port block RAM`
3			`//-----------------------------------------------------------------`
4			`module ram`
5			`(`
6			`// Port A`
7			`input clka_i /verilator public/,`
8			`input ena_i /verilator public/,`
9			`input [3:0] wea_i /verilator public/,`
10			`input [31:2] addra_i /verilator public/,`
11			`input [31:0] dataa_i /verilator public/,`
12			`output [31:0] dataa_o /verilator public/,`
13
14			`// Port B`
15			`input clkb_i /verilator public/,`
16			`input enb_i /verilator public/,`
17			`input [3:0] web_i /verilator public/,`
18			`input [31:2] addrb_i /verilator public/,`
19			`input [31:0] datab_i /verilator public/,`
20			`output [31:0] datab_o /verilator public/`
21			`);`
22
23			`//-----------------------------------------------------------------`
24			`// Params`
25			`//-----------------------------------------------------------------`
26			`parameter [31:0] block_count = 6;`
27			`parameter [31:0] SIZE = 14;`
28
29			`//-----------------------------------------------------------------`
30			`// Instantiation`
31			`//-----------------------------------------------------------------`
32
33			`ram_dp8`
34			`#(`
35			`.WIDTH(8),`
36			`.SIZE(SIZE)`
37			`)`
38			`u0`
39			`(`
40			`.aclk_i(clka_i),`
41			`.aadr_i(addra_i[SIZE+2-1:2]),`
42			`.adat_o(dataa_o[7:0]),`
43			`.adat_i(dataa_i[7:0]),`
44			`.awr_i(wea_i[0]),`
45
46			`.bclk_i(clkb_i),`
47			`.badr_i(addrb_i[SIZE+2-1:2]),`
48			`.bdat_o(datab_o[7:0]),`
49			`.bdat_i(datab_i[7:0]),`
50			`.bwr_i(web_i[0])`
51			`);`
52
53			`ram_dp8`
54			`#(`
55			`.WIDTH(8),`
56			`.SIZE(SIZE)`
57			`)`
58			`u1`
59			`(`
60			`.aclk_i(clka_i),`
61			`.aadr_i(addra_i[SIZE+2-1:2]),`
62			`.adat_o(dataa_o[15:8]),`
63			`.adat_i(dataa_i[15:8]),`
64			`.awr_i(wea_i[1]),`
65
66			`.bclk_i(clkb_i),`
67			`.badr_i(addrb_i[SIZE+2-1:2]),`
68			`.bdat_o(datab_o[15:8]),`
69			`.bdat_i(datab_i[15:8]),`
70			`.bwr_i(web_i[1])`
71			`);`
72
73			`ram_dp8`
74			`#(`
75			`.WIDTH(8),`
76			`.SIZE(SIZE)`
77			`)`
78			`u2`
79			`(`
80			`.aclk_i(clka_i),`
81			`.aadr_i(addra_i[SIZE+2-1:2]),`
82			`.adat_o(dataa_o[23:16]),`
83			`.adat_i(dataa_i[23:16]),`
84			`.awr_i(wea_i[2]),`
85
86			`.bclk_i(clkb_i),`
87			`.badr_i(addrb_i[SIZE+2-1:2]),`
88			`.bdat_o(datab_o[23:16]),`
89			`.bdat_i(datab_i[23:16]),`
90			`.bwr_i(web_i[2])`
91			`);`
92
93			`ram_dp8`
94			`#(`
95			`.WIDTH(8),`
96			`.SIZE(SIZE)`
97			`)`
98			`u3`
99			`(`
100			`.aclk_i(clka_i),`
101			`.aadr_i(addra_i[SIZE+2-1:2]),`
102			`.adat_o(dataa_o[31:24]),`
103			`.adat_i(dataa_i[31:24]),`
104			`.awr_i(wea_i[3]),`
105
106			`.bclk_i(clkb_i),`
107			`.badr_i(addrb_i[SIZE+2-1:2]),`
108			`.bdat_o(datab_o[31:24]),`
109			`.bdat_i(datab_i[31:24]),`
110			`.bwr_i(web_i[3])`
111			`);`
112
113			`endmodule`

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[/] [altor32/] [trunk/] [rtl/] [sim/] [ram.v] - Blame information for rev 27