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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_mem.v] - Blame information for rev 60

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1 16 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Memory Access - Instantiates the memory access stage        //
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//  sub-modules of the Amber 25 Core                            //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Instantiates the Data Cache                                 //
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//  Also contains a little bit of logic to decode memory        //
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//  accesses to decide if they are cached or not                //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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module a25_mem
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(
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input                       i_clk,
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input                       i_fetch_stall,          // Fetch stage asserting stall
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input                       i_exec_stall,           // Execute stage asserting stall
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output                      o_mem_stall,            // Mem stage asserting stall
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input       [31:0]          i_daddress,
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input                       i_daddress_valid,
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input       [31:0]          i_daddress_nxt,         // un-registered version of address to the cache rams
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input       [31:0]          i_write_data,
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input                       i_write_enable,
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input                       i_exclusive,            // high for read part of swap access
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input       [3:0]           i_byte_enable,
59 35 csantifort
input       [8:0]           i_exec_load_rd,         // The destination register for a load instruction
60 16 csantifort
input                       i_cache_enable,         // cache enable
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input                       i_cache_flush,          // cache flush
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input       [31:0]          i_cacheable_area,       // each bit corresponds to 2MB address space
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output      [31:0]          o_mem_read_data,
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output                      o_mem_read_data_valid,
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output      [10:0]          o_mem_load_rd,          // The destination register for a load instruction
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// Wishbone accesses                                                         
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output                      o_wb_cached_req,        // Cached Request
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output                      o_wb_uncached_req,      // Unached Request
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output                      o_wb_write,             // Read=0, Write=1
72 35 csantifort
output     [15:0]           o_wb_byte_enable,       // byte eable
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output     [127:0]          o_wb_write_data,
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output     [31:0]           o_wb_address,           // wb bus                                 
75 35 csantifort
input      [127:0]          i_wb_uncached_rdata,    // wb bus                              
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input      [127:0]          i_wb_cached_rdata,      // wb bus                              
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input                       i_wb_cached_ready,      // wishbone access complete and read data valid
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input                       i_wb_uncached_ready     // wishbone access complete and read data valid
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);
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`include "memory_configuration.v"
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wire    [31:0]              cache_read_data;
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wire                        address_cachable;
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wire                        sel_cache_p;
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wire                        sel_cache;
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wire                        cached_wb_req;
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wire                        uncached_data_access;
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wire                        uncached_data_access_p;
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wire                        cache_stall;
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wire                        uncached_wb_wait;
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reg                         uncached_wb_req_r = 'd0;
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reg                         uncached_wb_stop_r = 'd0;
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reg                         cached_wb_stop_r = 'd0;
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wire                        daddress_valid_p;  // pulse
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reg      [31:0]             mem_read_data_r = 'd0;
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reg                         mem_read_data_valid_r = 'd0;
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reg      [10:0]             mem_load_rd_r = 'd0;
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wire     [10:0]             mem_load_rd_c;
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wire     [31:0]             mem_read_data_c;
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wire                        mem_read_data_valid_c;
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reg                         mem_stall_r = 'd0;
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wire                        use_mem_reg;
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reg                         fetch_only_stall_r = 'd0;
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wire                        fetch_only_stall;
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wire                        void_output;
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wire                        wb_stop;
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reg                         daddress_valid_stop_r = 'd0;
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wire     [31:0]             wb_rdata32;
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// ======================================
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// Memory Decode
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// ======================================
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assign address_cachable         = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
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assign sel_cache_p              = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive;
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assign sel_cache                = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive;
117 60 csantifort
assign uncached_data_access     = i_daddress_valid && !sel_cache && !cache_stall;
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assign uncached_data_access_p   = daddress_valid_p && !sel_cache;
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assign use_mem_reg              = wb_stop && !mem_stall_r;
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assign o_mem_read_data          = use_mem_reg ? mem_read_data_r       : mem_read_data_c;
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assign o_mem_load_rd            = use_mem_reg ? mem_load_rd_r         : mem_load_rd_c;
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assign o_mem_read_data_valid    = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
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// Return read data either from the wishbone bus or the cache
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assign wb_rdata32               = i_daddress[3:2] == 2'd0 ? i_wb_uncached_rdata[ 31: 0] :
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                                  i_daddress[3:2] == 2'd1 ? i_wb_uncached_rdata[ 63:32] :
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                                  i_daddress[3:2] == 2'd2 ? i_wb_uncached_rdata[ 95:64] :
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                                                            i_wb_uncached_rdata[127:96] ;
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132 16 csantifort
assign mem_read_data_c          = sel_cache             ? cache_read_data :
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                                  uncached_data_access  ? wb_rdata32      :
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                                                          32'h76543210    ;
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136 16 csantifort
assign mem_load_rd_c            = {i_daddress[1:0], i_exec_load_rd};
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assign mem_read_data_valid_c    = i_daddress_valid && !i_write_enable && !o_mem_stall;
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assign o_mem_stall              = uncached_wb_wait || cache_stall;
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// Request wishbone access
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assign o_wb_byte_enable         = i_daddress[3:2] == 2'd0 ? {12'd0, i_byte_enable       } :
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                                  i_daddress[3:2] == 2'd1 ? { 8'd0, i_byte_enable,  4'd0} :
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                                  i_daddress[3:2] == 2'd2 ? { 4'd0, i_byte_enable,  8'd0} :
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                                                            {       i_byte_enable, 12'd0} ;
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147 16 csantifort
assign o_wb_write               = i_write_enable;
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assign o_wb_address             = {i_daddress[31:2], 2'd0};
149 35 csantifort
assign o_wb_write_data          = {4{i_write_data}};
150 16 csantifort
assign o_wb_cached_req          = !cached_wb_stop_r && cached_wb_req;
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assign o_wb_uncached_req        = !uncached_wb_stop_r && uncached_data_access_p;
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assign uncached_wb_wait         = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
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always @( posedge i_clk )
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    begin
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    uncached_wb_req_r <=  (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
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    end
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assign fetch_only_stall     = i_fetch_stall && !o_mem_stall;
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always @( posedge i_clk )
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    fetch_only_stall_r <= fetch_only_stall;
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assign void_output = (fetch_only_stall_r && fetch_only_stall) || (fetch_only_stall_r && mem_read_data_valid_r);
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// pulse this signal
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assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r;
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always @( posedge i_clk )
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    begin
173 60 csantifort
    uncached_wb_stop_r      <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall);
174 16 csantifort
    cached_wb_stop_r        <= (cached_wb_stop_r   || cached_wb_req)          && (i_fetch_stall || o_mem_stall);
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    daddress_valid_stop_r   <= (daddress_valid_stop_r || daddress_valid_p)    && (i_fetch_stall || o_mem_stall);
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    // hold this until the mem access completes
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    mem_stall_r <= o_mem_stall;
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    end
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assign wb_stop = uncached_wb_stop_r || cached_wb_stop_r;
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always @( posedge i_clk )
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    if ( !wb_stop || o_mem_stall )
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        begin
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        mem_read_data_r         <= mem_read_data_c;
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        mem_load_rd_r           <= mem_load_rd_c;
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        mem_read_data_valid_r   <= mem_read_data_valid_c;
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        end
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// ======================================
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// L1 Data Cache
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// ======================================
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a25_dcache u_dcache (
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    .i_clk                      ( i_clk                 ),
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    .i_fetch_stall              ( i_fetch_stall         ),
198 35 csantifort
    .i_exec_stall               ( i_exec_stall          ),
199 16 csantifort
    .o_stall                    ( cache_stall           ),
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    .i_request                  ( sel_cache_p           ),
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    .i_exclusive                ( i_exclusive           ),
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    .i_write_data               ( i_write_data          ),
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    .i_write_enable             ( i_write_enable        ),
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    .i_address                  ( i_daddress            ),
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    .i_address_nxt              ( i_daddress_nxt        ),
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    .i_byte_enable              ( i_byte_enable         ),
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    .i_cache_enable             ( i_cache_enable        ),
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    .i_cache_flush              ( i_cache_flush         ),
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    .o_read_data                ( cache_read_data       ),
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    .o_wb_cached_req            ( cached_wb_req         ),
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    .i_wb_cached_rdata          ( i_wb_cached_rdata     ),
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    .i_wb_cached_ready          ( i_wb_cached_ready     )
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);
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endmodule
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