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[/] [amber/] [trunk/] [hw/] [vlog/] [xs6_ddr3/] [ddr3/] [user_design/] [mig.prj] - Blame information for rev 64

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    ddr3
    xc6slx45t-fgg484/-3
    3.92
    
        DDR3_SDRAM/Components/MT41J64M16XX-187E
        2500
        0
        1
        FALSE
        
        13
        10
        3
        
            
        
        8(00)
        6
        Enable
        RZQ/6
        RZQ/4
        0
        Disabled
        Disabled
        Full Array
        5
        Enabled
        Normal
        NATIVE
        Class II
        Class II
        UNCALIB_TERM
        50 Ohms
        
        
        
        Single-Ended
        1
        Disable
        Single-Ended
        One 128-bit bi-directional port
        R7
        W4
        Port0
        Bi-directional
        ROW_BANK_COLUMN
        Round Robin
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
    


Line No.	Rev	Author	Line
1	64	csantifort
2
3			`ddr3`
4			`xc6slx45t-fgg484/-3`
5			`3.92`
6
7			`DDR3_SDRAM/Components/MT41J64M16XX-187E`
8			`2500`
9			`0`
10			`1`
11			`FALSE`
12
13			`13`
14			`10`
15			`3`
16
17
18
19			`8(00)`
20			`6`
21			`Enable`
22			`RZQ/6`
23			`RZQ/4`
24			`0`
25			`Disabled`
26			`Disabled`
27			`Full Array`
28			`5`
29			`Enabled`
30			`Normal`
31			`NATIVE`
32			`Class II`
33			`Class II`
34			`UNCALIB_TERM`
35			`50 Ohms`
36
37
38
39			`Single-Ended`
40			`1`
41			`Disable`
42			`Single-Ended`
43			`One 128-bit bi-directional port`
44			`R7`
45			`W4`
46			`Port0`
47			`Bi-directional`
48			`ROW_BANK_COLUMN`
49			`Round Robin`
50			`0`
51			`0`
52			`0`
53			`0`
54			`0`
55			`0`
56			`0`
57			`0`
58			`0`
59			`0`
60			`0`
61			`0`
62
63

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Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [xs6_ddr3/] [ddr3/] [user_design/] [mig.prj] - Blame information for rev 64