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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [clk_source/] [xilinx_pll/] [xilinx_pll_sim/] [freq_gen.v] - Blame information for rev 48

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/*
 * freq_gen.v: Generates the frequency depending on the given period length while allowing manipulation using
 *      the inputs provided. Starts frequency generation on the first rising
 *      edge of the input clk after the period_stable input is 1.
 * author: Till Mahlburg
 * year: 2019-2020
 * organization: Universität Leipzig
 * license: ISC
 *
 */
 
// synthesis translate_off
 
`timescale 1 ns / 1 ps
 
module freq_gen (
        /* global multiplier in the PLL, multiplied by 1000 */
        input [31:0] M_1000,
        /* global divisor in the PLL */
        input [31:0] D,
        /* output specific divisor in the PLL, multiplied by 1000 */
        input [31:0] O_1000,
 
        input RST,
        input PWRDWN,
        /* informs the module if the given period length (ref_period) can be trusted */
        input period_stable,
        input [31:0] ref_period_1000,
        /* needed to achieve phase lock, by detecting the first rising edge of the clk
         * and aligning the output clk to it */
        input clk,
        output reg out,
        /* period length is multiplied by 1000 for higher precision */
        output reg [31:0] out_period_length_1000);
 
        /* tracks when to start the frequency generation */
        reg start;
 
        /* generate the wanted frequency */
        always begin
                if (PWRDWN) begin
                        out <= 1'bx;
                        start <= 1'bx;
                        #1;
                end else if (RST) begin
                        out <= 1'b0;
                        start <= 1'b0;
                        #1;
                end else if (ref_period_1000 > 0 && start) begin
                        /* The formula used is based on Equation 3-2 on page 72 of Xilinx UG472,
                         * but adjusted to calculate the period length not the frequency.
                         * Multiplying by 1.0 forces verilog to calculate with floating
                         * point number. Multiplying the out_period_length_1000 by 1000 is an
                         * easy solution to returning floating point numbers.
                         */
                        out_period_length_1000 <= ((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0)) * 1000);
                        out <= ~out;
                        #(((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0))) / 2.0);
                end else begin
                        out <= 1'b0;
                        #1;
                end
        end
 
        /* detect the first rising edge of the input clk, after period_stable is achieved */
        always @(posedge clk) begin
                if (period_stable && !start) begin
                        #((ref_period_1000 / 1000.0) - 1);
                        start <= 1'b1;
                end else if (!period_stable) begin
                        start <= 1'b0;
                end
        end
 
endmodule
 
// synthesis translate_on

Line No.	Rev	Author	Line
1	48	alirezamon	`/*`
2			`* freq_gen.v: Generates the frequency depending on the given period length while allowing manipulation using`
3			`* the inputs provided. Starts frequency generation on the first rising`
4			`* edge of the input clk after the period_stable input is 1.`
5			`* author: Till Mahlburg`
6			`* year: 2019-2020`
7			`* organization: Universität Leipzig`
8			`* license: ISC`
9			`*`
10			`*/`
11
12			`// synthesis translate_off`
13
14			`timescale 1 ns / 1 ps
15
16			`module freq_gen (`
17			`/* global multiplier in the PLL, multiplied by 1000 */`
18			`input [31:0] M_1000,`
19			`/* global divisor in the PLL */`
20			`input [31:0] D,`
21			`/* output specific divisor in the PLL, multiplied by 1000 */`
22			`input [31:0] O_1000,`
23
24			`input RST,`
25			`input PWRDWN,`
26			`/* informs the module if the given period length (ref_period) can be trusted */`
27			`input period_stable,`
28			`input [31:0] ref_period_1000,`
29			`/* needed to achieve phase lock, by detecting the first rising edge of the clk`
30			`* and aligning the output clk to it */`
31			`input clk,`
32			`output reg out,`
33			`/* period length is multiplied by 1000 for higher precision */`
34			`output reg [31:0] out_period_length_1000);`
35
36			`/* tracks when to start the frequency generation */`
37			`reg start;`
38
39			`/* generate the wanted frequency */`
40			`always begin`
41			`if (PWRDWN) begin`
42			`out <= 1'bx;`
43			`start <= 1'bx;`
44			`#1;`
45			`end else if (RST) begin`
46			`out <= 1'b0;`
47			`start <= 1'b0;`
48			`#1;`
49			`end else if (ref_period_1000 > 0 && start) begin`
50			`/* The formula used is based on Equation 3-2 on page 72 of Xilinx UG472,`
51			`* but adjusted to calculate the period length not the frequency.`
52			`* Multiplying by 1.0 forces verilog to calculate with floating`
53			`* point number. Multiplying the out_period_length_1000 by 1000 is an`
54			`* easy solution to returning floating point numbers.`
55			`*/`
56			`out_period_length_1000 <= ((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0)) * 1000);`
57			`out <= ~out;`
58			`#(((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0))) / 2.0);`
59			`end else begin`
60			`out <= 1'b0;`
61			`#1;`
62			`end`
63			`end`
64
65			`/* detect the first rising edge of the input clk, after period_stable is achieved */`
66			`always @(posedge clk) begin`
67			`if (period_stable && !start) begin`
68			`#((ref_period_1000 / 1000.0) - 1);`
69			`start <= 1'b1;`
70			`end else if (!period_stable) begin`
71			`start <= 1'b0;`
72			`end`
73			`end`
74
75			`endmodule`
76
77			`// synthesis translate_on`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [clk_source/] [xilinx_pll/] [xilinx_pll_sim/] [freq_gen.v] - Blame information for rev 48