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alirezamon |
/*
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* phase_shift.v: Shifts the input clock by the given degree and can change
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it's duty cycle.
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* author: Till Mahlburg
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* year: 2019-2020
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* organization: Universität Leipzig
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* license: ISC
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*
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*/
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// synthesis translate_off
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`timescale 1 ns / 1 ps
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module phase_shift (
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input RST,
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input PWRDWN,
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input clk,
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/* shift in degrees */
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input signed [31:0] shift_1000,
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/* period length of the clock */
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input [31:0] clk_period_1000,
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/* duty cycle in percent */
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input [6:0] duty_cycle,
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output reg lock,
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output reg clk_shifted);
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/* The formulas used here are composed of the following:
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* - clk_period_1000 / 1000.0 calculates the actual period length, which
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* has been multiplied by 1000 to enable a higher precision.
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* - shift * ((clk_period_1000 / 1000.0) / 360.0) calculate the basic shift
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* as a multiple of a 360th of the period of the clk to shift
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* - if the desired shift is negative, we just add a shift by
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* 360 degrees and add the (negative) shift:
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* clk_period + (shift * (clk_period / 360.0))
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* - to calculate the duty cycle, we delay or rush the output of
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* 0 by adding (or subtracting) the desired duty cycle in 100th
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* of the input clk period from the default (50):
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* (duty_cycle + 50.0) * (clk_period / 100.0)
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*/
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/* calculate when to put out high */
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always @(posedge clk or posedge RST or posedge PWRDWN) begin
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if (!RST && !PWRDWN) begin
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if (shift_1000 < 0) begin
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clk_shifted <= #((clk_period_1000 / 1000.0) + ((shift_1000 / 1000.0) * ((clk_period_1000 / 1000.0) / 360.0))) 1;
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end else begin
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clk_shifted <= #((shift_1000 / 1000.0) * ((clk_period_1000 / 1000.0) / 360.0)) 1;
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end
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end
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end
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/* calculate when to put out low and return when the phase and duty cycle is correctly set */
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always @(negedge clk or posedge RST) begin
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if (RST) begin
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clk_shifted <= 1'b0;
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lock <= 1'b0;
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end else if (lock !== 1'bx) begin
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if (shift_1000 < 0) begin
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clk_shifted <= #((clk_period_1000 / 1000.0) + ((shift_1000/ 1000.0) * ((clk_period_1000 / 1000.0) / 360.0)) + ((duty_cycle + 50.0) * ((clk_period_1000 / 1000.0) / 100.0))) 0;
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lock <= #((clk_period_1000 / 1000.0) + ((shift_1000/ 1000.0) * ((clk_period_1000 / 1000.0) / 360.0)) + ((duty_cycle + 50.0) * ((clk_period_1000 / 1000.0) / 100.0))) 1'b1;
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end else begin
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clk_shifted <= #((shift_1000/ 1000.0) * ((clk_period_1000 / 1000.0) / 360.0) + ((duty_cycle + 50.0) * ((clk_period_1000 / 1000.0) / 100.0))) 0;
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lock <= #((shift_1000/ 1000.0) * ((clk_period_1000 / 1000.0) / 360.0) + ((duty_cycle + 50.0) * ((clk_period_1000 / 1000.0) / 100.0))) 1'b1;
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end
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end
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end
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/* PWRDWN for good */
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always begin
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if (PWRDWN) begin
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clk_shifted <= 1'bx;
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lock <= 1'bx;
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#0.001;
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end else begin
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#1;
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end
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end
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endmodule
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// synthesis translate_on
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