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alirezamon |
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/**************************************************************************
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** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
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** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
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****************************************************************************/
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/**********************************************************************
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** File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topolgy/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
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**
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** Copyright (C) 2014-2021 Alireza Monemi
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**
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** This file is part of ProNoC 2.1.0
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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******************************************************************************/
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`include "pronoc_def.v"
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/*****************************
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* Tcustom1Rcustom_look_ahead_routing_genvar
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******************************/
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module Tcustom1Rcustom_look_ahead_routing_genvar #(
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parameter RAw = 3,
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parameter EAw = 3,
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parameter DSTPw=4,
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parameter CURRENT_R_ADDR=0
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)
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(
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dest_e_addr,
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src_e_addr,
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destport,
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reset,
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clk
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);
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input [EAw-1 :0] dest_e_addr;
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input [EAw-1 :0] src_e_addr;
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output [DSTPw-1 :0] destport;
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input reset,clk;
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reg [EAw-1 :0] dest_e_addr_delay;
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reg [EAw-1 :0] src_e_addr_delay;
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always @ (`pronoc_clk_reset_edge )begin
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if(`pronoc_reset) begin
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dest_e_addr_delay<={EAw{1'b0}};
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src_e_addr_delay<={EAw{1'b0}};
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end else begin
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dest_e_addr_delay<=dest_e_addr;
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src_e_addr_delay<=src_e_addr;
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end
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end
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custom1_look_ahead_routing_genvar_comb #(
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.RAw(RAw),
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.EAw(EAw),
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.DSTPw(DSTPw),
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.CURRENT_R_ADDR(CURRENT_R_ADDR)
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)
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lkp_cmb
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(
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.dest_e_addr(dest_e_addr_delay),
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.src_e_addr(src_e_addr_delay),
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.destport(destport)
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);
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endmodule
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/*******************
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* Tcustom1Rcustom_look_ahead_routing_genvar_comb
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********************/
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module Tcustom1Rcustom_look_ahead_routing_genvar_comb #(
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parameter RAw = 3,
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parameter EAw = 3,
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parameter DSTPw=4,
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parameter CURRENT_R_ADDR=0
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)
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(
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dest_e_addr,
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src_e_addr,
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destport
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);
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input [EAw-1 :0] dest_e_addr;
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input [EAw-1 :0] src_e_addr;
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output reg [DSTPw-1 :0] destport;
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localparam [EAw-1 : 0] E0=0;
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localparam [EAw-1 : 0] E1=1;
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localparam [EAw-1 : 0] E2=2;
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localparam [EAw-1 : 0] E3=3;
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localparam [EAw-1 : 0] E4=4;
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localparam [EAw-1 : 0] E5=5;
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localparam [EAw-1 : 0] E6=6;
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localparam [EAw-1 : 0] E7=7;
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localparam [EAw-1 : 0] E8=8;
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localparam [EAw-1 : 0] E9=9;
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localparam [EAw-1 : 0] E10=10;
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localparam [EAw-1 : 0] E11=11;
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localparam [EAw-1 : 0] E12=12;
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localparam [EAw-1 : 0] E13=13;
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localparam [EAw-1 : 0] E14=14;
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localparam [EAw-1 : 0] E15=15;
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generate
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if(CURRENT_R_ADDR == 0) begin :R0
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always@(*)begin
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destport= 0;
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case({src_e_addr,dest_e_addr})
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{E0,E9},{E0,E10}: begin
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destport= 0;
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end
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{E0,E2},{E0,E3},{E0,E8},{E0,E11},{E0,E12}: begin
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destport= 1;
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end
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{E0,E1},{E0,E4},{E0,E5},{E0,E6},{E0,E7},{E0,E13},{E0,E14},{E0,E15}: begin
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destport= 2;
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end
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endcase
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end
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end//R0
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if(CURRENT_R_ADDR == 1) begin :R1
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always@(*)begin
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destport= 0;
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case({src_e_addr,dest_e_addr})
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{E1,E2},{E1,E7},{E2,E7}: begin
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destport= 0;
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end
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{E1,E3},{E1,E4},{E1,E5},{E1,E6},{E1,E8},{E1,E9},{E1,E11},{E1,E12},{E1,E13},{E1,E14},{E1,E15},{E2,E9},{E2,E12}: begin
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destport= 1;
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end
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{E1,E0},{E1,E10},{E2,E0},{E2,E10}: begin
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destport= 2;
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end
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endcase
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end
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end//R1
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if(CURRENT_R_ADDR == 2) begin :R2
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always@(*)begin
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destport= 0;
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case({src_e_addr,dest_e_addr})
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{E1,E11},{E2,E1},{E2,E11}: begin
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destport= 0;
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end
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{E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E0},{E2,E4},{E2,E5},{E2,E6},{E2,E7},{E2,E8},{E2,E9},{E2,E10},{E2,E12},{E2,E13},{E2,E14},{E2,E15}: begin
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destport= 1;
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end
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{E1,E3},{E2,E3}: begin
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destport= 3;
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end
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endcase
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end
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end//R2
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if(CURRENT_R_ADDR == 3) begin :R3
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always@(*)begin
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destport= 0;
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case({src_e_addr,dest_e_addr})
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{E3,E4},{E3,E11}: begin
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destport= 0;
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end
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{E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E10},{E3,E12},{E3,E13},{E3,E14}: begin
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destport= 1;
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end
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{E3,E2}: begin
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destport= 2;
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end
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{E3,E0},{E3,E5},{E3,E9},{E3,E15}: begin
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destport= 3;
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end
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endcase
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end
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end//R3
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if(CURRENT_R_ADDR == 4) begin :R4
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always@(*)begin
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destport= 0;
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case({src_e_addr,dest_e_addr})
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{E3,E13},{E4,E3},{E4,E13},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin
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destport= 0;
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end
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{E4,E2},{E4,E11},{E4,E14}: begin
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destport= 1;
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end
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{E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15}: begin
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destport= 2;
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end
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{E3,E6},{E4,E6}: begin
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destport= 3;
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end
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{E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E7},{E4,E8},{E4,E10}: begin
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destport= 4;
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end
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endcase
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end
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end//R4
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if(CURRENT_R_ADDR == 5) begin :R5
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always@(*)begin
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destport= 0;
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case({src_e_addr,dest_e_addr})
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{E0,E6},{E0,E15},{E3,E9},{E3,E15},{E4,E9},{E4,E15},{E5,E6},{E5,E9},{E5,E15},{E6,E9},{E6,E15},{E9,E6},{E9,E15},{E13,E9},{E14,E9},{E15,E9}: begin
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destport= 0;
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end
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{E0,E4},{E0,E13},{E4,E12},{E5,E1},{E5,E2},{E5,E3},{E5,E4},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E5,E13},{E5,E14},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin
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destport= 1;
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end
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228 |
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{E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11}: begin
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229 |
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destport= 2;
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230 |
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end
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231 |
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{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E11,E0},{E13,E0},{E15,E0}: begin
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232 |
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destport= 3;
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233 |
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end
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234 |
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endcase
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end
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end//R5
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237 |
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238 |
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if(CURRENT_R_ADDR == 6) begin :R6
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239 |
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always@(*)begin
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240 |
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destport= 0;
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241 |
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case({src_e_addr,dest_e_addr})
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242 |
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{E0,E13},{E3,E5},{E4,E5},{E5,E13},{E6,E5},{E6,E13},{E9,E13}: begin
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243 |
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destport= 0;
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244 |
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end
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245 |
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{E3,E15},{E4,E12},{E4,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin
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246 |
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destport= 1;
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247 |
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end
|
248 |
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{E0,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E9,E3},{E9,E4}: begin
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249 |
|
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destport= 2;
|
250 |
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end
|
251 |
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{E3,E0},{E3,E9},{E4,E0},{E4,E9},{E6,E0},{E6,E9}: begin
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252 |
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destport= 3;
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253 |
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end
|
254 |
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{E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14}: begin
|
255 |
|
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destport= 4;
|
256 |
|
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end
|
257 |
|
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endcase
|
258 |
|
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end
|
259 |
|
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end//R6
|
260 |
|
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|
261 |
|
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if(CURRENT_R_ADDR == 7) begin :R7
|
262 |
|
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always@(*)begin
|
263 |
|
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destport= 0;
|
264 |
|
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case({src_e_addr,dest_e_addr})
|
265 |
|
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{E0,E1},{E1,E8},{E1,E10},{E2,E10},{E3,E1},{E3,E10},{E4,E1},{E4,E10},{E5,E1},{E6,E1},{E7,E1},{E7,E8},{E7,E10},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E11,E10},{E12,E1},{E13,E1},{E13,E10},{E14,E1},{E14,E10},{E15,E1}: begin
|
266 |
|
|
destport= 0;
|
267 |
|
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end
|
268 |
|
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{E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12}: begin
|
269 |
|
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destport= 1;
|
270 |
|
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end
|
271 |
|
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{E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15}: begin
|
272 |
|
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destport= 2;
|
273 |
|
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end
|
274 |
|
|
{E1,E0},{E2,E0},{E7,E0},{E14,E0}: begin
|
275 |
|
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destport= 3;
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276 |
|
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end
|
277 |
|
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endcase
|
278 |
|
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end
|
279 |
|
|
end//R7
|
280 |
|
|
|
281 |
|
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if(CURRENT_R_ADDR == 8) begin :R8
|
282 |
|
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always@(*)begin
|
283 |
|
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destport= 0;
|
284 |
|
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case({src_e_addr,dest_e_addr})
|
285 |
|
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{E1,E12},{E2,E12},{E3,E7},{E4,E7},{E7,E12},{E7,E14},{E8,E7},{E8,E12},{E8,E14},{E9,E7},{E11,E7},{E13,E7},{E14,E7}: begin
|
286 |
|
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destport= 0;
|
287 |
|
|
end
|
288 |
|
|
{E1,E15},{E7,E5},{E7,E15},{E8,E4},{E8,E5},{E8,E15}: begin
|
289 |
|
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destport= 1;
|
290 |
|
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end
|
291 |
|
|
{E1,E4},{E1,E9},{E2,E9},{E3,E10},{E4,E10},{E7,E3},{E7,E4},{E7,E6},{E7,E9},{E7,E13},{E8,E0},{E8,E3},{E8,E6},{E8,E9},{E8,E13},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin
|
292 |
|
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destport= 2;
|
293 |
|
|
end
|
294 |
|
|
{E3,E1},{E4,E1},{E8,E1},{E8,E10},{E9,E1},{E11,E1},{E13,E1},{E14,E1}: begin
|
295 |
|
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destport= 3;
|
296 |
|
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end
|
297 |
|
|
{E7,E2},{E7,E11},{E8,E2},{E8,E11}: begin
|
298 |
|
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destport= 4;
|
299 |
|
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end
|
300 |
|
|
endcase
|
301 |
|
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end
|
302 |
|
|
end//R8
|
303 |
|
|
|
304 |
|
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if(CURRENT_R_ADDR == 9) begin :R9
|
305 |
|
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always@(*)begin
|
306 |
|
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destport= 0;
|
307 |
|
|
case({src_e_addr,dest_e_addr})
|
308 |
|
|
{E0,E5},{E0,E12},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E9,E5},{E9,E12},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin
|
309 |
|
|
destport= 0;
|
310 |
|
|
end
|
311 |
|
|
{E0,E11},{E0,E14},{E0,E15},{E9,E2},{E9,E11},{E9,E15}: begin
|
312 |
|
|
destport= 1;
|
313 |
|
|
end
|
314 |
|
|
{E0,E4},{E0,E6},{E0,E13},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin
|
315 |
|
|
destport= 2;
|
316 |
|
|
end
|
317 |
|
|
{E9,E10}: begin
|
318 |
|
|
destport= 3;
|
319 |
|
|
end
|
320 |
|
|
{E0,E8},{E9,E1},{E9,E7},{E9,E8}: begin
|
321 |
|
|
destport= 4;
|
322 |
|
|
end
|
323 |
|
|
endcase
|
324 |
|
|
end
|
325 |
|
|
end//R9
|
326 |
|
|
|
327 |
|
|
if(CURRENT_R_ADDR == 10) begin :R10
|
328 |
|
|
always@(*)begin
|
329 |
|
|
destport= 0;
|
330 |
|
|
case({src_e_addr,dest_e_addr})
|
331 |
|
|
{E0,E7},{E1,E0},{E2,E0},{E5,E7},{E6,E7},{E7,E0},{E10,E0},{E10,E7},{E10,E12},{E12,E7},{E14,E0},{E15,E7}: begin
|
332 |
|
|
destport= 0;
|
333 |
|
|
end
|
334 |
|
|
{E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15}: begin
|
335 |
|
|
destport= 1;
|
336 |
|
|
end
|
337 |
|
|
{E10,E9}: begin
|
338 |
|
|
destport= 2;
|
339 |
|
|
end
|
340 |
|
|
{E0,E1},{E5,E1},{E6,E1},{E10,E1},{E12,E1},{E15,E1}: begin
|
341 |
|
|
destport= 3;
|
342 |
|
|
end
|
343 |
|
|
{E10,E8}: begin
|
344 |
|
|
destport= 4;
|
345 |
|
|
end
|
346 |
|
|
endcase
|
347 |
|
|
end
|
348 |
|
|
end//R10
|
349 |
|
|
|
350 |
|
|
if(CURRENT_R_ADDR == 11) begin :R11
|
351 |
|
|
always@(*)begin
|
352 |
|
|
destport= 0;
|
353 |
|
|
case({src_e_addr,dest_e_addr})
|
354 |
|
|
{E0,E2},{E0,E3},{E1,E3},{E1,E14},{E2,E3},{E2,E14},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E11,E3},{E11,E14},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin
|
355 |
|
|
destport= 0;
|
356 |
|
|
end
|
357 |
|
|
{E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15}: begin
|
358 |
|
|
destport= 1;
|
359 |
|
|
end
|
360 |
|
|
{E1,E6},{E2,E4},{E2,E6},{E2,E13},{E11,E4},{E11,E6},{E11,E13}: begin
|
361 |
|
|
destport= 2;
|
362 |
|
|
end
|
363 |
|
|
{E2,E8},{E3,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10}: begin
|
364 |
|
|
destport= 3;
|
365 |
|
|
end
|
366 |
|
|
endcase
|
367 |
|
|
end
|
368 |
|
|
end//R11
|
369 |
|
|
|
370 |
|
|
if(CURRENT_R_ADDR == 12) begin :R12
|
371 |
|
|
always@(*)begin
|
372 |
|
|
destport= 0;
|
373 |
|
|
case({src_e_addr,dest_e_addr})
|
374 |
|
|
{E0,E8},{E1,E9},{E1,E15},{E2,E9},{E5,E8},{E5,E10},{E6,E8},{E6,E10},{E7,E9},{E8,E9},{E8,E10},{E9,E8},{E9,E10},{E10,E8},{E10,E9},{E10,E15},{E11,E9},{E12,E8},{E12,E9},{E12,E10},{E12,E15},{E15,E8},{E15,E10}: begin
|
375 |
|
|
destport= 0;
|
376 |
|
|
end
|
377 |
|
|
{E0,E2},{E0,E3},{E0,E11},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E2},{E10,E11},{E10,E14},{E12,E1},{E12,E2},{E12,E7},{E12,E11},{E12,E14},{E15,E1},{E15,E7}: begin
|
378 |
|
|
destport= 2;
|
379 |
|
|
end
|
380 |
|
|
{E8,E0},{E8,E4},{E9,E1},{E9,E7},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E0},{E12,E3},{E12,E4},{E12,E6},{E12,E13}: begin
|
381 |
|
|
destport= 3;
|
382 |
|
|
end
|
383 |
|
|
{E8,E5},{E10,E5},{E12,E5}: begin
|
384 |
|
|
destport= 4;
|
385 |
|
|
end
|
386 |
|
|
endcase
|
387 |
|
|
end
|
388 |
|
|
end//R12
|
389 |
|
|
|
390 |
|
|
if(CURRENT_R_ADDR == 13) begin :R13
|
391 |
|
|
always@(*)begin
|
392 |
|
|
destport= 0;
|
393 |
|
|
case({src_e_addr,dest_e_addr})
|
394 |
|
|
{E0,E4},{E1,E4},{E1,E6},{E2,E4},{E2,E6},{E3,E6},{E3,E14},{E4,E6},{E4,E14},{E5,E4},{E5,E14},{E6,E4},{E7,E4},{E7,E6},{E8,E4},{E8,E6},{E9,E4},{E9,E14},{E10,E4},{E10,E6},{E11,E4},{E11,E6},{E12,E4},{E12,E6},{E13,E4},{E13,E6},{E13,E14},{E14,E4},{E14,E6},{E15,E4},{E15,E6}: begin
|
395 |
|
|
destport= 0;
|
396 |
|
|
end
|
397 |
|
|
{E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15}: begin
|
398 |
|
|
destport= 1;
|
399 |
|
|
end
|
400 |
|
|
{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin
|
401 |
|
|
destport= 2;
|
402 |
|
|
end
|
403 |
|
|
{E3,E1},{E3,E7},{E3,E8},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10}: begin
|
404 |
|
|
destport= 3;
|
405 |
|
|
end
|
406 |
|
|
{E4,E2},{E4,E11},{E5,E2},{E13,E2},{E13,E11}: begin
|
407 |
|
|
destport= 4;
|
408 |
|
|
end
|
409 |
|
|
endcase
|
410 |
|
|
end
|
411 |
|
|
end//R13
|
412 |
|
|
|
413 |
|
|
if(CURRENT_R_ADDR == 14) begin :R14
|
414 |
|
|
always@(*)begin
|
415 |
|
|
destport= 0;
|
416 |
|
|
case({src_e_addr,dest_e_addr})
|
417 |
|
|
{E0,E11},{E2,E8},{E2,E13},{E2,E15},{E3,E8},{E4,E8},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E7,E13},{E7,E15},{E8,E11},{E8,E13},{E8,E15},{E9,E11},{E10,E11},{E11,E8},{E11,E13},{E11,E15},{E12,E11},{E13,E8},{E13,E11},{E13,E15},{E14,E8},{E14,E11},{E14,E13},{E14,E15},{E15,E11}: begin
|
418 |
|
|
destport= 0;
|
419 |
|
|
end
|
420 |
|
|
{E3,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12}: begin
|
421 |
|
|
destport= 1;
|
422 |
|
|
end
|
423 |
|
|
{E0,E2},{E1,E4},{E2,E4},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E7,E3},{E7,E4},{E8,E2},{E8,E3},{E9,E2},{E10,E2},{E11,E4},{E12,E2},{E13,E2},{E14,E2},{E14,E3},{E14,E4},{E15,E2}: begin
|
424 |
|
|
destport= 2;
|
425 |
|
|
end
|
426 |
|
|
{E0,E3},{E1,E6},{E1,E13},{E2,E6},{E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E7,E6},{E8,E6},{E11,E1},{E11,E6},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E6},{E14,E7},{E14,E10}: begin
|
427 |
|
|
destport= 3;
|
428 |
|
|
end
|
429 |
|
|
{E1,E5},{E2,E5},{E7,E5},{E11,E0},{E11,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9}: begin
|
430 |
|
|
destport= 4;
|
431 |
|
|
end
|
432 |
|
|
endcase
|
433 |
|
|
end
|
434 |
|
|
end//R14
|
435 |
|
|
|
436 |
|
|
if(CURRENT_R_ADDR == 15) begin :R15
|
437 |
|
|
always@(*)begin
|
438 |
|
|
destport= 0;
|
439 |
|
|
case({src_e_addr,dest_e_addr})
|
440 |
|
|
{E0,E14},{E1,E5},{E1,E13},{E2,E5},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E6,E14},{E7,E5},{E8,E5},{E10,E5},{E10,E13},{E10,E14},{E11,E5},{E11,E12},{E12,E5},{E12,E13},{E12,E14},{E13,E5},{E13,E12},{E14,E5},{E14,E12},{E15,E5},{E15,E12},{E15,E13},{E15,E14}: begin
|
441 |
|
|
destport= 0;
|
442 |
|
|
end
|
443 |
|
|
{E8,E4},{E10,E3},{E10,E4},{E11,E9},{E12,E3},{E12,E4},{E15,E3},{E15,E4}: begin
|
444 |
|
|
destport= 2;
|
445 |
|
|
end
|
446 |
|
|
{E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E10,E6},{E11,E0},{E12,E6},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E1},{E15,E6},{E15,E7},{E15,E9},{E15,E10}: begin
|
447 |
|
|
destport= 3;
|
448 |
|
|
end
|
449 |
|
|
{E0,E2},{E0,E3},{E0,E11},{E5,E8},{E5,E11},{E6,E2},{E6,E8},{E6,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E15,E2},{E15,E8},{E15,E11}: begin
|
450 |
|
|
destport= 4;
|
451 |
|
|
end
|
452 |
|
|
endcase
|
453 |
|
|
end
|
454 |
|
|
end//R15
|
455 |
|
|
|
456 |
|
|
endgenerate
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
endmodule
|
461 |
|
|
|
462 |
|
|
|