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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx-sprs.v] - Blame information for rev 48

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/* ****************************************************************************
  This Source Code Form is subject to the terms of the
  Open Hardware Description License, v. 1.0. If a copy
  of the OHDL was not distributed with this file, You
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
  Description: SPR definitions
 
  Copyright (C) 2012 Authors
 
  Author(s): Julius Baxter <juliusbaxter@gmail.com>
 
***************************************************************************** */
`define SPR_BASE(x)   (x/(2**11))
`define SPR_OFFSET(x) (x%(2**11))
 
//
// Addresses
//
`define OR1K_SPR_SYS_BASE       {4'd0}
`define OR1K_SPR_VR_ADDR        {5'd0,11'd0}
`define OR1K_SPR_UPR_ADDR       {5'd0,11'd1}
`define OR1K_SPR_CPUCFGR_ADDR   {5'd0,11'd2}
`define OR1K_SPR_DMMUCFGR_ADDR  {5'd0,11'd3}
`define OR1K_SPR_IMMUCFGR_ADDR  {5'd0,11'd4}
`define OR1K_SPR_DCCFGR_ADDR    {5'd0,11'd5}
`define OR1K_SPR_ICCFGR_ADDR    {5'd0,11'd6}
`define OR1K_SPR_DCFGR_ADDR     {5'd0,11'd7}
`define OR1K_SPR_PCCFGR_ADDR    {5'd0,11'd8}
`define OR1K_SPR_VR2_ADDR       {5'd0,11'd9}
`define OR1K_SPR_AVR_ADDR       {5'd0,11'd10}
`define OR1K_SPR_EVBAR_ADDR     {5'd0,11'd11}
`define OR1K_SPR_AECR_ADDR      {5'd0,11'd12}
`define OR1K_SPR_AESR_ADDR      {5'd0,11'd13}
`define OR1K_SPR_NPC_ADDR       {5'd0,11'd16}
`define OR1K_SPR_SR_ADDR        {5'd0,11'd17}
`define OR1K_SPR_PPC_ADDR       {5'd0,11'd18}
`define OR1K_SPR_FPCSR_ADDR     {5'd0,11'd20}
`define OR1K_SPR_ISR0_ADDR      {5'd0,11'd21}
`define OR1K_SPR_EPCR0_ADDR     {5'd0,11'd32}
`define OR1K_SPR_EEAR0_ADDR     {5'd0,11'd48}
`define OR1K_SPR_ESR0_ADDR      {5'd0,11'd64}
`define OR1K_SPR_COREID_ADDR    {5'd0,11'd128}
`define OR1K_SPR_NUMCORES_ADDR  {5'd0,11'd129}
`define OR1K_SPR_GPR0_ADDR      {5'd0,11'd1024}
 
`define OR1K_SPR_DMMU_BASE      {4'd1}
`define OR1K_SPR_DMMUCR_ADDR    {5'd1,11'd0}
`define OR1K_SPR_DMMUPR_ADDR    {5'd1,11'd1}
`define OR1K_SPR_DTLBEIR_ADDR   {5'd1,11'd2}
`define OR1K_SPR_DATBMR0_ADDR   {5'd1,11'd4}
`define OR1K_SPR_DATBTR0_ADDR   {5'd1,11'd8}
`define OR1K_SPR_DTLBW0MR0_ADDR {5'd1,11'd512}
`define OR1K_SPR_DTLBW0TR0_ADDR {5'd1,11'd640}
`define OR1K_SPR_DTLBW1MR0_ADDR {5'd1,11'd768}
`define OR1K_SPR_DTLBW1TR0_ADDR {5'd1,11'd896}
`define OR1K_SPR_DTLBW2MR0_ADDR {5'd1,11'd1024}
`define OR1K_SPR_DTLBW2TR0_ADDR {5'd1,11'd1152}
`define OR1K_SPR_DTLBW3MR0_ADDR {5'd1,11'd1280}
`define OR1K_SPR_DTLBW3TR0_ADDR {5'd1,11'd1408}
 
`define OR1K_SPR_IMMU_BASE      {4'd2}
`define OR1K_SPR_IMMUCR_ADDR    {5'd2,11'd0}
`define OR1K_SPR_IMMUPR_ADDR    {5'd2,11'd1}
`define OR1K_SPR_ITLBEIR_ADDR   {5'd2,11'd2}
`define OR1K_SPR_IATBMR0_ADDR   {5'd2,11'd4}
`define OR1K_SPR_IATBTR0_ADDR   {5'd2,11'd8}
`define OR1K_SPR_ITLBW0MR0_ADDR {5'd2,11'd512}
`define OR1K_SPR_ITLBW0TR0_ADDR {5'd2,11'd640}
`define OR1K_SPR_ITLBW1MR0_ADDR {5'd2,11'd768}
`define OR1K_SPR_ITLBW1TR0_ADDR {5'd2,11'd896}
`define OR1K_SPR_ITLBW2MR0_ADDR {5'd2,11'd1024}
`define OR1K_SPR_ITLBW2TR0_ADDR {5'd2,11'd1152}
`define OR1K_SPR_ITLBW3MR0_ADDR {5'd2,11'd1280}
`define OR1K_SPR_ITLBW3TR0_ADDR {5'd2,11'd1408}
 
`define OR1K_SPR_DC_BASE        {4'd3}
`define OR1K_SPR_DCCR_ADDR      {5'd3,11'd0}
`define OR1K_SPR_DCBPR_ADDR     {5'd3,11'd1}
`define OR1K_SPR_DCBFR_ADDR     {5'd3,11'd2}
`define OR1K_SPR_DCBIR_ADDR     {5'd3,11'd3}
`define OR1K_SPR_DCBWR_ADDR     {5'd3,11'd4}
`define OR1K_SPR_DCBLR_ADDR     {5'd3,11'd5}
 
`define OR1K_SPR_IC_BASE        {4'd4}
`define OR1K_SPR_ICCR_ADDR      {5'd4,11'd0}
`define OR1K_SPR_ICBPR_ADDR     {5'd4,11'd1}
`define OR1K_SPR_ICBIR_ADDR     {5'd4,11'd2}
`define OR1K_SPR_ICBLR_ADDR     {5'd4,11'd3}
 
`define OR1K_SPR_MAC_BASE       {4'd5}
`define OR1K_SPR_MACLO_ADDR     {5'd5,11'd1}
`define OR1K_SPR_MACHI_ADDR     {5'd5,11'd2}
 
`define OR1K_SPR_DU_BASE        {4'd6}
`define OR1K_SPR_DVR0_ADDR      {5'd6,11'd0}
`define OR1K_SPR_DCR0_ADDR      {5'd6,11'd8}
`define OR1K_SPR_DMR1_ADDR      {5'd6,11'd16}
`define OR1K_SPR_DMR2_ADDR      {5'd6,11'd17}
`define OR1K_SPR_DCWR0_ADDR     {5'd6,11'd18}
`define OR1K_SPR_DSR_ADDR       {5'd6,11'd20}
`define OR1K_SPR_DRR_ADDR       {5'd6,11'd21}
 
`define OR1K_SPR_PC_BASE        {4'd7}
`define OR1K_SPR_PCCR0_ADDR     {5'd7,11'd0}
`define OR1K_SPR_PCCR1_ADDR     {5'd7,11'd1}
`define OR1K_SPR_PCCR2_ADDR     {5'd7,11'd2}
`define OR1K_SPR_PCCR3_ADDR     {5'd7,11'd3}
`define OR1K_SPR_PCCR4_ADDR     {5'd7,11'd4}
`define OR1K_SPR_PCCR5_ADDR     {5'd7,11'd5}
`define OR1K_SPR_PCCR6_ADDR     {5'd7,11'd6}
`define OR1K_SPR_PCCR7_ADDR     {5'd7,11'd7}
`define OR1K_SPR_PCMR0_ADDR     {5'd7,11'd8}
`define OR1K_SPR_PCMR1_ADDR     {5'd7,11'd9}
`define OR1K_SPR_PCMR2_ADDR     {5'd7,11'd10}
`define OR1K_SPR_PCMR3_ADDR     {5'd7,11'd11}
`define OR1K_SPR_PCMR4_ADDR     {5'd7,11'd12}
`define OR1K_SPR_PCMR5_ADDR     {5'd7,11'd13}
`define OR1K_SPR_PCMR6_ADDR     {5'd7,11'd14}
`define OR1K_SPR_PCMR7_ADDR     {5'd7,11'd15}
 
`define OR1K_SPR_PM_BASE        {4'd8}
`define OR1K_SPR_PMR_ADDR       {5'd8,11'd0}
 
`define OR1K_SPR_PIC_BASE       {4'd9}
`define OR1K_SPR_PICMR_ADDR     {5'd9,11'd0}
`define OR1K_SPR_PICSR_ADDR     {5'd9,11'd2}
 
`define OR1K_SPR_TT_BASE        {4'd10}
`define OR1K_SPR_TTMR_ADDR      {5'd10,11'd0}
`define OR1K_SPR_TTCR_ADDR      {5'd10,11'd1}
 
`define OR1K_SPR_FPU_BASE       {4'd11}
 
//
// Register bit defines
//
 
// Supervision Register
`define OR1K_SPR_SR_SM     0  /* Supervisor mode */
`define OR1K_SPR_SR_TEE    1  /* Timer exception enable */
`define OR1K_SPR_SR_IEE    2  /* Interrupt exception enable */
`define OR1K_SPR_SR_DCE    3  /* Data cache enable */
`define OR1K_SPR_SR_ICE    4  /* Instruction cache enable */
`define OR1K_SPR_SR_DME    5  /* Data MMU enable */
`define OR1K_SPR_SR_IME    6  /* Instruction MMU enable */
`define OR1K_SPR_SR_LEE    7  /* Little-endian enable */
`define OR1K_SPR_SR_CE     8  /* CID enable */
`define OR1K_SPR_SR_F      9  /* Flag */
`define OR1K_SPR_SR_CY    10  /* Carry flag */
`define OR1K_SPR_SR_OV    11  /* Overflow flag */
`define OR1K_SPR_SR_OVE   12  /* Overflow exception enable */
`define OR1K_SPR_SR_DSX   13  /* Delay slot exception */
`define OR1K_SPR_SR_EPH   14  /* Exception prefix high */
`define OR1K_SPR_SR_FO    15  /* Fixed to one */
`define OR1K_SPR_SR_SUMRA 16  /* SPR user read mode access */
`define OR1K_SPR_SR_RESERVED 27:17 /* Reserved */
`define OR1K_SPR_SR_CID      31:28 /* Context ID */
 
// Version register - DEPRECATED
`define OR1K_SPR_VR_REV   5:0  /* Revision */
`define OR1K_SPR_VR_UVRP  6  /* Updated Version Registers Present */
`define OR1K_SPR_VR_RESERVED 15:7 /* Reserved */
`define OR1K_SPR_VR_CFG   23:16  /* Configuration Template */
`define OR1K_SPR_VR_VER   31:24  /* Version */
 
 
// Unit Present register
`define OR1K_SPR_UPR_UP    0
`define OR1K_SPR_UPR_DCP   1
`define OR1K_SPR_UPR_ICP   2
`define OR1K_SPR_UPR_DMP   3
`define OR1K_SPR_UPR_IMP   4
`define OR1K_SPR_UPR_MP    5
`define OR1K_SPR_UPR_DUP   6
`define OR1K_SPR_UPR_PCUP  7
`define OR1K_SPR_UPR_PICP  8
`define OR1K_SPR_UPR_PMP   9
`define OR1K_SPR_UPR_TTP  10
`define OR1K_SPR_UPR_RESERVED 23:11
`define OR1K_SPR_UPR_CUP   31:24
 
// CPU Configuration register
`define OR1K_SPR_CPUCFGR_NSGF   3:0 /* Number of shadow GPRs */
`define OR1K_SPR_CPUCFGR_CFG    4
`define OR1K_SPR_CPUCFGR_OB32S  5
`define OR1K_SPR_CPUCFGR_OB64S  6
`define OR1K_SPR_CPUCFGR_OF32S  7
`define OR1K_SPR_CPUCFGR_OF64S  8
`define OR1K_SPR_CPUCFGR_OV64S  9
`define OR1K_SPR_CPUCFGR_ND     10 /* No delay-slot implementation */
`define OR1K_SPR_CPUCFGR_AVRP   11 /* Arch. version registers */
`define OR1K_SPR_CPUCFGR_EVBARP 12 /* Exception vector base addr reg */
`define OR1K_SPR_CPUCFGR_ISRP   13 /* Implementation specific regs */
`define OR1K_SPR_CPUCFGR_AECSRP 14 /* Arith. exception regs */
`define OR1K_SPR_CPUCFGR_RESERVED 31:15
 
// Version register 2 (new with OR1K 1.0)
`define OR1K_SPR_VR2_VER 23:0
`define OR1K_SPR_VR2_CPUID 31:24
 
// Architecture Version register
`define OR1K_SPR_AVR_RESERVED 7:0
`define OR1K_SPR_AVR_REV 15:8
`define OR1K_SPR_AVR_MIN 23:16
`define OR1K_SPR_AVR_MAJ 31:24
 
// Exception Vector Base Address register
`define OR1K_SPR_EVBAR_RESERVED 12:0
`define OR1K_SPR_EVBAR_EVBA 31:13
 
// Arithmetic Exception Control register
`define OR1K_SPR_AECR_CYADDE    0
`define OR1K_SPR_AECR_OVADDE    1
`define OR1K_SPR_AECR_CYMULE    2
`define OR1K_SPR_AECR_OVMULE    3
`define OR1K_SPR_AECR_DBZE      4
`define OR1K_SPR_AECR_CYMACADDE 5
`define OR1K_SPR_AECR_OVMACADDE 6
`define OR1K_SPR_AECR_RESERVED  31:7
 
// Arithmetic Exception Status register
`define OR1K_SPR_AESR_CYADDE    0
`define OR1K_SPR_AESR_OVADDE    1
`define OR1K_SPR_AESR_CYMULE    2
`define OR1K_SPR_AESR_OVMULE    3
`define OR1K_SPR_AESR_DBZE      4
`define OR1K_SPR_AESR_CYMACADDE 5
`define OR1K_SPR_AESR_OVMACADDE 6
`define OR1K_SPR_AESR_RESERVED  31:7
 
// Tick timer registers
`define OR1K_SPR_TTMR_TP   27:0 /* Time period */
`define OR1K_SPR_TTMR_IP   28   /* Interrupt pending */
`define OR1K_SPR_TTMR_IE   29   /* Interrupt enable */
`define OR1K_SPR_TTMR_M    31:30 /* Mode */
// Tick timer mode values
`define OR1K_SPR_TTMR_M_DIS 2'b00  /* Disabled */
`define OR1K_SPR_TTMR_M_RST 2'b01  /* Restart-on-match mode */
`define OR1K_SPR_TTMR_M_STP 2'b10  /* Stop-on-match mode */
`define OR1K_SPR_TTMR_M_CNT 2'b11  /* Continue counting mode */
 
// Data Cache Configuration register
`define OR1K_SPR_DCCFGR_NCW   2:0 /* Number of Cache Ways */
`define OR1K_SPR_DCCFGR_NCS   6:3 /* Number of Cache Sets */
`define OR1K_SPR_DCCFGR_CBS   7   /* Cache Block Size */
`define OR1K_SPR_DCCFGR_CWS   8   /* Cache Write Strategy */
`define OR1K_SPR_DCCFGR_CCRI  9   /* Cache Control Register Implemented */
`define OR1K_SPR_DCCFGR_CBIRI 10  /* Cache Block Invalidate Register Implemented */
`define OR1K_SPR_DCCFGR_CBPRI 11  /* Cache Block Prefetch Register Implemented */
`define OR1K_SPR_DCCFGR_CBLRI 12  /* Cache Block Lock Register Implemented */
`define OR1K_SPR_DCCFGR_CBFRI 13  /* Cache Block Flush Register Implemented */
`define OR1K_SPR_DCCFGR_CBWBRI 14 /* Cache Block Write-Back Register Implemented */
 
// Instruction Cache Configuration register
`define OR1K_SPR_ICCFGR_NCW   2:0 /* Number of Cache Ways */
`define OR1K_SPR_ICCFGR_NCS   6:3 /* Number of Cache Sets */
`define OR1K_SPR_ICCFGR_CBS   7   /* Cache Block Size */
`define OR1K_SPR_ICCFGR_CCRI  9   /* Cache Control Register Implemented */
`define OR1K_SPR_ICCFGR_CBIRI 10  /* Cache Block Invalidate Register Implemented */
`define OR1K_SPR_ICCFGR_CBPRI 11  /* Cache Block Prefetch Register Implemented */
`define OR1K_SPR_ICCFGR_CBLRI 12  /* Cache Block Lock Register Implemented */
 
// Data MMU Configuration register
`define OR1K_SPR_DMMUFGR_NTW   1:0 /* Number of TLB ways */
`define OR1K_SPR_DMMUFGR_NTS   4:2 /* Number of TLB sets */
`define OR1K_SPR_DMMUFGR_NAE   7:5 /* Number of ATB entries */
`define OR1K_SPR_DMMUFGR_CRI   8   /* Control Register Implemented */
`define OR1K_SPR_DMMUFGR_PRI   9   /* Protection Register Implemented */
`define OR1K_SPR_DMMUFGR_TEIRI 10  /* TLB Entry Invalidate Register Implemented */
`define OR1K_SPR_DMMUFGR_HTR   11  /* Hardware TLB Reload */
 
// Instruction MMU Configuration register
`define OR1K_SPR_IMMUFGR_NTW   1:0 /* Number of TLB ways */
`define OR1K_SPR_IMMUFGR_NTS   4:2 /* Number of TLB sets */
`define OR1K_SPR_IMMUFGR_NAE   7:5 /* Number of ATB entries */
`define OR1K_SPR_IMMUFGR_CRI   8   /* Control Register Implemented */
`define OR1K_SPR_IMMUFGR_PRI   9   /* Protection Register Implemented */
`define OR1K_SPR_IMMUFGR_TEIRI 10  /* TLB Entry Invalidate Register Implemented */
`define OR1K_SPR_IMMUFGR_HTR   11  /* Hardware TLB Reload */
 
// Debug Mode Register 1
`define OR1K_SPR_DMR1_ST 22
`define OR1K_SPR_DMR1_BT 23
 
// Debug Stop Register
`define OR1K_SPR_DSR_RSTE  0
`define OR1K_SPR_DSR_BUSEE 1
`define OR1K_SPR_DSR_DPFE  2
`define OR1K_SPR_DSR_IPFE  3
`define OR1K_SPR_DSR_TTE   4
`define OR1K_SPR_DSR_AE    5
`define OR1K_SPR_DSR_IIE   6
`define OR1K_SPR_DSR_INTE  7
`define OR1K_SPR_DSR_DME   8
`define OR1K_SPR_DSR_IME   9
`define OR1K_SPR_DSR_RE   10
`define OR1K_SPR_DSR_SCE  11
`define OR1K_SPR_DSR_FPE  12
`define OR1K_SPR_DSR_TE   13
 
`define OR1K_SPR_DRR_RSTE  0
`define OR1K_SPR_DRR_BUSEE 1
`define OR1K_SPR_DRR_DPFE  2
`define OR1K_SPR_DRR_IPFE  3
`define OR1K_SPR_DRR_TTE   4
`define OR1K_SPR_DRR_AE    5
`define OR1K_SPR_DRR_IIE   6
`define OR1K_SPR_DRR_IE    7
`define OR1K_SPR_DRR_DME   8
`define OR1K_SPR_DRR_IME   9
`define OR1K_SPR_DRR_RE   10
`define OR1K_SPR_DRR_SCE  11
`define OR1K_SPR_DRR_FPE  12
`define OR1K_SPR_DRR_TE   13
 
// FPCSR bits
`define OR1K_FPCSR_FPEE  0
`define OR1K_FPCSR_RM    2:1
`define OR1K_FPCSR_OVF   3
`define OR1K_FPCSR_UNF   4
`define OR1K_FPCSR_SNF   5
`define OR1K_FPCSR_QNF   6
`define OR1K_FPCSR_ZF    7
`define OR1K_FPCSR_IXF   8
`define OR1K_FPCSR_IVF   9
`define OR1K_FPCSR_INF   10
`define OR1K_FPCSR_DZF   11
// FPCSR sizes of fields
`define OR1K_FPCSR_WIDTH    12 // [11:0]
`define OR1K_FPCSR_RM_SIZE   2
`define OR1K_FPCSR_ALLF_SIZE 9 // [11:3]
// FPCSR flags
`define OR1K_FPCSR_ALLF  `OR1K_FPCSR_DZF:`OR1K_FPCSR_OVF
// FPCSR reset value
`define OR1K_FPCSR_RESET_VALUE `OR1K_FPCSR_WIDTH'd0
// FPCSR extention: maskable FPU flags.
// -vvvv- uncomment the next line to switch the extention on -vvvv-
//`define OR1K_FPCSR_MASK_FLAGS
// bits
`define OR1K_FPCSR_MASK_OVF   12
`define OR1K_FPCSR_MASK_UNF   13
`define OR1K_FPCSR_MASK_SNF   14
`define OR1K_FPCSR_MASK_QNF   15
`define OR1K_FPCSR_MASK_ZF    16
`define OR1K_FPCSR_MASK_IXF   17
`define OR1K_FPCSR_MASK_IVF   18
`define OR1K_FPCSR_MASK_INF   19
`define OR1K_FPCSR_MASK_DZF   20
// bus select
`define OR1K_FPCSR_MASK_ALL  `OR1K_FPCSR_MASK_DZF:`OR1K_FPCSR_MASK_OVF
// reset value.
`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'd0
 
// PCU PCMR bits
`define OR1K_PCMR_CP     0
`define OR1K_PCMR_RSVD_1 1
`define OR1K_PCMR_CISM   2
`define OR1K_PCMR_CIUM   3
`define OR1K_PCMR_LA     4
`define OR1K_PCMR_SA     5
`define OR1K_PCMR_IF     6
`define OR1K_PCMR_DCM    7
`define OR1K_PCMR_ICM    8
`define OR1K_PCMR_IFS    9
`define OR1K_PCMR_LSUS   10
`define OR1K_PCMR_BS     11
`define OR1K_PCMR_DTLBM  12
`define OR1K_PCMR_ITLBM  13
`define OR1K_PCMR_DDS    14
`define OR1K_PCMR_WPE    25:15
`define OR1K_PCMR_RSVD_2 31:26
 
// Implementation-specific SPR defines
`define MOR1KX_SPR_SR_WIDTH 16
`define MOR1KX_SPR_SR_RESET_VALUE `MOR1KX_SPR_SR_WIDTH'h8001

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx-sprs.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`/* ****************************************************************************`
2			`This Source Code Form is subject to the terms of the`
3			`Open Hardware Description License, v. 1.0. If a copy`
4			`of the OHDL was not distributed with this file, You`
5			`can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt`
6
7			`Description: SPR definitions`
8
9			`Copyright (C) 2012 Authors`
10
11			`Author(s): Julius Baxter <juliusbaxter@gmail.com>`
12
13			`***************************************************************************** */`
14			`define SPR_BASE(x) (x/(2**11))
15			`define SPR_OFFSET(x) (x%(2**11))
16
17			`//`
18			`// Addresses`
19			`//`
20			`define OR1K_SPR_SYS_BASE {4'd0}
21			`define OR1K_SPR_VR_ADDR {5'd0,11'd0}
22			`define OR1K_SPR_UPR_ADDR {5'd0,11'd1}
23			`define OR1K_SPR_CPUCFGR_ADDR {5'd0,11'd2}
24			`define OR1K_SPR_DMMUCFGR_ADDR {5'd0,11'd3}
25			`define OR1K_SPR_IMMUCFGR_ADDR {5'd0,11'd4}
26			`define OR1K_SPR_DCCFGR_ADDR {5'd0,11'd5}
27			`define OR1K_SPR_ICCFGR_ADDR {5'd0,11'd6}
28			`define OR1K_SPR_DCFGR_ADDR {5'd0,11'd7}
29			`define OR1K_SPR_PCCFGR_ADDR {5'd0,11'd8}
30			`define OR1K_SPR_VR2_ADDR {5'd0,11'd9}
31			`define OR1K_SPR_AVR_ADDR {5'd0,11'd10}
32			`define OR1K_SPR_EVBAR_ADDR {5'd0,11'd11}
33			`define OR1K_SPR_AECR_ADDR {5'd0,11'd12}
34			`define OR1K_SPR_AESR_ADDR {5'd0,11'd13}
35			`define OR1K_SPR_NPC_ADDR {5'd0,11'd16}
36			`define OR1K_SPR_SR_ADDR {5'd0,11'd17}
37			`define OR1K_SPR_PPC_ADDR {5'd0,11'd18}
38			`define OR1K_SPR_FPCSR_ADDR {5'd0,11'd20}
39			`define OR1K_SPR_ISR0_ADDR {5'd0,11'd21}
40			`define OR1K_SPR_EPCR0_ADDR {5'd0,11'd32}
41			`define OR1K_SPR_EEAR0_ADDR {5'd0,11'd48}
42			`define OR1K_SPR_ESR0_ADDR {5'd0,11'd64}
43			`define OR1K_SPR_COREID_ADDR {5'd0,11'd128}
44			`define OR1K_SPR_NUMCORES_ADDR {5'd0,11'd129}
45			`define OR1K_SPR_GPR0_ADDR {5'd0,11'd1024}
46
47			`define OR1K_SPR_DMMU_BASE {4'd1}
48			`define OR1K_SPR_DMMUCR_ADDR {5'd1,11'd0}
49			`define OR1K_SPR_DMMUPR_ADDR {5'd1,11'd1}
50			`define OR1K_SPR_DTLBEIR_ADDR {5'd1,11'd2}
51			`define OR1K_SPR_DATBMR0_ADDR {5'd1,11'd4}
52			`define OR1K_SPR_DATBTR0_ADDR {5'd1,11'd8}
53			`define OR1K_SPR_DTLBW0MR0_ADDR {5'd1,11'd512}
54			`define OR1K_SPR_DTLBW0TR0_ADDR {5'd1,11'd640}
55			`define OR1K_SPR_DTLBW1MR0_ADDR {5'd1,11'd768}
56			`define OR1K_SPR_DTLBW1TR0_ADDR {5'd1,11'd896}
57			`define OR1K_SPR_DTLBW2MR0_ADDR {5'd1,11'd1024}
58			`define OR1K_SPR_DTLBW2TR0_ADDR {5'd1,11'd1152}
59			`define OR1K_SPR_DTLBW3MR0_ADDR {5'd1,11'd1280}
60			`define OR1K_SPR_DTLBW3TR0_ADDR {5'd1,11'd1408}
61
62			`define OR1K_SPR_IMMU_BASE {4'd2}
63			`define OR1K_SPR_IMMUCR_ADDR {5'd2,11'd0}
64			`define OR1K_SPR_IMMUPR_ADDR {5'd2,11'd1}
65			`define OR1K_SPR_ITLBEIR_ADDR {5'd2,11'd2}
66			`define OR1K_SPR_IATBMR0_ADDR {5'd2,11'd4}
67			`define OR1K_SPR_IATBTR0_ADDR {5'd2,11'd8}
68			`define OR1K_SPR_ITLBW0MR0_ADDR {5'd2,11'd512}
69			`define OR1K_SPR_ITLBW0TR0_ADDR {5'd2,11'd640}
70			`define OR1K_SPR_ITLBW1MR0_ADDR {5'd2,11'd768}
71			`define OR1K_SPR_ITLBW1TR0_ADDR {5'd2,11'd896}
72			`define OR1K_SPR_ITLBW2MR0_ADDR {5'd2,11'd1024}
73			`define OR1K_SPR_ITLBW2TR0_ADDR {5'd2,11'd1152}
74			`define OR1K_SPR_ITLBW3MR0_ADDR {5'd2,11'd1280}
75			`define OR1K_SPR_ITLBW3TR0_ADDR {5'd2,11'd1408}
76
77			`define OR1K_SPR_DC_BASE {4'd3}
78			`define OR1K_SPR_DCCR_ADDR {5'd3,11'd0}
79			`define OR1K_SPR_DCBPR_ADDR {5'd3,11'd1}
80			`define OR1K_SPR_DCBFR_ADDR {5'd3,11'd2}
81			`define OR1K_SPR_DCBIR_ADDR {5'd3,11'd3}
82			`define OR1K_SPR_DCBWR_ADDR {5'd3,11'd4}
83			`define OR1K_SPR_DCBLR_ADDR {5'd3,11'd5}
84
85			`define OR1K_SPR_IC_BASE {4'd4}
86			`define OR1K_SPR_ICCR_ADDR {5'd4,11'd0}
87			`define OR1K_SPR_ICBPR_ADDR {5'd4,11'd1}
88			`define OR1K_SPR_ICBIR_ADDR {5'd4,11'd2}
89			`define OR1K_SPR_ICBLR_ADDR {5'd4,11'd3}
90
91			`define OR1K_SPR_MAC_BASE {4'd5}
92			`define OR1K_SPR_MACLO_ADDR {5'd5,11'd1}
93			`define OR1K_SPR_MACHI_ADDR {5'd5,11'd2}
94
95			`define OR1K_SPR_DU_BASE {4'd6}
96			`define OR1K_SPR_DVR0_ADDR {5'd6,11'd0}
97			`define OR1K_SPR_DCR0_ADDR {5'd6,11'd8}
98			`define OR1K_SPR_DMR1_ADDR {5'd6,11'd16}
99			`define OR1K_SPR_DMR2_ADDR {5'd6,11'd17}
100			`define OR1K_SPR_DCWR0_ADDR {5'd6,11'd18}
101			`define OR1K_SPR_DSR_ADDR {5'd6,11'd20}
102			`define OR1K_SPR_DRR_ADDR {5'd6,11'd21}
103
104			`define OR1K_SPR_PC_BASE {4'd7}
105			`define OR1K_SPR_PCCR0_ADDR {5'd7,11'd0}
106			`define OR1K_SPR_PCCR1_ADDR {5'd7,11'd1}
107			`define OR1K_SPR_PCCR2_ADDR {5'd7,11'd2}
108			`define OR1K_SPR_PCCR3_ADDR {5'd7,11'd3}
109			`define OR1K_SPR_PCCR4_ADDR {5'd7,11'd4}
110			`define OR1K_SPR_PCCR5_ADDR {5'd7,11'd5}
111			`define OR1K_SPR_PCCR6_ADDR {5'd7,11'd6}
112			`define OR1K_SPR_PCCR7_ADDR {5'd7,11'd7}
113			`define OR1K_SPR_PCMR0_ADDR {5'd7,11'd8}
114			`define OR1K_SPR_PCMR1_ADDR {5'd7,11'd9}
115			`define OR1K_SPR_PCMR2_ADDR {5'd7,11'd10}
116			`define OR1K_SPR_PCMR3_ADDR {5'd7,11'd11}
117			`define OR1K_SPR_PCMR4_ADDR {5'd7,11'd12}
118			`define OR1K_SPR_PCMR5_ADDR {5'd7,11'd13}
119			`define OR1K_SPR_PCMR6_ADDR {5'd7,11'd14}
120			`define OR1K_SPR_PCMR7_ADDR {5'd7,11'd15}
121
122			`define OR1K_SPR_PM_BASE {4'd8}
123			`define OR1K_SPR_PMR_ADDR {5'd8,11'd0}
124
125			`define OR1K_SPR_PIC_BASE {4'd9}
126			`define OR1K_SPR_PICMR_ADDR {5'd9,11'd0}
127			`define OR1K_SPR_PICSR_ADDR {5'd9,11'd2}
128
129			`define OR1K_SPR_TT_BASE {4'd10}
130			`define OR1K_SPR_TTMR_ADDR {5'd10,11'd0}
131			`define OR1K_SPR_TTCR_ADDR {5'd10,11'd1}
132
133			`define OR1K_SPR_FPU_BASE {4'd11}
134
135			`//`
136			`// Register bit defines`
137			`//`
138
139			`// Supervision Register`
140			`define OR1K_SPR_SR_SM 0 /* Supervisor mode */
141			`define OR1K_SPR_SR_TEE 1 /* Timer exception enable */
142			`define OR1K_SPR_SR_IEE 2 /* Interrupt exception enable */
143			`define OR1K_SPR_SR_DCE 3 /* Data cache enable */
144			`define OR1K_SPR_SR_ICE 4 /* Instruction cache enable */
145			`define OR1K_SPR_SR_DME 5 /* Data MMU enable */
146			`define OR1K_SPR_SR_IME 6 /* Instruction MMU enable */
147			`define OR1K_SPR_SR_LEE 7 /* Little-endian enable */
148			`define OR1K_SPR_SR_CE 8 /* CID enable */
149			`define OR1K_SPR_SR_F 9 /* Flag */
150			`define OR1K_SPR_SR_CY 10 /* Carry flag */
151			`define OR1K_SPR_SR_OV 11 /* Overflow flag */
152			`define OR1K_SPR_SR_OVE 12 /* Overflow exception enable */
153			`define OR1K_SPR_SR_DSX 13 /* Delay slot exception */
154			`define OR1K_SPR_SR_EPH 14 /* Exception prefix high */
155			`define OR1K_SPR_SR_FO 15 /* Fixed to one */
156			`define OR1K_SPR_SR_SUMRA 16 /* SPR user read mode access */
157			`define OR1K_SPR_SR_RESERVED 27:17 /* Reserved */
158			`define OR1K_SPR_SR_CID 31:28 /* Context ID */
159
160			`// Version register - DEPRECATED`
161			`define OR1K_SPR_VR_REV 5:0 /* Revision */
162			`define OR1K_SPR_VR_UVRP 6 /* Updated Version Registers Present */
163			`define OR1K_SPR_VR_RESERVED 15:7 /* Reserved */
164			`define OR1K_SPR_VR_CFG 23:16 /* Configuration Template */
165			`define OR1K_SPR_VR_VER 31:24 /* Version */
166
167
168			`// Unit Present register`
169			`define OR1K_SPR_UPR_UP 0
170			`define OR1K_SPR_UPR_DCP 1
171			`define OR1K_SPR_UPR_ICP 2
172			`define OR1K_SPR_UPR_DMP 3
173			`define OR1K_SPR_UPR_IMP 4
174			`define OR1K_SPR_UPR_MP 5
175			`define OR1K_SPR_UPR_DUP 6
176			`define OR1K_SPR_UPR_PCUP 7
177			`define OR1K_SPR_UPR_PICP 8
178			`define OR1K_SPR_UPR_PMP 9
179			`define OR1K_SPR_UPR_TTP 10
180			`define OR1K_SPR_UPR_RESERVED 23:11
181			`define OR1K_SPR_UPR_CUP 31:24
182
183			`// CPU Configuration register`
184			`define OR1K_SPR_CPUCFGR_NSGF 3:0 /* Number of shadow GPRs */
185			`define OR1K_SPR_CPUCFGR_CFG 4
186			`define OR1K_SPR_CPUCFGR_OB32S 5
187			`define OR1K_SPR_CPUCFGR_OB64S 6
188			`define OR1K_SPR_CPUCFGR_OF32S 7
189			`define OR1K_SPR_CPUCFGR_OF64S 8
190			`define OR1K_SPR_CPUCFGR_OV64S 9
191			`define OR1K_SPR_CPUCFGR_ND 10 /* No delay-slot implementation */
192			`define OR1K_SPR_CPUCFGR_AVRP 11 /* Arch. version registers */
193			`define OR1K_SPR_CPUCFGR_EVBARP 12 /* Exception vector base addr reg */
194			`define OR1K_SPR_CPUCFGR_ISRP 13 /* Implementation specific regs */
195			`define OR1K_SPR_CPUCFGR_AECSRP 14 /* Arith. exception regs */
196			`define OR1K_SPR_CPUCFGR_RESERVED 31:15
197
198			`// Version register 2 (new with OR1K 1.0)`
199			`define OR1K_SPR_VR2_VER 23:0
200			`define OR1K_SPR_VR2_CPUID 31:24
201
202			`// Architecture Version register`
203			`define OR1K_SPR_AVR_RESERVED 7:0
204			`define OR1K_SPR_AVR_REV 15:8
205			`define OR1K_SPR_AVR_MIN 23:16
206			`define OR1K_SPR_AVR_MAJ 31:24
207
208			`// Exception Vector Base Address register`
209			`define OR1K_SPR_EVBAR_RESERVED 12:0
210			`define OR1K_SPR_EVBAR_EVBA 31:13
211
212			`// Arithmetic Exception Control register`
213			`define OR1K_SPR_AECR_CYADDE 0
214			`define OR1K_SPR_AECR_OVADDE 1
215			`define OR1K_SPR_AECR_CYMULE 2
216			`define OR1K_SPR_AECR_OVMULE 3
217			`define OR1K_SPR_AECR_DBZE 4
218			`define OR1K_SPR_AECR_CYMACADDE 5
219			`define OR1K_SPR_AECR_OVMACADDE 6
220			`define OR1K_SPR_AECR_RESERVED 31:7
221
222			`// Arithmetic Exception Status register`
223			`define OR1K_SPR_AESR_CYADDE 0
224			`define OR1K_SPR_AESR_OVADDE 1
225			`define OR1K_SPR_AESR_CYMULE 2
226			`define OR1K_SPR_AESR_OVMULE 3
227			`define OR1K_SPR_AESR_DBZE 4
228			`define OR1K_SPR_AESR_CYMACADDE 5
229			`define OR1K_SPR_AESR_OVMACADDE 6
230			`define OR1K_SPR_AESR_RESERVED 31:7
231
232			`// Tick timer registers`
233			`define OR1K_SPR_TTMR_TP 27:0 /* Time period */
234			`define OR1K_SPR_TTMR_IP 28 /* Interrupt pending */
235			`define OR1K_SPR_TTMR_IE 29 /* Interrupt enable */
236			`define OR1K_SPR_TTMR_M 31:30 /* Mode */
237			`// Tick timer mode values`
238			`define OR1K_SPR_TTMR_M_DIS 2'b00 /* Disabled */
239			`define OR1K_SPR_TTMR_M_RST 2'b01 /* Restart-on-match mode */
240			`define OR1K_SPR_TTMR_M_STP 2'b10 /* Stop-on-match mode */
241			`define OR1K_SPR_TTMR_M_CNT 2'b11 /* Continue counting mode */
242
243			`// Data Cache Configuration register`
244			`define OR1K_SPR_DCCFGR_NCW 2:0 /* Number of Cache Ways */
245			`define OR1K_SPR_DCCFGR_NCS 6:3 /* Number of Cache Sets */
246			`define OR1K_SPR_DCCFGR_CBS 7 /* Cache Block Size */
247			`define OR1K_SPR_DCCFGR_CWS 8 /* Cache Write Strategy */
248			`define OR1K_SPR_DCCFGR_CCRI 9 /* Cache Control Register Implemented */
249			`define OR1K_SPR_DCCFGR_CBIRI 10 /* Cache Block Invalidate Register Implemented */
250			`define OR1K_SPR_DCCFGR_CBPRI 11 /* Cache Block Prefetch Register Implemented */
251			`define OR1K_SPR_DCCFGR_CBLRI 12 /* Cache Block Lock Register Implemented */
252			`define OR1K_SPR_DCCFGR_CBFRI 13 /* Cache Block Flush Register Implemented */
253			`define OR1K_SPR_DCCFGR_CBWBRI 14 /* Cache Block Write-Back Register Implemented */
254
255			`// Instruction Cache Configuration register`
256			`define OR1K_SPR_ICCFGR_NCW 2:0 /* Number of Cache Ways */
257			`define OR1K_SPR_ICCFGR_NCS 6:3 /* Number of Cache Sets */
258			`define OR1K_SPR_ICCFGR_CBS 7 /* Cache Block Size */
259			`define OR1K_SPR_ICCFGR_CCRI 9 /* Cache Control Register Implemented */
260			`define OR1K_SPR_ICCFGR_CBIRI 10 /* Cache Block Invalidate Register Implemented */
261			`define OR1K_SPR_ICCFGR_CBPRI 11 /* Cache Block Prefetch Register Implemented */
262			`define OR1K_SPR_ICCFGR_CBLRI 12 /* Cache Block Lock Register Implemented */
263
264			`// Data MMU Configuration register`
265			`define OR1K_SPR_DMMUFGR_NTW 1:0 /* Number of TLB ways */
266			`define OR1K_SPR_DMMUFGR_NTS 4:2 /* Number of TLB sets */
267			`define OR1K_SPR_DMMUFGR_NAE 7:5 /* Number of ATB entries */
268			`define OR1K_SPR_DMMUFGR_CRI 8 /* Control Register Implemented */
269			`define OR1K_SPR_DMMUFGR_PRI 9 /* Protection Register Implemented */
270			`define OR1K_SPR_DMMUFGR_TEIRI 10 /* TLB Entry Invalidate Register Implemented */
271			`define OR1K_SPR_DMMUFGR_HTR 11 /* Hardware TLB Reload */
272
273			`// Instruction MMU Configuration register`
274			`define OR1K_SPR_IMMUFGR_NTW 1:0 /* Number of TLB ways */
275			`define OR1K_SPR_IMMUFGR_NTS 4:2 /* Number of TLB sets */
276			`define OR1K_SPR_IMMUFGR_NAE 7:5 /* Number of ATB entries */
277			`define OR1K_SPR_IMMUFGR_CRI 8 /* Control Register Implemented */
278			`define OR1K_SPR_IMMUFGR_PRI 9 /* Protection Register Implemented */
279			`define OR1K_SPR_IMMUFGR_TEIRI 10 /* TLB Entry Invalidate Register Implemented */
280			`define OR1K_SPR_IMMUFGR_HTR 11 /* Hardware TLB Reload */
281
282			`// Debug Mode Register 1`
283			`define OR1K_SPR_DMR1_ST 22
284			`define OR1K_SPR_DMR1_BT 23
285
286			`// Debug Stop Register`
287			`define OR1K_SPR_DSR_RSTE 0
288			`define OR1K_SPR_DSR_BUSEE 1
289			`define OR1K_SPR_DSR_DPFE 2
290			`define OR1K_SPR_DSR_IPFE 3
291			`define OR1K_SPR_DSR_TTE 4
292			`define OR1K_SPR_DSR_AE 5
293			`define OR1K_SPR_DSR_IIE 6
294			`define OR1K_SPR_DSR_INTE 7
295			`define OR1K_SPR_DSR_DME 8
296			`define OR1K_SPR_DSR_IME 9
297			`define OR1K_SPR_DSR_RE 10
298			`define OR1K_SPR_DSR_SCE 11
299			`define OR1K_SPR_DSR_FPE 12
300			`define OR1K_SPR_DSR_TE 13
301
302			`define OR1K_SPR_DRR_RSTE 0
303			`define OR1K_SPR_DRR_BUSEE 1
304			`define OR1K_SPR_DRR_DPFE 2
305			`define OR1K_SPR_DRR_IPFE 3
306			`define OR1K_SPR_DRR_TTE 4
307			`define OR1K_SPR_DRR_AE 5
308			`define OR1K_SPR_DRR_IIE 6
309			`define OR1K_SPR_DRR_IE 7
310			`define OR1K_SPR_DRR_DME 8
311			`define OR1K_SPR_DRR_IME 9
312			`define OR1K_SPR_DRR_RE 10
313			`define OR1K_SPR_DRR_SCE 11
314			`define OR1K_SPR_DRR_FPE 12
315			`define OR1K_SPR_DRR_TE 13
316
317			`// FPCSR bits`
318			`define OR1K_FPCSR_FPEE 0
319			`define OR1K_FPCSR_RM 2:1
320			`define OR1K_FPCSR_OVF 3
321			`define OR1K_FPCSR_UNF 4
322			`define OR1K_FPCSR_SNF 5
323			`define OR1K_FPCSR_QNF 6
324			`define OR1K_FPCSR_ZF 7
325			`define OR1K_FPCSR_IXF 8
326			`define OR1K_FPCSR_IVF 9
327			`define OR1K_FPCSR_INF 10
328			`define OR1K_FPCSR_DZF 11
329			`// FPCSR sizes of fields`
330			`define OR1K_FPCSR_WIDTH 12 // [11:0]
331			`define OR1K_FPCSR_RM_SIZE 2
332			`define OR1K_FPCSR_ALLF_SIZE 9 // [11:3]
333			`// FPCSR flags`
334			`define OR1K_FPCSR_ALLF `OR1K_FPCSR_DZF:`OR1K_FPCSR_OVF
335			`// FPCSR reset value`
336			`define OR1K_FPCSR_RESET_VALUE `OR1K_FPCSR_WIDTH'd0
337			`// FPCSR extention: maskable FPU flags.`
338			`// -vvvv- uncomment the next line to switch the extention on -vvvv-`
339			//`define OR1K_FPCSR_MASK_FLAGS
340			`// bits`
341			`define OR1K_FPCSR_MASK_OVF 12
342			`define OR1K_FPCSR_MASK_UNF 13
343			`define OR1K_FPCSR_MASK_SNF 14
344			`define OR1K_FPCSR_MASK_QNF 15
345			`define OR1K_FPCSR_MASK_ZF 16
346			`define OR1K_FPCSR_MASK_IXF 17
347			`define OR1K_FPCSR_MASK_IVF 18
348			`define OR1K_FPCSR_MASK_INF 19
349			`define OR1K_FPCSR_MASK_DZF 20
350			`// bus select`
351			`define OR1K_FPCSR_MASK_ALL `OR1K_FPCSR_MASK_DZF:`OR1K_FPCSR_MASK_OVF
352			`// reset value.`
353			`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'd0
354
355			`// PCU PCMR bits`
356			`define OR1K_PCMR_CP 0
357			`define OR1K_PCMR_RSVD_1 1
358			`define OR1K_PCMR_CISM 2
359			`define OR1K_PCMR_CIUM 3
360			`define OR1K_PCMR_LA 4
361			`define OR1K_PCMR_SA 5
362			`define OR1K_PCMR_IF 6
363			`define OR1K_PCMR_DCM 7
364			`define OR1K_PCMR_ICM 8
365			`define OR1K_PCMR_IFS 9
366			`define OR1K_PCMR_LSUS 10
367			`define OR1K_PCMR_BS 11
368			`define OR1K_PCMR_DTLBM 12
369			`define OR1K_PCMR_ITLBM 13
370			`define OR1K_PCMR_DDS 14
371			`define OR1K_PCMR_WPE 25:15
372			`define OR1K_PCMR_RSVD_2 31:26
373
374			`// Implementation-specific SPR defines`
375			`define MOR1KX_SPR_SR_WIDTH 16
376			`define MOR1KX_SPR_SR_RESET_VALUE `MOR1KX_SPR_SR_WIDTH'h8001