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/* ****************************************************************************

  This Source Code Form is subject to the terms of the

  Open Hardware Description License, v. 1.0. If a copy

  of the OHDL was not distributed with this file, You

  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt

  Description: mor1kx espresso pipeline control unit

  inputs from execute stage

  generate pipeline controls

  manage SPRs

  issue addresses for exceptions to fetch stage

  control branches going to fetch stage

  contains tick timer

  contains PIC logic

  Copyright (C) 2012 Authors

  Author(s): Julius Baxter <juliusbaxter@gmail.com>

***************************************************************************** */

`include "mor1kx-defines.v"

module mor1kx_ctrl_espresso

  (/*AUTOARG*/

   // Outputs

   flag_o, spr_npc_o, spr_ppc_o, mfspr_dat_o, ctrl_mfspr_we_o,

   carry_o, pipeline_flush_o, padv_fetch_o, padv_decode_o,

   padv_execute_o, fetch_take_exception_branch_o, exception_taken_o,

   execute_waiting_o, stepping_o, du_dat_o, du_ack_o, du_stall_o,

   du_restart_pc_o, du_restart_o, spr_bus_addr_o, spr_bus_we_o,

   spr_bus_stb_o, spr_bus_dat_o, spr_sr_o, ctrl_branch_target_o,

   ctrl_branch_occur_o, rf_we_o,

   // Inputs

   clk, rst, ctrl_alu_result_i, ctrl_rfb_i, ctrl_flag_set_i,

   ctrl_flag_clear_i, ctrl_opc_insn_i, pc_fetch_i, fetch_advancing_i,

   except_ibus_err_i, except_illegal_i, except_syscall_i,

   except_dbus_i, except_trap_i, except_align_i, next_fetch_done_i,

   alu_valid_i, lsu_valid_i, op_lsu_load_i, op_lsu_store_i, op_jr_i,

   op_jbr_i, irq_i, carry_set_i, carry_clear_i, overflow_set_i,

   overflow_clear_i, du_addr_i, du_stb_i, du_dat_i, du_we_i,

   du_stall_i, spr_bus_dat_dc_i, spr_bus_ack_dc_i, spr_bus_dat_ic_i,

   spr_bus_ack_ic_i, spr_bus_dat_dmmu_i, spr_bus_ack_dmmu_i,

   spr_bus_dat_immu_i, spr_bus_ack_immu_i, spr_bus_dat_mac_i,

   spr_bus_ack_mac_i, spr_bus_dat_pmu_i, spr_bus_ack_pmu_i,

   spr_bus_dat_pcu_i, spr_bus_ack_pcu_i, spr_bus_dat_fpu_i,

   spr_bus_ack_fpu_i, multicore_coreid_i, rf_wb_i

   );

   parameter OPTION_OPERAND_WIDTH       = 32;

   parameter OPTION_RESET_PC            = {{(OPTION_OPERAND_WIDTH-13){1'b0}},

                                `OR1K_RESET_VECTOR,8'd0};

   parameter FEATURE_SYSCALL            = "ENABLED";

   parameter FEATURE_TRAP               = "ENABLED";

   parameter FEATURE_RANGE              = "ENABLED";

   parameter FEATURE_DATACACHE          = "NONE";

   parameter OPTION_DCACHE_BLOCK_WIDTH  = 5;

   parameter OPTION_DCACHE_SET_WIDTH    = 9;

   parameter OPTION_DCACHE_WAYS         = 2;

   parameter FEATURE_DMMU               = "NONE";

   parameter FEATURE_INSTRUCTIONCACHE   = "NONE";

   parameter OPTION_ICACHE_BLOCK_WIDTH  = 5;

   parameter OPTION_ICACHE_SET_WIDTH    = 9;

   parameter OPTION_ICACHE_WAYS         = 2;

   parameter FEATURE_IMMU               = "NONE";

   parameter FEATURE_TIMER              = "ENABLED";

   parameter FEATURE_DEBUGUNIT          = "NONE";

   parameter FEATURE_PERFCOUNTERS       = "NONE";

   parameter FEATURE_PMU                = "NONE";

   parameter FEATURE_MAC                = "NONE";

   parameter FEATURE_FPU                = "NONE";

   parameter FEATURE_MULTICORE          = "NONE";

   parameter FEATURE_PIC                = "ENABLED";

   parameter OPTION_PIC_TRIGGER         = "LEVEL";

   parameter OPTION_PIC_NMI_WIDTH       = 0;

   parameter FEATURE_DSX                = "NONE";

   parameter FEATURE_FASTCONTEXTS       = "NONE";

   parameter FEATURE_OVERFLOW           = "NONE";

   parameter SPR_SR_WIDTH               = 16;

   parameter SPR_SR_RESET_VALUE         = 16'h8001;

   input clk, rst;

   // ALU result - either jump target, SPR address

   input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i;

   // Operand B from RF might be jump address, might be value for SPR

   input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i;

   input                            ctrl_flag_set_i, ctrl_flag_clear_i;

   output                           flag_o;

   output [OPTION_OPERAND_WIDTH-1:0] spr_npc_o;

   output [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o;

   input [`OR1K_OPCODE_WIDTH-1:0]   ctrl_opc_insn_i;

   // PC of execute stage (NPC)

   input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_i;

   input                            fetch_advancing_i;

   // Exception inputs, registered on output of execute stage

   input                            except_ibus_err_i,

                                    except_illegal_i,

                                    except_syscall_i, except_dbus_i,

                                    except_trap_i, except_align_i;

   // Inputs from two units that can stall proceedings

   input                            next_fetch_done_i;

   input                            alu_valid_i, lsu_valid_i;

   input                            op_lsu_load_i, op_lsu_store_i;

   input                            op_jr_i, op_jbr_i;

   // External IRQ lines in

   input [31:0]                     irq_i;

   // SPR data out

   output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o;

   // WE to RF for l.mfspr

   output                            ctrl_mfspr_we_o;

   // Flag out to branch control, combinatorial

   reg                               flag;

   // Arithmetic flags to and from ALU

   output                            carry_o;

   input                             carry_set_i;

   input                             carry_clear_i;

   input                             overflow_set_i;

   input                             overflow_clear_i;

   // Branch indicator from control unit (l.rfe/exception)

   wire                              ctrl_branch_exception;

   // PC out to fetch stage for l.rfe, exceptions

   wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc;

   // Clear instructions from decode and fetch stage

   output                            pipeline_flush_o;

   output                            padv_fetch_o;

   output                            padv_decode_o;

   output                            padv_execute_o;

   // This indicates to the fetch unit only that it should basically interrupt

   // whatever it's doing and start fetching the exception

   output                            fetch_take_exception_branch_o;

   // This indicates to other parts of the CPU that we've handled an excption

   // so can be used to clear exception indication registers

   output                            exception_taken_o;

   output                            execute_waiting_o;

   output                            stepping_o;

   // Debug bus

   input [15:0]                      du_addr_i;

   input                             du_stb_i;

   input [OPTION_OPERAND_WIDTH-1:0]  du_dat_i;

   input                             du_we_i;

   output [OPTION_OPERAND_WIDTH-1:0] du_dat_o;

   output                            du_ack_o;

   // Stall control from debug interface

   input                             du_stall_i;

   output                            du_stall_o;

   output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;

   output                            du_restart_o;

   // SPR accesses to external units (cache, mmu, etc.)

   output [15:0]                     spr_bus_addr_o;

   output                            spr_bus_we_o;

   output                            spr_bus_stb_o;

   output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_dc_i;

   input                             spr_bus_ack_dc_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_ic_i;

   input                             spr_bus_ack_ic_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_dmmu_i;

   input                             spr_bus_ack_dmmu_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_immu_i;

   input                             spr_bus_ack_immu_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_mac_i;

   input                             spr_bus_ack_mac_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_pmu_i;

   input                             spr_bus_ack_pmu_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_pcu_i;

   input                             spr_bus_ack_pcu_i;

   input [OPTION_OPERAND_WIDTH-1:0]  spr_bus_dat_fpu_i;

   input                             spr_bus_ack_fpu_i;

   output [15:0]             spr_sr_o;

   // The multicore core identifier

   input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i;

   // Internal signals

   reg [SPR_SR_WIDTH-1:0]            spr_sr;

   reg [SPR_SR_WIDTH-1:0]            spr_esr;

   reg [OPTION_OPERAND_WIDTH-1:0]    spr_epcr;

   reg [OPTION_OPERAND_WIDTH-1:0]    spr_eear;

   // Programmable Interrupt Control SPRs

   wire [31:0]                        spr_picmr;

   wire [31:0]                        spr_picsr;

   // Tick Timer SPRs

   wire [31:0]                       spr_ttmr;

   wire [31:0]                       spr_ttcr;

   reg [OPTION_OPERAND_WIDTH-1:0]    spr_ppc;

   reg [OPTION_OPERAND_WIDTH-1:0]    spr_npc;

   reg                               execute_delay_slot;

   reg                               delay_slot_rf_we_done;

   output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o;

   reg                               execute_go;

   wire                              execute_done;

   reg                               execute_waiting_r;

   reg                               decode_execute_halt;

   reg                               exception_taken;

   reg [OPTION_OPERAND_WIDTH-1:0]    last_branch_insn_pc;

   reg [OPTION_OPERAND_WIDTH-1:0]    last_branch_target_pc;

   reg                               take_exception;

   reg                               exception_r;

   reg [OPTION_OPERAND_WIDTH-1:0]    exception_pc_addr;

   reg                               waiting_for_fetch;

   reg                               branched_and_waiting_for_fetch;

   reg                               doing_rfe_r;

   wire                              doing_rfe;

   wire                              deassert_doing_rfe;

   wire                              exception, exception_pending;

   wire                              execute_stage_exceptions;

   wire                              decode_stage_exceptions;

   wire                              exception_re;

   wire                              except_ticktimer;

   wire                              except_pic;

   wire                              except_ticktimer_nonsrmasked;

   wire                              except_pic_nonsrmasked;

   wire                              except_range;

   wire [15:0]                       spr_addr;

   wire                              op_mtspr;

   wire                              op_mfspr;

   wire                              op_rfe;

   wire [OPTION_OPERAND_WIDTH-1:0]   b;

   wire                              execute_waiting;

   wire                              execute_valid;

   wire                              deassert_decode_execute_halt;

   wire                              ctrl_branch_occur;

   wire                              new_branch;

   output                            ctrl_branch_occur_o;

   output                            rf_we_o;

   input                             rf_wb_i;

   wire                              except_ibus_align;

   wire                              fetch_advance;

   wire                              rfete;

   wire                              stall_on_trap;

   /* Debug SPRs */

   reg [31:0]                        spr_dmr1;

   reg [31:0]                        spr_dmr2;

   reg [31:0]                        spr_dsr;

   reg [31:0]                        spr_drr;

   /* DU internal control signals */

   wire                              du_access;

   wire                              cpu_stall;

   wire                              du_restart_from_stall;

   wire [1:0]                        pstep;

   wire                              stepping;

   wire                              stepped_into_delay_slot;

   wire                              du_npc_write;

   reg                               du_npc_written;

   reg [OPTION_OPERAND_WIDTH-1:0]    du_spr_npc;

   /* Wires for SPR management */

   wire                              spr_group_present;

   wire [3:0]                        spr_group;

   wire                              spr_we;

   wire                              spr_read;

   wire [OPTION_OPERAND_WIDTH-1:0]   spr_write_dat;

   wire [11:0]                       spr_access_ack;

   wire [31:0]                       spr_internal_read_dat [0:12];

   wire                              spr_read_access;

   wire                              spr_write_access;

   wire                              spr_bus_access;

   reg [OPTION_OPERAND_WIDTH-1:0]    spr_sys_group_read;

   /* Wires from mor1kx_cfgrs module */

   wire [31:0]                        spr_vr;

   wire [31:0]                        spr_vr2;

   wire [31:0]                        spr_avr;

   wire [31:0]                        spr_upr;

   wire [31:0]                        spr_cpucfgr;

   wire [31:0]                        spr_dmmucfgr;

   wire [31:0]                        spr_immucfgr;

   wire [31:0]                        spr_dccfgr;

   wire [31:0]                        spr_iccfgr;

   wire [31:0]                        spr_dcfgr;

   wire [31:0]                        spr_pccfgr;

   wire [31:0]                        spr_fpcsr = 0;

   wire [31:0]                        spr_isr [0:7];

   assign b = ctrl_rfb_i;

   assign ctrl_branch_exception = (exception_r | (op_rfe | doing_rfe)) &

                                  !exception_taken;

   assign exception_pending = (except_ibus_err_i | except_ibus_align |

                               except_illegal_i | except_syscall_i |

                               except_dbus_i | except_align_i |

                               except_ticktimer | except_range |

                               except_pic | except_trap_i );

   assign exception = exception_pending;

   assign fetch_take_exception_branch_o =  (take_exception | op_rfe) &

                                           !stepping;

   assign execute_stage_exceptions = except_dbus_i | except_align_i |

                                     except_range;

   assign decode_stage_exceptions = except_trap_i | except_illegal_i;

   assign exception_re = exception & !exception_r & !exception_taken;

   assign deassert_decode_execute_halt = ctrl_branch_occur &

                                         decode_execute_halt;

   assign ctrl_branch_except_pc = (op_rfe | doing_rfe) & !rfete ? spr_epcr :

                                  exception_pc_addr;

   // Exceptions take precedence

   assign ctrl_branch_occur = // instruction is branch, and flag is right

                              (op_jbr_i &

                               // is l.j or l.jal

                               (!(|ctrl_opc_insn_i[2:1]) |

                                // is l.bf/bnf and flag is right

                                (ctrl_opc_insn_i[2]==flag))) |

                              (op_jr_i & !(except_ibus_align));

   assign ctrl_branch_occur_o = // Usual branch signaling

                                ((ctrl_branch_occur | ctrl_branch_exception) &

                                fetch_advance) |

                                // Need to tell the fetch stage to branch

                                // when it gets the next instruction because

                                // there was fetch stalls between the branch

                                // and the delay slot insn

                                (execute_delay_slot);

   assign ctrl_branch_target_o = ctrl_branch_exception ?

                                 ctrl_branch_except_pc :

                                 // jump or branch?

                                 op_jbr_i ? ctrl_alu_result_i :

                                 ctrl_rfb_i;

   // Do writeback when we register our output to the next stage, or if

   // we're doing mfspr

   assign rf_we_o = (execute_done & !delay_slot_rf_we_done) &

                    ((rf_wb_i & !op_mfspr

                      & !((op_lsu_load_i | op_lsu_store_i) &

                          except_dbus_i | except_align_i)) |

                     (op_mfspr));

   assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] &&

                         (spr_sr[`OR1K_SPR_SR_OV] | overflow_set_i &

                          execute_done)  & !doing_rfe : 0;

   // Check for unaligned jump address from register

   assign except_ibus_align = op_jr_i & (|ctrl_rfb_i[1:0]);

   // Return from exception to exception (if pending tick or PIC ints)

   assign rfete = (spr_esr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked) |

                  (spr_esr[`OR1K_SPR_SR_TEE] & except_ticktimer_nonsrmasked);

   always @(posedge clk)

     if (rst)

       exception_pc_addr <= OPTION_RESET_PC;

     else if (exception_re | (rfete & execute_done))

       casez(

             {except_ibus_err_i,

              except_illegal_i,

              except_align_i,

              except_ibus_align,

              except_syscall_i,

              except_trap_i,

              except_dbus_i,

              except_range,

              except_pic_nonsrmasked,

              except_ticktimer_nonsrmasked

              }

             )

         10'b1?????????:

           exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0};

         10'b01????????:

           exception_pc_addr <= {19'd0,`OR1K_ILLEGAL_VECTOR,8'd0};

         10'b001???????,

           10'b0001??????:

             exception_pc_addr <= {19'd0,`OR1K_ALIGN_VECTOR,8'd0};

         10'b00001?????:

           exception_pc_addr <= {19'd0,`OR1K_SYSCALL_VECTOR,8'd0};

         10'b000001????:

           exception_pc_addr <= {19'd0,`OR1K_TRAP_VECTOR,8'd0};

         10'b0000001???:

           exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0};

         10'b00000001??:

           exception_pc_addr <= {19'd0,`OR1K_RANGE_VECTOR,8'd0};

         10'b000000001?:

           exception_pc_addr <= {19'd0,`OR1K_INT_VECTOR,8'd0};

         //10'b0000000001:

         default:

           exception_pc_addr <= {19'd0,`OR1K_TT_VECTOR,8'd0};

       endcase // casex (...

   assign op_mtspr = ctrl_opc_insn_i==`OR1K_OPCODE_MTSPR;

   assign op_mfspr = ctrl_opc_insn_i==`OR1K_OPCODE_MFSPR;

   assign op_rfe = ctrl_opc_insn_i==`OR1K_OPCODE_RFE;

   reg                               waiting_for_except_fetch;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       waiting_for_except_fetch <= 0;

     else if (waiting_for_except_fetch & next_fetch_done_i)

       waiting_for_except_fetch <= 0;

     else if (fetch_take_exception_branch_o)

       waiting_for_except_fetch <= 1;

   assign fetch_advance = (next_fetch_done_i | except_ibus_err_i) &

                          !execute_waiting & !cpu_stall &

                          (!stepping |

                           (stepping & pstep[0] & !next_fetch_done_i));

   assign padv_fetch_o = fetch_advance & !exception_pending & !doing_rfe_r &

                         !cpu_stall;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       take_exception <= 0;

     else

       take_exception <= (exception_pending | exception_r) &

                         (fetch_advance |

                          // Cause exception to always be 'taken' if stepping

                          (stepping & execute_done)

                          ) &

                         // Would like this as only a single pulse

                         !take_exception;

   reg                               padv_decode_r;

   // Some bits of the pipeline (execute_alu for instance) require a falling

   // edge of the decode signal to start work on multi-cycle ops.

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       padv_decode_r <= 0;

     else

       padv_decode_r <= padv_fetch_o;

   assign padv_decode_o = padv_decode_r;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       execute_go <= 0;

     else

       execute_go <= padv_fetch_o | execute_waiting |

                     (stepping & next_fetch_done_i);

   assign execute_done = execute_go & !execute_waiting;

   // ALU or LSU stall execution, nothing else can

   assign execute_valid = !((op_lsu_load_i | op_lsu_store_i) & !lsu_valid_i |

                            !alu_valid_i);

   assign execute_waiting = !execute_valid & !waiting_for_fetch;

   assign execute_waiting_o = execute_waiting;

   assign padv_execute_o = execute_done;

   assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0];

   assign ctrl_mfspr_we_o = op_mfspr & execute_go;

   // Pipeline flush

   assign pipeline_flush_o = (execute_done & op_rfe) |

                             (exception_re) |

                             cpu_stall;

   // Flag

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       flag <= 0;

     else if (execute_done)

       flag <= ctrl_flag_clear_i ? 0 :

               ctrl_flag_set_i ? 1 : flag;

   assign flag_o = flag;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       execute_waiting_r <= 0;

     else if (!execute_waiting)

       execute_waiting_r <= 0;

     else if (execute_waiting)

       execute_waiting_r <= 1;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       decode_execute_halt <= 0;

     else if (du_restart_from_stall)

       decode_execute_halt <= 0;

     else if (decode_execute_halt & deassert_decode_execute_halt)

       decode_execute_halt <= 0;

     else if ((op_rfe | exception) & !decode_execute_halt & !exception_taken)

       decode_execute_halt <= 1;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       exception_r <= 0;

     else if (exception_taken | du_restart_from_stall)

       exception_r <= 0;

     else if (exception & !exception_r)

       exception_r <= 1;

   // Signal to indicate that the incoming exception or l.rfe has been taken

   // and we're waiting for it to propagate through the pipeline.

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       exception_taken <= 0;

     else if (exception_taken)

       exception_taken <= 0;

     else if (exception_r & take_exception)

       exception_taken <= 1;

   assign exception_taken_o = exception_taken;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       last_branch_insn_pc <= 0;

     else if (fetch_advance & ctrl_branch_occur)

       last_branch_insn_pc <= spr_ppc;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       last_branch_target_pc <= 0;

     else if (execute_done & ctrl_branch_occur & stepping)

       last_branch_target_pc <= ctrl_branch_target_o;

   // Used to gate execute stage's advance signal in the case where a LSU op has

   // finished before the next instruction has been fetched. Typically this

   // occurs when not using icache and doing lots of memory accesses.

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       waiting_for_fetch <= 0;

     else if (next_fetch_done_i)

       waiting_for_fetch <= 0;

     else if (!execute_waiting & execute_waiting_r & !next_fetch_done_i)

       waiting_for_fetch <= 1;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       branched_and_waiting_for_fetch <= 0;

     else if (exception_re)

       branched_and_waiting_for_fetch <= 0;

     else if (padv_fetch_o & ctrl_branch_occur_o)

       branched_and_waiting_for_fetch <= 1;

     else if (branched_and_waiting_for_fetch)

       branched_and_waiting_for_fetch <= !next_fetch_done_i;

   assign doing_rfe = ((execute_done & op_rfe) | doing_rfe_r) &

                      !deassert_doing_rfe;

   // Basically, the fetch stage should always take the rfe immediately

   assign deassert_doing_rfe =  doing_rfe_r;

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       doing_rfe_r <= 0;

     else if (deassert_doing_rfe)

       doing_rfe_r <= 0;

     else if (execute_done)

       doing_rfe_r <= op_rfe;

   assign spr_sr_o = spr_sr;

   // Supervision register

   always @(posedge clk `OR_ASYNC_RST)

     if (rst)

       spr_sr <= SPR_SR_RESET_VALUE;

     else if (fetch_take_exception_branch_o)

       begin

          if (op_rfe & !rfete)

            begin

               spr_sr <= spr_esr;

            end

          else

            begin

               // Go into supervisor mode, disable interrupts, MMUs

               spr_sr[`OR1K_SPR_SR_SM  ] <= 1'b1;

               if (FEATURE_TIMER!="NONE")

                 spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0;

               if (FEATURE_PIC!="NONE")

                 spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0;

               if (FEATURE_DMMU!="NONE")

                 spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0;

               if (FEATURE_IMMU!="NONE")

                 spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0;

               if (FEATURE_OVERFLOW!="NONE")

                 spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0;

            end

       end

     else if (execute_done)

       begin

          spr_sr[`OR1K_SPR_SR_F   ] <= ctrl_flag_set_i ? 1 :

                                       ctrl_flag_clear_i ? 0 :

                                       spr_sr[`OR1K_SPR_SR_F   ];

          spr_sr[`OR1K_SPR_SR_CY   ] <= carry_set_i ? 1 :

                                        carry_clear_i ? 0 :

                                        spr_sr[`OR1K_SPR_SR_CY   ];

          if (FEATURE_OVERFLOW!="NONE")

            spr_sr[`OR1K_SPR_SR_OV   ] <= overflow_set_i ? 1 :

                                overflow_clear_i ? 0 :

                                spr_sr[`OR1K_SPR_SR_OV   ];

          if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) &&

              spr_addr==`OR1K_SPR_SR_ADDR)