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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: Register file for cappuccino pipeline
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Handles reading the register file rams and register bypassing.
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_rf_cappuccino
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#(
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parameter FEATURE_FASTCONTEXTS = "NONE",
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parameter OPTION_RF_CLEAR_ON_INIT = 0,
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parameter OPTION_RF_NUM_SHADOW_GPR = 0,
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parameter OPTION_RF_ADDR_WIDTH = 5,
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parameter OPTION_RF_WORDS = 32,
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parameter FEATURE_DEBUGUNIT = "NONE",
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parameter OPTION_OPERAND_WIDTH = 32
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)
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(
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input clk,
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input rst,
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// pipeline control signal in
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input padv_decode_i,
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input padv_execute_i,
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input padv_ctrl_i,
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input decode_valid_i,
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input fetch_rf_adr_valid_i,
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// GPR numbers
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input [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_i,
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input [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_i,
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input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_i,
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input [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_i,
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input [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_i,
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input [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_i,
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input [OPTION_RF_ADDR_WIDTH-1:0] wb_rfd_adr_i,
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// SPR interface
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input [15:0] spr_bus_addr_i,
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input spr_bus_stb_i,
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input spr_bus_we_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
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output spr_gpr_ack_o,
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output [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_o,
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// Write back signal indications
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input execute_rf_wb_i,
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input ctrl_rf_wb_i,
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input wb_rf_wb_i,
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input [OPTION_OPERAND_WIDTH-1:0] result_i,
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input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i,
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input pipeline_flush_i,
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output [OPTION_OPERAND_WIDTH-1:0] decode_rfa_o,
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output [OPTION_OPERAND_WIDTH-1:0] decode_rfb_o,
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output [OPTION_OPERAND_WIDTH-1:0] execute_rfa_o,
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output [OPTION_OPERAND_WIDTH-1:0] execute_rfb_o
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);
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`include "mor1kx_utils.vh"
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localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
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OPTION_RF_NUM_SHADOW_GPR);
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wire [OPTION_OPERAND_WIDTH-1:0] rfa_ram_o;
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wire [OPTION_OPERAND_WIDTH-1:0] rfb_ram_o;
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reg [OPTION_OPERAND_WIDTH-1:0] wb_hazard_result;
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reg [OPTION_OPERAND_WIDTH-1:0] execute_rfa;
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reg [OPTION_OPERAND_WIDTH-1:0] execute_rfb;
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wire [RF_ADDR_WIDTH-1:0] rfa_rdad;
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wire [RF_ADDR_WIDTH-1:0] rfb_rdad;
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wire rfa_rden;
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wire rfb_rden;
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wire rf_wren;
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wire [RF_ADDR_WIDTH-1:0] rf_wradr;
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wire [OPTION_OPERAND_WIDTH-1:0] rf_wrdat;
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reg flushing;
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// Keep track of the flush signal, this is needed to not wrongly assert
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// execute_hazard after an exception (or rfe) has happened.
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// What happens in that case is that the instruction in execute stage is
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// invalid until the next padv_decode, so it's execute_rfd_adr can not be
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// used to evaluate the execute_hazard.
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always @(posedge clk)
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if (pipeline_flush_i)
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flushing <= 1;
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else if (padv_decode_i)
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flushing <= 0;
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// Detect hazards
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reg execute_hazard_a;
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reg execute_hazard_b;
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always @(posedge clk)
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if (pipeline_flush_i) begin
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execute_hazard_a <= 0;
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execute_hazard_b <= 0;
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end else if (padv_decode_i & !flushing) begin
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execute_hazard_a <= execute_rf_wb_i &
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(execute_rfd_adr_i == decode_rfa_adr_i);
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execute_hazard_b <= execute_rf_wb_i &
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(execute_rfd_adr_i == decode_rfb_adr_i);
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end
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reg [OPTION_OPERAND_WIDTH-1:0] execute_hazard_result_r;
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always @(posedge clk)
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if (decode_valid_i)
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execute_hazard_result_r <= ctrl_alu_result_i;
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wire [OPTION_OPERAND_WIDTH-1:0] execute_hazard_result;
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assign execute_hazard_result = decode_valid_i ? ctrl_alu_result_i :
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execute_hazard_result_r;
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reg ctrl_hazard_a;
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reg ctrl_hazard_b;
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always @(posedge clk)
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if (padv_decode_i) begin
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ctrl_hazard_a <= ctrl_rf_wb_i & (ctrl_rfd_adr_i == decode_rfa_adr_i);
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ctrl_hazard_b <= ctrl_rf_wb_i & (ctrl_rfd_adr_i == decode_rfb_adr_i);
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end
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reg [OPTION_OPERAND_WIDTH-1:0] ctrl_hazard_result_r;
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always @(posedge clk)
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if (decode_valid_i)
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ctrl_hazard_result_r <= result_i;
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_hazard_result;
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assign ctrl_hazard_result = decode_valid_i ? result_i : ctrl_hazard_result_r;
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reg wb_hazard_a;
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reg wb_hazard_b;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst) begin
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wb_hazard_a <= 0;
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wb_hazard_b <= 0;
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end else if (padv_decode_i) begin
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wb_hazard_a <= wb_rf_wb_i & (wb_rfd_adr_i == decode_rfa_adr_i);
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wb_hazard_b <= wb_rf_wb_i & (wb_rfd_adr_i == decode_rfb_adr_i);
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end
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always @(posedge clk)
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if (padv_decode_i)
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wb_hazard_result <= result_i;
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// Bypassing to decode stage
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//
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// Since the decode stage doesn't read from the register file, we have to
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// save any writes to the current read addresses in decode stage until
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// fetch latch in new values.
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// When fetch latch in the new values, and a writeback happens at the
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// same time, we bypass that value too.
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// Port A
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reg use_last_wb_a;
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reg wb_to_decode_bypass_a;
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reg [OPTION_OPERAND_WIDTH-1:0] wb_to_decode_result_a;
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always @(posedge clk)
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if (fetch_rf_adr_valid_i) begin
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wb_to_decode_result_a <= result_i;
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wb_to_decode_bypass_a <= wb_rf_wb_i & (wb_rfd_adr_i == fetch_rfa_adr_i);
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use_last_wb_a <= 0;
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end else if (wb_rf_wb_i) begin
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if (decode_rfa_adr_i == wb_rfd_adr_i) begin
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wb_to_decode_result_a <= result_i;
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use_last_wb_a <= 1;
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end
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end
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wire execute_to_decode_bypass_a;
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assign execute_to_decode_bypass_a = ctrl_rf_wb_i &
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(ctrl_rfd_adr_i == decode_rfa_adr_i);
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wire ctrl_to_decode_bypass_a;
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assign ctrl_to_decode_bypass_a = use_last_wb_a | wb_rf_wb_i &
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(wb_rfd_adr_i == decode_rfa_adr_i);
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_to_decode_result_a;
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assign ctrl_to_decode_result_a = use_last_wb_a ?
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wb_to_decode_result_a : result_i;
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// Port B
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reg use_last_wb_b;
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reg wb_to_decode_bypass_b;
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reg [OPTION_OPERAND_WIDTH-1:0] wb_to_decode_result_b;
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always @(posedge clk)
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if (fetch_rf_adr_valid_i) begin
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wb_to_decode_result_b <= result_i;
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wb_to_decode_bypass_b <= wb_rf_wb_i & (wb_rfd_adr_i == fetch_rfb_adr_i);
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use_last_wb_b <= 0;
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end else if (wb_rf_wb_i) begin
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if (decode_rfb_adr_i == wb_rfd_adr_i) begin
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wb_to_decode_result_b <= result_i;
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use_last_wb_b <= 1;
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end
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end
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wire execute_to_decode_bypass_b;
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assign execute_to_decode_bypass_b = ctrl_rf_wb_i &
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(ctrl_rfd_adr_i == decode_rfb_adr_i);
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wire ctrl_to_decode_bypass_b;
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assign ctrl_to_decode_bypass_b = use_last_wb_b | wb_rf_wb_i &
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(wb_rfd_adr_i == decode_rfb_adr_i);
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_to_decode_result_b;
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assign ctrl_to_decode_result_b = use_last_wb_b ?
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wb_to_decode_result_b : result_i;
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assign decode_rfa_o = execute_to_decode_bypass_a ? ctrl_alu_result_i :
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ctrl_to_decode_bypass_a ? ctrl_to_decode_result_a :
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wb_to_decode_bypass_a ? wb_to_decode_result_a :
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rfa_ram_o;
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assign decode_rfb_o = execute_to_decode_bypass_b ? ctrl_alu_result_i :
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ctrl_to_decode_bypass_b ? ctrl_to_decode_result_b :
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wb_to_decode_bypass_b ? wb_to_decode_result_b :
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rfb_ram_o;
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assign execute_rfa_o = execute_hazard_a ? execute_hazard_result :
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ctrl_hazard_a ? ctrl_hazard_result :
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wb_hazard_a ? wb_hazard_result :
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execute_rfa;
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assign execute_rfb_o = execute_hazard_b ? execute_hazard_result :
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ctrl_hazard_b ? ctrl_hazard_result :
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wb_hazard_b ? wb_hazard_result :
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execute_rfb;
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always @(posedge clk)
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if (padv_decode_i) begin
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execute_rfa <= decode_rfa_o;
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execute_rfb <= decode_rfb_o;
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end
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generate
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if (FEATURE_DEBUGUNIT!="NONE" || FEATURE_FASTCONTEXTS!="NONE" ||
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OPTION_RF_NUM_SHADOW_GPR > 0) begin
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wire spr_gpr_we;
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wire spr_gpr_re;
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assign spr_gpr_we = (spr_bus_addr_i[15:9] == 7'h2) &
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spr_bus_stb_i & spr_bus_we_i;
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assign spr_gpr_re = (spr_bus_addr_i[15:9] == 7'h2) &
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spr_bus_stb_i & !spr_bus_we_i & !padv_ctrl_i;
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reg spr_gpr_read_ack;
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always @(posedge clk)
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spr_gpr_read_ack <= spr_gpr_re;
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assign spr_gpr_ack_o = spr_gpr_we & !wb_rf_wb_i |
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spr_gpr_re & spr_gpr_read_ack;
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wire [RF_ADDR_WIDTH-1:0] wb_rfd_adr_expand;
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assign wb_rfd_adr_expand[OPTION_RF_ADDR_WIDTH-1:0] = wb_rfd_adr_i;
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assign rf_wren = wb_rf_wb_i | spr_gpr_we;
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assign rf_wradr = wb_rf_wb_i ? wb_rfd_adr_expand : spr_bus_addr_i[RF_ADDR_WIDTH-1:0];
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assign rf_wrdat = wb_rf_wb_i ? result_i : spr_bus_dat_i;
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// Zero-pad unused parts of vector
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if (OPTION_RF_NUM_SHADOW_GPR > 0) begin
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assign wb_rfd_adr_expand[RF_ADDR_WIDTH-1:OPTION_RF_ADDR_WIDTH] =
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{(RF_ADDR_WIDTH-OPTION_RF_ADDR_WIDTH){1'b0}};
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assign rfa_rdad[RF_ADDR_WIDTH-1:OPTION_RF_ADDR_WIDTH] =
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{(RF_ADDR_WIDTH-OPTION_RF_ADDR_WIDTH){1'b0}};
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assign rfb_rdad[RF_ADDR_WIDTH-1:OPTION_RF_ADDR_WIDTH] =
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{(RF_ADDR_WIDTH-OPTION_RF_ADDR_WIDTH){1'b0}};
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end
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end else begin
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assign spr_gpr_ack_o = 1;
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assign rf_wren = wb_rf_wb_i;
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assign rf_wradr = wb_rfd_adr_i;
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assign rf_wrdat = result_i;
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end
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endgenerate
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assign rfa_rdad[OPTION_RF_ADDR_WIDTH-1:0] = fetch_rfa_adr_i;
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assign rfb_rdad[OPTION_RF_ADDR_WIDTH-1:0] = fetch_rfb_adr_i;
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assign rfa_rden = fetch_rf_adr_valid_i;
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assign rfb_rden = fetch_rf_adr_valid_i;
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mor1kx_simple_dpram_sclk
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#(
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.ADDR_WIDTH (RF_ADDR_WIDTH),
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.DATA_WIDTH (OPTION_OPERAND_WIDTH),
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.CLEAR_ON_INIT (OPTION_RF_CLEAR_ON_INIT),
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.ENABLE_BYPASS (0)
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)
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rfa
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(
|
314 |
|
|
.clk (clk),
|
315 |
|
|
.dout (rfa_ram_o),
|
316 |
|
|
.raddr (rfa_rdad),
|
317 |
|
|
.re (rfa_rden),
|
318 |
|
|
.waddr (rf_wradr),
|
319 |
|
|
.we (rf_wren),
|
320 |
|
|
.din (rf_wrdat)
|
321 |
|
|
);
|
322 |
|
|
|
323 |
|
|
mor1kx_simple_dpram_sclk
|
324 |
|
|
#(
|
325 |
|
|
.ADDR_WIDTH (RF_ADDR_WIDTH),
|
326 |
|
|
.DATA_WIDTH (OPTION_OPERAND_WIDTH),
|
327 |
|
|
.CLEAR_ON_INIT (OPTION_RF_CLEAR_ON_INIT),
|
328 |
|
|
.ENABLE_BYPASS (0)
|
329 |
|
|
)
|
330 |
|
|
rfb
|
331 |
|
|
(
|
332 |
|
|
.clk (clk),
|
333 |
|
|
.dout (rfb_ram_o),
|
334 |
|
|
.raddr (rfb_rdad),
|
335 |
|
|
.re (rfb_rden),
|
336 |
|
|
.waddr (rf_wradr),
|
337 |
|
|
.we (rf_wren),
|
338 |
|
|
.din (rf_wrdat)
|
339 |
|
|
);
|
340 |
|
|
|
341 |
|
|
generate
|
342 |
|
|
if (FEATURE_DEBUGUNIT!="NONE" || FEATURE_FASTCONTEXTS!="NONE" ||
|
343 |
|
|
OPTION_RF_NUM_SHADOW_GPR > 0) begin : rfspr_gen
|
344 |
|
|
mor1kx_simple_dpram_sclk
|
345 |
|
|
#(
|
346 |
|
|
.ADDR_WIDTH (RF_ADDR_WIDTH),
|
347 |
|
|
.DATA_WIDTH (OPTION_OPERAND_WIDTH),
|
348 |
|
|
.CLEAR_ON_INIT (OPTION_RF_CLEAR_ON_INIT),
|
349 |
|
|
.ENABLE_BYPASS (0)
|
350 |
|
|
)
|
351 |
|
|
rfspr
|
352 |
|
|
(
|
353 |
|
|
.clk (clk),
|
354 |
|
|
.dout (spr_gpr_dat_o),
|
355 |
|
|
.raddr (spr_bus_addr_i[RF_ADDR_WIDTH-1:0]),
|
356 |
|
|
.re (1'b1),
|
357 |
|
|
.waddr (rf_wradr),
|
358 |
|
|
.we (rf_wren),
|
359 |
|
|
.din (rf_wrdat)
|
360 |
|
|
);
|
361 |
|
|
end else begin
|
362 |
|
|
assign spr_gpr_dat_o = 0;
|
363 |
|
|
end
|
364 |
|
|
endgenerate
|
365 |
|
|
|
366 |
|
|
endmodule // mor1kx_rf_cappuccino
|