OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [sw/] [or1200/] [or1200-utils.c] - Blame information for rev 38

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 alirezamon
#include "spr-defs.h"
2
#include "or1200-utils.h"
3
#include "board.h" // For timer rate (IN_CLK, TICKS_PER_SEC)
4
 
5
/* For writing into SPR. */
6
void
7
mtspr(unsigned long spr, unsigned long value)
8
{
9
  asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
10
}
11
 
12
/* For reading SPR. */
13
unsigned long
14
mfspr(unsigned long spr)
15
{
16
  unsigned long value;
17
  asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
18
  return value;
19
}
20
 
21
/* Print out a character via simulator */
22
void
23
sim_putc(unsigned char c)
24
{
25
  asm("l.addi\tr3,%0,0": :"r" (c));
26
  asm("l.nop %0": :"K" (NOP_PUTC));
27
}
28
 
29
/* print long */
30
void
31
report(unsigned long value)
32
{
33
  asm("l.addi\tr3,%0,0": :"r" (value));
34
  asm("l.nop %0": :"K" (NOP_REPORT));
35
}
36
 
37
/* Loops/exits simulation */
38
void
39
exit (int i)
40
{
41
  asm("l.add r3,r0,%0": : "r" (i));
42
  asm("l.nop %0": :"K" (NOP_EXIT));
43
  while (1);
44
}
45
 
46
/* Enable user interrupts */
47
void
48
cpu_enable_user_interrupts(void)
49
{
50
  /* Enable interrupts in supervisor register */
51
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
52
}
53
 
54
/* Tick timer variable */
55
unsigned long timer_ticks;
56
 
57
/* Tick timer functions */
58
/* Enable tick timer and interrupt generation */
59
void
60
cpu_enable_timer(void)
61
{
62
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) &
63
                                               SPR_TTMR_TP));
64
  mtspr(SPR_SR, SPR_SR_TEE | mfspr(SPR_SR));
65
 
66
}
67
 
68
/* Disable tick timer and interrupt generation */
69
void
70
cpu_disable_timer(void)
71
{
72
  // Disable timer: clear it all!
73
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_TEE);
74
  mtspr(SPR_TTMR, 0);
75
 
76
}
77
 
78
/* Timer increment - called by interrupt routine */
79
void
80
cpu_timer_tick(void)
81
{
82
  timer_ticks++;
83
  // Reset timer mode register to interrupt with same interval
84
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
85
        ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_TP));
86
}
87
 
88
/* Reset tick counter */
89
void
90
cpu_reset_timer_ticks(void)
91
{
92
  timer_ticks=0;
93
}
94
 
95
/* Get tick counter */
96
unsigned long
97
cpu_get_timer_ticks(void)
98
{
99
  return timer_ticks;
100
}
101
 
102
/* Wait for 10ms, assumes CLK_HZ is 100, which it usually is.
103
   Will be slightly inaccurate!*/
104
void
105
cpu_sleep_10ms(void)
106
{
107
  unsigned long ttcr = mfspr(SPR_TTCR) & SPR_TTCR_CNT;
108
  unsigned long first_time = cpu_get_timer_ticks();
109
  while (first_time == cpu_get_timer_ticks()); // Wait for tick to occur
110
  // Now wait until we're past the tick value we read before to know we've
111
  // gone at least enough
112
  while(ttcr > (mfspr(SPR_TTCR) & SPR_TTCR_CNT));
113
 
114
}
115
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.