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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h 11680 2013-04-17 19:59:56Z sshwarts $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2013 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CPU_H
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# define BX_CPU_H 1
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#include <setjmp.h>
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// <TAG-DEFINES-DECODE-START>
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// segment register encoding
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#define BX_SEG_REG_ES 0
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#define BX_SEG_REG_CS 1
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#define BX_SEG_REG_SS 2
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#define BX_SEG_REG_DS 3
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#define BX_SEG_REG_FS 4
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#define BX_SEG_REG_GS 5
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// NULL now has to fit in 3 bits.
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#define BX_SEG_REG_NULL 7
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#define BX_NULL_SEG_REG(seg) ((seg) == BX_SEG_REG_NULL)
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// <TAG-DEFINES-DECODE-END>
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#define BX_16BIT_REG_AX 0
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#define BX_16BIT_REG_CX 1
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#define BX_16BIT_REG_DX 2
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#define BX_16BIT_REG_BX 3
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#define BX_16BIT_REG_SP 4
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#define BX_16BIT_REG_BP 5
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#define BX_16BIT_REG_SI 6
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#define BX_16BIT_REG_DI 7
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#define BX_32BIT_REG_EAX 0
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#define BX_32BIT_REG_ECX 1
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#define BX_32BIT_REG_EDX 2
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#define BX_32BIT_REG_EBX 3
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#define BX_32BIT_REG_ESP 4
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#define BX_32BIT_REG_EBP 5
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#define BX_32BIT_REG_ESI 6
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#define BX_32BIT_REG_EDI 7
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#define BX_64BIT_REG_RAX 0
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#define BX_64BIT_REG_RCX 1
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#define BX_64BIT_REG_RDX 2
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#define BX_64BIT_REG_RBX 3
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#define BX_64BIT_REG_RSP 4
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#define BX_64BIT_REG_RBP 5
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#define BX_64BIT_REG_RSI 6
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#define BX_64BIT_REG_RDI 7
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#define BX_64BIT_REG_R8 8
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#define BX_64BIT_REG_R9 9
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#define BX_64BIT_REG_R10 10
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#define BX_64BIT_REG_R11 11
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#define BX_64BIT_REG_R12 12
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#define BX_64BIT_REG_R13 13
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#define BX_64BIT_REG_R14 14
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#define BX_64BIT_REG_R15 15
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#if BX_SUPPORT_X86_64
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# define BX_GENERAL_REGISTERS 16
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#else
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# define BX_GENERAL_REGISTERS 8
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#endif
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#define BX_TMP_REGISTER (BX_GENERAL_REGISTERS)
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#define BX_16BIT_REG_IP (BX_GENERAL_REGISTERS+1)
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#define BX_32BIT_REG_EIP (BX_GENERAL_REGISTERS+1)
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#define BX_64BIT_REG_RIP (BX_GENERAL_REGISTERS+1)
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#define BX_NIL_REGISTER (BX_GENERAL_REGISTERS+2)
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#if defined(NEED_CPU_REG_SHORTCUTS)
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/* WARNING:
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Only BX_CPU_C member functions can use these shortcuts safely!
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Functions that use the shortcuts outside of BX_CPU_C might work
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when BX_USE_CPU_SMF=1 but will fail when BX_USE_CPU_SMF=0
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(for example in SMP mode).
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*/
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// access to 8 bit general registers
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#define AL (BX_CPU_THIS_PTR gen_reg[0].word.byte.rl)
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#define CL (BX_CPU_THIS_PTR gen_reg[1].word.byte.rl)
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#define DL (BX_CPU_THIS_PTR gen_reg[2].word.byte.rl)
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#define BL (BX_CPU_THIS_PTR gen_reg[3].word.byte.rl)
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#define AH (BX_CPU_THIS_PTR gen_reg[0].word.byte.rh)
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#define CH (BX_CPU_THIS_PTR gen_reg[1].word.byte.rh)
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#define DH (BX_CPU_THIS_PTR gen_reg[2].word.byte.rh)
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#define BH (BX_CPU_THIS_PTR gen_reg[3].word.byte.rh)
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#define TMP8L (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].word.byte.rl)
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// access to 16 bit general registers
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#define AX (BX_CPU_THIS_PTR gen_reg[0].word.rx)
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#define CX (BX_CPU_THIS_PTR gen_reg[1].word.rx)
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#define DX (BX_CPU_THIS_PTR gen_reg[2].word.rx)
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#define BX (BX_CPU_THIS_PTR gen_reg[3].word.rx)
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#define SP (BX_CPU_THIS_PTR gen_reg[4].word.rx)
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#define BP (BX_CPU_THIS_PTR gen_reg[5].word.rx)
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#define SI (BX_CPU_THIS_PTR gen_reg[6].word.rx)
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#define DI (BX_CPU_THIS_PTR gen_reg[7].word.rx)
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// access to 16 bit instruction pointer
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#define IP (BX_CPU_THIS_PTR gen_reg[BX_16BIT_REG_IP].word.rx)
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#define TMP16 (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].word.rx)
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// accesss to 32 bit general registers
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#define EAX (BX_CPU_THIS_PTR gen_reg[0].dword.erx)
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#define ECX (BX_CPU_THIS_PTR gen_reg[1].dword.erx)
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#define EDX (BX_CPU_THIS_PTR gen_reg[2].dword.erx)
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#define EBX (BX_CPU_THIS_PTR gen_reg[3].dword.erx)
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#define ESP (BX_CPU_THIS_PTR gen_reg[4].dword.erx)
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#define EBP (BX_CPU_THIS_PTR gen_reg[5].dword.erx)
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#define ESI (BX_CPU_THIS_PTR gen_reg[6].dword.erx)
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#define EDI (BX_CPU_THIS_PTR gen_reg[7].dword.erx)
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// access to 32 bit instruction pointer
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#define EIP (BX_CPU_THIS_PTR gen_reg[BX_32BIT_REG_EIP].dword.erx)
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#define TMP32 (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].dword.erx)
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#if BX_SUPPORT_X86_64
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// accesss to 64 bit general registers
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#define RAX (BX_CPU_THIS_PTR gen_reg[0].rrx)
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#define RCX (BX_CPU_THIS_PTR gen_reg[1].rrx)
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#define RDX (BX_CPU_THIS_PTR gen_reg[2].rrx)
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#define RBX (BX_CPU_THIS_PTR gen_reg[3].rrx)
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#define RSP (BX_CPU_THIS_PTR gen_reg[4].rrx)
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#define RBP (BX_CPU_THIS_PTR gen_reg[5].rrx)
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#define RSI (BX_CPU_THIS_PTR gen_reg[6].rrx)
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#define RDI (BX_CPU_THIS_PTR gen_reg[7].rrx)
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#define R8 (BX_CPU_THIS_PTR gen_reg[8].rrx)
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#define R9 (BX_CPU_THIS_PTR gen_reg[9].rrx)
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#define R10 (BX_CPU_THIS_PTR gen_reg[10].rrx)
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#define R11 (BX_CPU_THIS_PTR gen_reg[11].rrx)
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#define R12 (BX_CPU_THIS_PTR gen_reg[12].rrx)
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#define R13 (BX_CPU_THIS_PTR gen_reg[13].rrx)
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#define R14 (BX_CPU_THIS_PTR gen_reg[14].rrx)
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#define R15 (BX_CPU_THIS_PTR gen_reg[15].rrx)
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// access to 64 bit instruction pointer
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#define RIP (BX_CPU_THIS_PTR gen_reg[BX_64BIT_REG_RIP].rrx)
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#define TMP64 (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].rrx)
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// access to 64 bit MSR registers
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#define MSR_FSBASE (BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base)
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#define MSR_GSBASE (BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base)
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#define MSR_LSTAR (BX_CPU_THIS_PTR msr.lstar)
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#define MSR_CSTAR (BX_CPU_THIS_PTR msr.cstar)
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#define MSR_FMASK (BX_CPU_THIS_PTR msr.fmask)
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#define MSR_KERNELGSBASE (BX_CPU_THIS_PTR msr.kernelgsbase)
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#define MSR_TSC_AUX (BX_CPU_THIS_PTR msr.tsc_aux)
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#else // simplify merge between 32-bit and 64-bit mode
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#define RAX EAX
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#define RCX ECX
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#define RDX EDX
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#define RBX EBX
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#define RSP ESP
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#define RBP EBP
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#define RSI ESI
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#define RDI EDI
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#define RIP EIP
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#endif // BX_SUPPORT_X86_64 == 0
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#define PREV_RIP (BX_CPU_THIS_PTR prev_rip)
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#if BX_SUPPORT_X86_64
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#define BX_READ_8BIT_REGx(index,extended) ((((index) & 4) == 0 || (extended)) ? \
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(BX_CPU_THIS_PTR gen_reg[index].word.byte.rl) : \
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(BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh))
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#define BX_READ_64BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].rrx)
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#define BX_READ_64BIT_REG_HIGH(index) (BX_CPU_THIS_PTR gen_reg[index].dword.hrx)
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#else
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#define BX_READ_8BIT_REG(index) (((index) & 4) ? \
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(BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh) : \
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(BX_CPU_THIS_PTR gen_reg[index].word.byte.rl))
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#define BX_READ_8BIT_REGx(index,ext) BX_READ_8BIT_REG(index)
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#endif
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#define BX_READ_8BIT_REGH(index) (BX_CPU_THIS_PTR gen_reg[index].word.byte.rh)
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#define BX_READ_16BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].word.rx)
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#define BX_READ_32BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].dword.erx)
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#define BX_WRITE_8BIT_REGH(index, val) {\
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BX_CPU_THIS_PTR gen_reg[index].word.byte.rh = val; \
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}
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#define BX_WRITE_16BIT_REG(index, val) {\
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BX_CPU_THIS_PTR gen_reg[index].word.rx = val; \
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}
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/*
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#define BX_WRITE_32BIT_REG(index, val) {\
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BX_CPU_THIS_PTR gen_reg[index].dword.erx = val; \
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}
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*/
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#if BX_SUPPORT_X86_64
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#define BX_WRITE_8BIT_REGx(index, extended, val) {\
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if (((index) & 4) == 0 || (extended)) \
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BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \
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else \
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BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \
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}
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#define BX_WRITE_32BIT_REGZ(index, val) {\
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BX_CPU_THIS_PTR gen_reg[index].rrx = (Bit32u) val; \
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}
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#define BX_WRITE_64BIT_REG(index, val) {\
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BX_CPU_THIS_PTR gen_reg[index].rrx = val; \
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}
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#define BX_CLEAR_64BIT_HIGH(index) {\
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BX_CPU_THIS_PTR gen_reg[index].dword.hrx = 0; \
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}
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#else
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#define BX_WRITE_8BIT_REG(index, val) {\
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if ((index) & 4) \
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BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \
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else \
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BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \
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}
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#define BX_WRITE_8BIT_REGx(index, ext, val) BX_WRITE_8BIT_REG(index, val)
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// For x86-32, I just pretend this one is like the macro above,
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// so common code can be used.
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#define BX_WRITE_32BIT_REGZ(index, val) {\
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BX_CPU_THIS_PTR gen_reg[index].dword.erx = (Bit32u) val; \
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}
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#define BX_CLEAR_64BIT_HIGH(index)
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#endif
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#define CPL (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl)
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#define USER_PL (BX_CPU_THIS_PTR user_pl) /* CPL == 3 */
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#if BX_SUPPORT_SMP
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#define BX_CPU_ID (BX_CPU_THIS_PTR bx_cpuid)
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#else
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#define BX_CPU_ID (0)
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#endif
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#endif // defined(NEED_CPU_REG_SHORTCUTS)
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// <TAG-INSTRUMENTATION_COMMON-BEGIN>
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// possible types passed to BX_INSTR_TLB_CNTRL()
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#define BX_INSTR_MOV_CR0 10
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#define BX_INSTR_MOV_CR3 11
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#define BX_INSTR_MOV_CR4 12
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#define BX_INSTR_TASK_SWITCH 13
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#define BX_INSTR_CONTEXT_SWITCH 14
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#define BX_INSTR_INVLPG 15
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#define BX_INSTR_INVEPT 16
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#define BX_INSTR_INVVPID 17
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#define BX_INSTR_INVPCID 18
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// possible types passed to BX_INSTR_CACHE_CNTRL()
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#define BX_INSTR_INVD 10
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#define BX_INSTR_WBINVD 11
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// possible types passed to BX_INSTR_FAR_BRANCH() and BX_INSTR_UCNEAR_BRANCH()
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#define BX_INSTR_IS_JMP 10
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#define BX_INSTR_IS_JMP_INDIRECT 11
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#define BX_INSTR_IS_CALL 12
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#define BX_INSTR_IS_CALL_INDIRECT 13
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#define BX_INSTR_IS_RET 14
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#define BX_INSTR_IS_IRET 15
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#define BX_INSTR_IS_INT 16
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#define BX_INSTR_IS_SYSCALL 17
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|
|
#define BX_INSTR_IS_SYSRET 18
|
301 |
|
|
#define BX_INSTR_IS_SYSENTER 19
|
302 |
|
|
#define BX_INSTR_IS_SYSEXIT 20
|
303 |
|
|
|
304 |
|
|
// possible types passed to BX_INSTR_PREFETCH_HINT()
|
305 |
|
|
#define BX_INSTR_PREFETCH_NTA 0
|
306 |
|
|
#define BX_INSTR_PREFETCH_T0 1
|
307 |
|
|
#define BX_INSTR_PREFETCH_T1 2
|
308 |
|
|
#define BX_INSTR_PREFETCH_T2 3
|
309 |
|
|
|
310 |
|
|
// <TAG-INSTRUMENTATION_COMMON-END>
|
311 |
|
|
|
312 |
|
|
// passed to internal debugger together with BX_READ/BX_WRITE/BX_EXECUTE/BX_RW
|
313 |
|
|
enum {
|
314 |
|
|
BX_PDPTR0_ACCESS = 1,
|
315 |
|
|
BX_PDPTR1_ACCESS,
|
316 |
|
|
BX_PDPTR2_ACCESS,
|
317 |
|
|
BX_PDPTR3_ACCESS,
|
318 |
|
|
BX_PTE_ACCESS,
|
319 |
|
|
BX_PDE_ACCESS,
|
320 |
|
|
BX_PDTE_ACCESS,
|
321 |
|
|
BX_PML4E_ACCESS,
|
322 |
|
|
BX_EPT_PTE_ACCESS,
|
323 |
|
|
BX_EPT_PDE_ACCESS,
|
324 |
|
|
BX_EPT_PDTE_ACCESS,
|
325 |
|
|
BX_EPT_PML4E_ACCESS,
|
326 |
|
|
BX_VMCS_ACCESS,
|
327 |
|
|
BX_SHADOW_VMCS_ACCESS,
|
328 |
|
|
BX_MSR_BITMAP_ACCESS,
|
329 |
|
|
BX_IO_BITMAP_ACCESS,
|
330 |
|
|
BX_VMREAD_BITMAP_ACCESS,
|
331 |
|
|
BX_VMWRITE_BITMAP_ACCESS,
|
332 |
|
|
BX_VMX_LOAD_MSR_ACCESS,
|
333 |
|
|
BX_VMX_STORE_MSR_ACCESS,
|
334 |
|
|
BX_VMX_VAPIC_ACCESS,
|
335 |
|
|
BX_SMRAM_ACCESS
|
336 |
|
|
};
|
337 |
|
|
|
338 |
|
|
struct BxExceptionInfo {
|
339 |
|
|
unsigned exception_type;
|
340 |
|
|
unsigned exception_class;
|
341 |
|
|
bx_bool push_error;
|
342 |
|
|
};
|
343 |
|
|
|
344 |
|
|
#define BX_DE_EXCEPTION 0 // Divide Error (fault)
|
345 |
|
|
#define BX_DB_EXCEPTION 1 // Debug (fault/trap)
|
346 |
|
|
#define BX_BP_EXCEPTION 3 // Breakpoint (trap)
|
347 |
|
|
#define BX_OF_EXCEPTION 4 // Overflow (trap)
|
348 |
|
|
#define BX_BR_EXCEPTION 5 // BOUND (fault)
|
349 |
|
|
#define BX_UD_EXCEPTION 6
|
350 |
|
|
#define BX_NM_EXCEPTION 7
|
351 |
|
|
#define BX_DF_EXCEPTION 8
|
352 |
|
|
#define BX_TS_EXCEPTION 10
|
353 |
|
|
#define BX_NP_EXCEPTION 11
|
354 |
|
|
#define BX_SS_EXCEPTION 12
|
355 |
|
|
#define BX_GP_EXCEPTION 13
|
356 |
|
|
#define BX_PF_EXCEPTION 14
|
357 |
|
|
#define BX_MF_EXCEPTION 16
|
358 |
|
|
#define BX_AC_EXCEPTION 17
|
359 |
|
|
#define BX_MC_EXCEPTION 18
|
360 |
|
|
#define BX_XM_EXCEPTION 19
|
361 |
|
|
#define BX_VE_EXCEPTION 20
|
362 |
|
|
|
363 |
|
|
#define BX_CPU_HANDLED_EXCEPTIONS 32
|
364 |
|
|
|
365 |
|
|
/* MSR registers */
|
366 |
|
|
#define BX_MSR_TSC 0x010
|
367 |
|
|
#define BX_MSR_APICBASE 0x01b
|
368 |
|
|
|
369 |
|
|
#if BX_CPU_LEVEL >= 6
|
370 |
|
|
#define BX_MSR_SYSENTER_CS 0x174
|
371 |
|
|
#define BX_MSR_SYSENTER_ESP 0x175
|
372 |
|
|
#define BX_MSR_SYSENTER_EIP 0x176
|
373 |
|
|
#endif
|
374 |
|
|
|
375 |
|
|
#define BX_MSR_DEBUGCTLMSR 0x1d9
|
376 |
|
|
#define BX_MSR_LASTBRANCHFROMIP 0x1db
|
377 |
|
|
#define BX_MSR_LASTBRANCHTOIP 0x1dc
|
378 |
|
|
#define BX_MSR_LASTINTOIP 0x1dd
|
379 |
|
|
|
380 |
|
|
#if BX_CPU_LEVEL >= 6
|
381 |
|
|
#define BX_MSR_MTRRCAP 0x0fe
|
382 |
|
|
#define BX_MSR_MTRRPHYSBASE0 0x200
|
383 |
|
|
#define BX_MSR_MTRRPHYSMASK0 0x201
|
384 |
|
|
#define BX_MSR_MTRRPHYSBASE1 0x202
|
385 |
|
|
#define BX_MSR_MTRRPHYSMASK1 0x203
|
386 |
|
|
#define BX_MSR_MTRRPHYSBASE2 0x204
|
387 |
|
|
#define BX_MSR_MTRRPHYSMASK2 0x205
|
388 |
|
|
#define BX_MSR_MTRRPHYSBASE3 0x206
|
389 |
|
|
#define BX_MSR_MTRRPHYSMASK3 0x207
|
390 |
|
|
#define BX_MSR_MTRRPHYSBASE4 0x208
|
391 |
|
|
#define BX_MSR_MTRRPHYSMASK4 0x209
|
392 |
|
|
#define BX_MSR_MTRRPHYSBASE5 0x20a
|
393 |
|
|
#define BX_MSR_MTRRPHYSMASK5 0x20b
|
394 |
|
|
#define BX_MSR_MTRRPHYSBASE6 0x20c
|
395 |
|
|
#define BX_MSR_MTRRPHYSMASK6 0x20d
|
396 |
|
|
#define BX_MSR_MTRRPHYSBASE7 0x20e
|
397 |
|
|
#define BX_MSR_MTRRPHYSMASK7 0x20f
|
398 |
|
|
#define BX_MSR_MTRRFIX64K_00000 0x250
|
399 |
|
|
#define BX_MSR_MTRRFIX16K_80000 0x258
|
400 |
|
|
#define BX_MSR_MTRRFIX16K_A0000 0x259
|
401 |
|
|
#define BX_MSR_MTRRFIX4K_C0000 0x268
|
402 |
|
|
#define BX_MSR_MTRRFIX4K_C8000 0x269
|
403 |
|
|
#define BX_MSR_MTRRFIX4K_D0000 0x26a
|
404 |
|
|
#define BX_MSR_MTRRFIX4K_D8000 0x26b
|
405 |
|
|
#define BX_MSR_MTRRFIX4K_E0000 0x26c
|
406 |
|
|
#define BX_MSR_MTRRFIX4K_E8000 0x26d
|
407 |
|
|
#define BX_MSR_MTRRFIX4K_F0000 0x26e
|
408 |
|
|
#define BX_MSR_MTRRFIX4K_F8000 0x26f
|
409 |
|
|
#define BX_MSR_PAT 0x277
|
410 |
|
|
#define BX_MSR_MTRR_DEFTYPE 0x2ff
|
411 |
|
|
#endif
|
412 |
|
|
|
413 |
|
|
#define BX_MSR_TSC_DEADLINE 0x6E0
|
414 |
|
|
|
415 |
|
|
#define BX_MSR_MAX_INDEX 0x1000
|
416 |
|
|
|
417 |
|
|
enum {
|
418 |
|
|
BX_MEMTYPE_UC = 0,
|
419 |
|
|
BX_MEMTYPE_WC,
|
420 |
|
|
BX_MEMTYPE_RESERVED2,
|
421 |
|
|
BX_MEMTYPE_RESERVED3,
|
422 |
|
|
BX_MEMTYPE_WT,
|
423 |
|
|
BX_MEMTYPE_WP,
|
424 |
|
|
BX_MEMTYPE_WB
|
425 |
|
|
};
|
426 |
|
|
|
427 |
|
|
#if BX_SUPPORT_VMX
|
428 |
|
|
#define BX_MSR_VMX_BASIC 0x480
|
429 |
|
|
#define BX_MSR_VMX_PINBASED_CTRLS 0x481
|
430 |
|
|
#define BX_MSR_VMX_PROCBASED_CTRLS 0x482
|
431 |
|
|
#define BX_MSR_VMX_VMEXIT_CTRLS 0x483
|
432 |
|
|
#define BX_MSR_VMX_VMENTRY_CTRLS 0x484
|
433 |
|
|
#define BX_MSR_VMX_MISC 0x485
|
434 |
|
|
#define BX_MSR_VMX_CR0_FIXED0 0x486
|
435 |
|
|
#define BX_MSR_VMX_CR0_FIXED1 0x487
|
436 |
|
|
#define BX_MSR_VMX_CR4_FIXED0 0x488
|
437 |
|
|
#define BX_MSR_VMX_CR4_FIXED1 0x489
|
438 |
|
|
#define BX_MSR_VMX_VMCS_ENUM 0x48a
|
439 |
|
|
#define BX_MSR_VMX_PROCBASED_CTRLS2 0x48b
|
440 |
|
|
#define BX_MSR_VMX_EPT_VPID_CAP 0x48c
|
441 |
|
|
#define BX_MSR_VMX_TRUE_PINBASED_CTRLS 0x48d
|
442 |
|
|
#define BX_MSR_VMX_TRUE_PROCBASED_CTRLS 0x48e
|
443 |
|
|
#define BX_MSR_VMX_TRUE_VMEXIT_CTRLS 0x48f
|
444 |
|
|
#define BX_MSR_VMX_TRUE_VMENTRY_CTRLS 0x490
|
445 |
|
|
#define BX_MSR_VMX_VMFUNC 0x491
|
446 |
|
|
#define BX_MSR_IA32_FEATURE_CONTROL 0x03A
|
447 |
|
|
#define BX_MSR_IA32_SMM_MONITOR_CTL 0x09B
|
448 |
|
|
#endif
|
449 |
|
|
|
450 |
|
|
#define BX_MSR_EFER 0xc0000080
|
451 |
|
|
#define BX_MSR_STAR 0xc0000081
|
452 |
|
|
#define BX_MSR_LSTAR 0xc0000082
|
453 |
|
|
#define BX_MSR_CSTAR 0xc0000083
|
454 |
|
|
#define BX_MSR_FMASK 0xc0000084
|
455 |
|
|
#define BX_MSR_FSBASE 0xc0000100
|
456 |
|
|
#define BX_MSR_GSBASE 0xc0000101
|
457 |
|
|
#define BX_MSR_KERNELGSBASE 0xc0000102
|
458 |
|
|
#define BX_MSR_TSC_AUX 0xc0000103
|
459 |
|
|
|
460 |
|
|
#define BX_SVM_VM_CR_MSR 0xc0010114
|
461 |
|
|
#define BX_SVM_IGNNE_MSR 0xc0010115
|
462 |
|
|
#define BX_SVM_SMM_CTL_MSR 0xc0010116
|
463 |
|
|
#define BX_SVM_HSAVE_PA_MSR 0xc0010117
|
464 |
|
|
|
465 |
|
|
#define BX_MODE_IA32_REAL 0x0 // CR0.PE=0 |
|
466 |
|
|
#define BX_MODE_IA32_V8086 0x1 // CR0.PE=1, EFLAGS.VM=1 | EFER.LMA=0
|
467 |
|
|
#define BX_MODE_IA32_PROTECTED 0x2 // CR0.PE=1, EFLAGS.VM=0 |
|
468 |
|
|
#define BX_MODE_LONG_COMPAT 0x3 // EFER.LMA = 1, CR0.PE=1, CS.L=0
|
469 |
|
|
#define BX_MODE_LONG_64 0x4 // EFER.LMA = 1, CR0.PE=1, CS.L=1
|
470 |
|
|
|
471 |
|
|
extern const char* cpu_mode_string(unsigned cpu_mode);
|
472 |
|
|
|
473 |
|
|
#if BX_SUPPORT_X86_64
|
474 |
|
|
#define IsCanonical(offset) ((Bit64u)((((Bit64s)(offset)) >> (BX_LIN_ADDRESS_WIDTH-1)) + 1) < 2)
|
475 |
|
|
#endif
|
476 |
|
|
|
477 |
|
|
#define IsValidPhyAddr(addr) (((addr) & BX_PHY_ADDRESS_RESERVED_BITS) == 0)
|
478 |
|
|
|
479 |
|
|
#define IsValidPageAlignedPhyAddr(addr) (((addr) & (BX_PHY_ADDRESS_RESERVED_BITS | 0xfff)) == 0)
|
480 |
|
|
|
481 |
|
|
#define CACHE_LINE_SIZE 64
|
482 |
|
|
|
483 |
|
|
class BX_CPU_C;
|
484 |
|
|
class BX_MEM_C;
|
485 |
|
|
|
486 |
|
|
#if BX_USE_CPU_SMF == 0
|
487 |
|
|
// normal member functions. This can ONLY be used within BX_CPU_C classes.
|
488 |
|
|
// Anyone on the outside should use the BX_CPU macro (defined in bochs.h)
|
489 |
|
|
// instead.
|
490 |
|
|
# define BX_CPU_THIS_PTR this->
|
491 |
|
|
# define BX_CPU_THIS this
|
492 |
|
|
# define BX_SMF
|
493 |
|
|
// with normal member functions, calling a member fn pointer looks like
|
494 |
|
|
// object->*(fnptr)(arg, ...);
|
495 |
|
|
// Since this is different from when SMF=1, encapsulate it in a macro.
|
496 |
|
|
# define BX_CPU_CALL_METHOD(func, args) \
|
497 |
|
|
(this->*((BxExecutePtr_tR) (func))) args
|
498 |
|
|
# define BX_CPU_CALL_METHODR(func, args) \
|
499 |
|
|
(this->*((BxResolvePtr_tR) (func))) args
|
500 |
|
|
# define BX_CPU_CALL_REP_ITERATION(func, args) \
|
501 |
|
|
(this->*((BxRepIterationPtr_tR) (func))) args
|
502 |
|
|
#else
|
503 |
|
|
// static member functions. With SMF, there is only one CPU by definition.
|
504 |
|
|
# define BX_CPU_THIS_PTR BX_CPU(0)->
|
505 |
|
|
# define BX_CPU_THIS BX_CPU(0)
|
506 |
|
|
# define BX_SMF static
|
507 |
|
|
# define BX_CPU_CALL_METHOD(func, args) \
|
508 |
|
|
((BxExecutePtr_tR) (func)) args
|
509 |
|
|
# define BX_CPU_CALL_METHODR(func, args) \
|
510 |
|
|
((BxResolvePtr_tR) (func)) args
|
511 |
|
|
# define BX_CPU_CALL_REP_ITERATION(func, args) \
|
512 |
|
|
((BxRepIterationPtr_tR) (func)) args
|
513 |
|
|
#endif
|
514 |
|
|
|
515 |
|
|
#if BX_SUPPORT_SMP
|
516 |
|
|
// multiprocessor simulation, we need an array of cpus and memories
|
517 |
|
|
BOCHSAPI extern BX_CPU_C **bx_cpu_array;
|
518 |
|
|
#else
|
519 |
|
|
// single processor simulation, so there's one of everything
|
520 |
|
|
BOCHSAPI extern BX_CPU_C bx_cpu;
|
521 |
|
|
#endif
|
522 |
|
|
|
523 |
|
|
// notify internal debugger/instrumentation about memory access
|
524 |
|
|
#define BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, paddr, size, pl, rw, dataptr) { \
|
525 |
|
|
BX_INSTR_LIN_ACCESS(BX_CPU_ID, (laddr), (paddr), (size), (rw)); \
|
526 |
|
|
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, (laddr), (paddr), (size), (pl), (rw), (dataptr)); \
|
527 |
|
|
}
|
528 |
|
|
|
529 |
|
|
#define BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, size, rw, why, dataptr) { \
|
530 |
|
|
BX_INSTR_PHY_ACCESS(BX_CPU_ID, (paddr), (size), (rw)); \
|
531 |
|
|
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, (paddr), (size), (rw), (why), (dataptr)); \
|
532 |
|
|
}
|
533 |
|
|
|
534 |
|
|
// accessors for all eflags in bx_flags_reg_t
|
535 |
|
|
// The macro is used once for each flag bit
|
536 |
|
|
// Do not use for arithmetic flags !
|
537 |
|
|
#define DECLARE_EFLAG_ACCESSOR(name,bitnum) \
|
538 |
|
|
BX_SMF BX_CPP_INLINE Bit32u get_##name (); \
|
539 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_##name (); \
|
540 |
|
|
BX_SMF BX_CPP_INLINE void assert_##name (); \
|
541 |
|
|
BX_SMF BX_CPP_INLINE void clear_##name (); \
|
542 |
|
|
BX_SMF BX_CPP_INLINE void set_##name (bx_bool val);
|
543 |
|
|
|
544 |
|
|
#define IMPLEMENT_EFLAG_ACCESSOR(name,bitnum) \
|
545 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::getB_##name () { \
|
546 |
|
|
return 1 & (BX_CPU_THIS_PTR eflags >> bitnum); \
|
547 |
|
|
} \
|
548 |
|
|
BX_CPP_INLINE Bit32u BX_CPU_C::get_##name () { \
|
549 |
|
|
return BX_CPU_THIS_PTR eflags & (1 << bitnum); \
|
550 |
|
|
}
|
551 |
|
|
|
552 |
|
|
#define IMPLEMENT_EFLAG_SET_ACCESSOR(name,bitnum) \
|
553 |
|
|
BX_CPP_INLINE void BX_CPU_C::assert_##name () { \
|
554 |
|
|
BX_CPU_THIS_PTR eflags |= (1<<bitnum); \
|
555 |
|
|
} \
|
556 |
|
|
BX_CPP_INLINE void BX_CPU_C::clear_##name () { \
|
557 |
|
|
BX_CPU_THIS_PTR eflags &= ~(1<<bitnum); \
|
558 |
|
|
} \
|
559 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_##name (bx_bool val) { \
|
560 |
|
|
BX_CPU_THIS_PTR eflags = \
|
561 |
|
|
(BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum); \
|
562 |
|
|
}
|
563 |
|
|
|
564 |
|
|
#if BX_CPU_LEVEL >= 4
|
565 |
|
|
|
566 |
|
|
#define IMPLEMENT_EFLAG_SET_ACCESSOR_AC(bitnum) \
|
567 |
|
|
BX_CPP_INLINE void BX_CPU_C::assert_AC() { \
|
568 |
|
|
BX_CPU_THIS_PTR eflags |= (1<<bitnum); \
|
569 |
|
|
handleAlignmentCheck(); \
|
570 |
|
|
} \
|
571 |
|
|
BX_CPP_INLINE void BX_CPU_C::clear_AC() { \
|
572 |
|
|
BX_CPU_THIS_PTR eflags &= ~(1<<bitnum); \
|
573 |
|
|
handleAlignmentCheck(); \
|
574 |
|
|
} \
|
575 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_AC(bx_bool val) { \
|
576 |
|
|
BX_CPU_THIS_PTR eflags = \
|
577 |
|
|
(BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum); \
|
578 |
|
|
handleAlignmentCheck(); \
|
579 |
|
|
}
|
580 |
|
|
|
581 |
|
|
#endif
|
582 |
|
|
|
583 |
|
|
#define IMPLEMENT_EFLAG_SET_ACCESSOR_VM(bitnum) \
|
584 |
|
|
BX_CPP_INLINE void BX_CPU_C::assert_VM() { \
|
585 |
|
|
set_VM(1); \
|
586 |
|
|
} \
|
587 |
|
|
BX_CPP_INLINE void BX_CPU_C::clear_VM() { \
|
588 |
|
|
set_VM(0); \
|
589 |
|
|
} \
|
590 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_VM(bx_bool val) { \
|
591 |
|
|
if (!long_mode()) { \
|
592 |
|
|
BX_CPU_THIS_PTR eflags = \
|
593 |
|
|
(BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum); \
|
594 |
|
|
handleCpuModeChange(); \
|
595 |
|
|
} \
|
596 |
|
|
}
|
597 |
|
|
|
598 |
|
|
// need special handling when IF is set
|
599 |
|
|
#define IMPLEMENT_EFLAG_SET_ACCESSOR_IF(bitnum) \
|
600 |
|
|
BX_CPP_INLINE void BX_CPU_C::assert_IF() { \
|
601 |
|
|
BX_CPU_THIS_PTR eflags |= (1<<bitnum); \
|
602 |
|
|
handleInterruptMaskChange(); \
|
603 |
|
|
} \
|
604 |
|
|
BX_CPP_INLINE void BX_CPU_C::clear_IF() { \
|
605 |
|
|
BX_CPU_THIS_PTR eflags &= ~(1<<bitnum); \
|
606 |
|
|
handleInterruptMaskChange(); \
|
607 |
|
|
} \
|
608 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_IF(bx_bool val) { \
|
609 |
|
|
if (val) assert_IF(); \
|
610 |
|
|
else clear_IF(); \
|
611 |
|
|
}
|
612 |
|
|
|
613 |
|
|
// assert async_event when TF is set
|
614 |
|
|
#define IMPLEMENT_EFLAG_SET_ACCESSOR_TF(bitnum) \
|
615 |
|
|
BX_CPP_INLINE void BX_CPU_C::assert_TF() { \
|
616 |
|
|
BX_CPU_THIS_PTR async_event = 1; \
|
617 |
|
|
BX_CPU_THIS_PTR eflags |= (1<<bitnum); \
|
618 |
|
|
} \
|
619 |
|
|
BX_CPP_INLINE void BX_CPU_C::clear_TF() { \
|
620 |
|
|
BX_CPU_THIS_PTR eflags &= ~(1<<bitnum); \
|
621 |
|
|
} \
|
622 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_TF(bx_bool val) { \
|
623 |
|
|
if (val) BX_CPU_THIS_PTR async_event = 1; \
|
624 |
|
|
BX_CPU_THIS_PTR eflags = \
|
625 |
|
|
(BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum); \
|
626 |
|
|
}
|
627 |
|
|
|
628 |
|
|
// invalidate prefetch queue and call prefetch() when RF is set
|
629 |
|
|
#define IMPLEMENT_EFLAG_SET_ACCESSOR_RF(bitnum) \
|
630 |
|
|
BX_CPP_INLINE void BX_CPU_C::assert_RF() { \
|
631 |
|
|
invalidate_prefetch_q(); \
|
632 |
|
|
BX_CPU_THIS_PTR eflags |= (1<<bitnum); \
|
633 |
|
|
} \
|
634 |
|
|
BX_CPP_INLINE void BX_CPU_C::clear_RF() { \
|
635 |
|
|
BX_CPU_THIS_PTR eflags &= ~(1<<bitnum); \
|
636 |
|
|
} \
|
637 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_RF(bx_bool val) { \
|
638 |
|
|
if (val) invalidate_prefetch_q(); \
|
639 |
|
|
BX_CPU_THIS_PTR eflags = \
|
640 |
|
|
(BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum); \
|
641 |
|
|
}
|
642 |
|
|
|
643 |
|
|
#define DECLARE_EFLAG_ACCESSOR_IOPL(bitnum) \
|
644 |
|
|
BX_SMF BX_CPP_INLINE void set_IOPL(Bit32u val); \
|
645 |
|
|
BX_SMF BX_CPP_INLINE Bit32u get_IOPL(void);
|
646 |
|
|
|
647 |
|
|
#define IMPLEMENT_EFLAG_ACCESSOR_IOPL(bitnum) \
|
648 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_IOPL(Bit32u val) { \
|
649 |
|
|
BX_CPU_THIS_PTR eflags &= ~(3<<12); \
|
650 |
|
|
BX_CPU_THIS_PTR eflags |= ((3&val) << 12); \
|
651 |
|
|
} \
|
652 |
|
|
BX_CPP_INLINE Bit32u BX_CPU_C::get_IOPL() { \
|
653 |
|
|
return 3 & (BX_CPU_THIS_PTR eflags >> 12); \
|
654 |
|
|
}
|
655 |
|
|
|
656 |
|
|
#define EFlagsCFMask (1 << 0)
|
657 |
|
|
#define EFlagsPFMask (1 << 2)
|
658 |
|
|
#define EFlagsAFMask (1 << 4)
|
659 |
|
|
#define EFlagsZFMask (1 << 6)
|
660 |
|
|
#define EFlagsSFMask (1 << 7)
|
661 |
|
|
#define EFlagsTFMask (1 << 8)
|
662 |
|
|
#define EFlagsIFMask (1 << 9)
|
663 |
|
|
#define EFlagsDFMask (1 << 10)
|
664 |
|
|
#define EFlagsOFMask (1 << 11)
|
665 |
|
|
#define EFlagsIOPLMask (3 << 12)
|
666 |
|
|
#define EFlagsNTMask (1 << 14)
|
667 |
|
|
#define EFlagsRFMask (1 << 16)
|
668 |
|
|
#define EFlagsVMMask (1 << 17)
|
669 |
|
|
#define EFlagsACMask (1 << 18)
|
670 |
|
|
#define EFlagsVIFMask (1 << 19)
|
671 |
|
|
#define EFlagsVIPMask (1 << 20)
|
672 |
|
|
#define EFlagsIDMask (1 << 21)
|
673 |
|
|
|
674 |
|
|
#define EFlagsOSZAPCMask \
|
675 |
|
|
(EFlagsCFMask | EFlagsPFMask | EFlagsAFMask | EFlagsZFMask | EFlagsSFMask | EFlagsOFMask)
|
676 |
|
|
|
677 |
|
|
#define EFlagsOSZAPMask \
|
678 |
|
|
(EFlagsPFMask | EFlagsAFMask | EFlagsZFMask | EFlagsSFMask | EFlagsOFMask)
|
679 |
|
|
|
680 |
|
|
#define EFlagsValidMask 0x003f7fd5 // only supported bits for EFLAGS
|
681 |
|
|
|
682 |
|
|
#if BX_CPU_LEVEL >= 5
|
683 |
|
|
typedef struct
|
684 |
|
|
{
|
685 |
|
|
#if BX_SUPPORT_APIC
|
686 |
|
|
bx_phy_address apicbase;
|
687 |
|
|
#endif
|
688 |
|
|
|
689 |
|
|
#define MSR_STAR (BX_CPU_THIS_PTR msr.star)
|
690 |
|
|
|
691 |
|
|
// SYSCALL/SYSRET instruction msr's
|
692 |
|
|
Bit64u star;
|
693 |
|
|
#if BX_SUPPORT_X86_64
|
694 |
|
|
Bit64u lstar;
|
695 |
|
|
Bit64u cstar;
|
696 |
|
|
Bit32u fmask;
|
697 |
|
|
Bit64u kernelgsbase;
|
698 |
|
|
Bit32u tsc_aux;
|
699 |
|
|
#endif
|
700 |
|
|
|
701 |
|
|
#if BX_CPU_LEVEL >= 6
|
702 |
|
|
// SYSENTER/SYSEXIT instruction msr's
|
703 |
|
|
Bit32u sysenter_cs_msr;
|
704 |
|
|
bx_address sysenter_esp_msr;
|
705 |
|
|
bx_address sysenter_eip_msr;
|
706 |
|
|
|
707 |
|
|
Bit64u mtrrphys[16];
|
708 |
|
|
Bit64u mtrrfix64k_00000;
|
709 |
|
|
Bit64u mtrrfix16k[2];
|
710 |
|
|
Bit64u mtrrfix4k[8];
|
711 |
|
|
Bit16u mtrr_deftype;
|
712 |
|
|
Bit64u pat;
|
713 |
|
|
#endif
|
714 |
|
|
|
715 |
|
|
#if BX_SUPPORT_VMX
|
716 |
|
|
Bit32u ia32_feature_ctrl;
|
717 |
|
|
#endif
|
718 |
|
|
|
719 |
|
|
#if BX_SUPPORT_SVM
|
720 |
|
|
Bit64u svm_hsave_pa;
|
721 |
|
|
#endif
|
722 |
|
|
|
723 |
|
|
/* TODO finish of the others */
|
724 |
|
|
} bx_regs_msr_t;
|
725 |
|
|
#endif
|
726 |
|
|
|
727 |
|
|
#include "cpuid.h"
|
728 |
|
|
#include "crregs.h"
|
729 |
|
|
#include "descriptor.h"
|
730 |
|
|
#include "instr.h"
|
731 |
|
|
#include "lazy_flags.h"
|
732 |
|
|
|
733 |
|
|
// BX_TLB_SIZE: Number of entries in TLB
|
734 |
|
|
// BX_TLB_INDEX_OF(lpf): This macro is passed the linear page frame
|
735 |
|
|
// (top 20 bits of the linear address. It must map these bits to
|
736 |
|
|
// one of the TLB cache slots, given the size of BX_TLB_SIZE.
|
737 |
|
|
// There will be a many-to-one mapping to each TLB cache slot.
|
738 |
|
|
// When there are collisions, the old entry is overwritten with
|
739 |
|
|
// one for the newest access.
|
740 |
|
|
|
741 |
|
|
#define BX_TLB_SIZE 1024
|
742 |
|
|
#define BX_TLB_MASK ((BX_TLB_SIZE-1) << 12)
|
743 |
|
|
#define BX_TLB_INDEX_OF(lpf, len) ((((unsigned)(lpf) + (len)) & BX_TLB_MASK) >> 12)
|
744 |
|
|
|
745 |
|
|
typedef bx_ptr_equiv_t bx_hostpageaddr_t;
|
746 |
|
|
|
747 |
|
|
typedef struct {
|
748 |
|
|
bx_address lpf; // linear page frame
|
749 |
|
|
bx_phy_address ppf; // physical page frame
|
750 |
|
|
bx_hostpageaddr_t hostPageAddr;
|
751 |
|
|
Bit32u accessBits;
|
752 |
|
|
Bit32u lpf_mask; // linear address mask of the page size
|
753 |
|
|
} bx_TLB_entry;
|
754 |
|
|
|
755 |
|
|
#if BX_SUPPORT_X86_64
|
756 |
|
|
#define LPF_MASK BX_CONST64(0xfffffffffffff000)
|
757 |
|
|
#else
|
758 |
|
|
#define LPF_MASK (0xfffff000)
|
759 |
|
|
#endif
|
760 |
|
|
|
761 |
|
|
#if BX_PHY_ADDRESS_LONG
|
762 |
|
|
#define PPF_MASK BX_CONST64(0xfffffffffffff000)
|
763 |
|
|
#else
|
764 |
|
|
#define PPF_MASK (0xfffff000)
|
765 |
|
|
#endif
|
766 |
|
|
|
767 |
|
|
#define LPFOf(laddr) ((laddr) & LPF_MASK)
|
768 |
|
|
#define PPFOf(laddr) ((laddr) & PPF_MASK)
|
769 |
|
|
|
770 |
|
|
#define AlignedAccessLPFOf(laddr, alignment_mask) \
|
771 |
|
|
((laddr) & (LPF_MASK | (alignment_mask)))
|
772 |
|
|
|
773 |
|
|
#define PAGE_OFFSET(laddr) ((Bit32u)(laddr) & 0xfff)
|
774 |
|
|
|
775 |
|
|
#include "icache.h"
|
776 |
|
|
|
777 |
|
|
// general purpose register
|
778 |
|
|
#if BX_SUPPORT_X86_64
|
779 |
|
|
|
780 |
|
|
#ifdef BX_BIG_ENDIAN
|
781 |
|
|
typedef struct {
|
782 |
|
|
union {
|
783 |
|
|
struct {
|
784 |
|
|
Bit32u dword_filler;
|
785 |
|
|
Bit16u word_filler;
|
786 |
|
|
union {
|
787 |
|
|
Bit16u rx;
|
788 |
|
|
struct {
|
789 |
|
|
Bit8u rh;
|
790 |
|
|
Bit8u rl;
|
791 |
|
|
} byte;
|
792 |
|
|
};
|
793 |
|
|
} word;
|
794 |
|
|
Bit64u rrx;
|
795 |
|
|
struct {
|
796 |
|
|
Bit32u hrx; // hi 32 bits
|
797 |
|
|
Bit32u erx; // lo 32 bits
|
798 |
|
|
} dword;
|
799 |
|
|
};
|
800 |
|
|
} bx_gen_reg_t;
|
801 |
|
|
#else
|
802 |
|
|
typedef struct {
|
803 |
|
|
union {
|
804 |
|
|
struct {
|
805 |
|
|
union {
|
806 |
|
|
Bit16u rx;
|
807 |
|
|
struct {
|
808 |
|
|
Bit8u rl;
|
809 |
|
|
Bit8u rh;
|
810 |
|
|
} byte;
|
811 |
|
|
};
|
812 |
|
|
Bit16u word_filler;
|
813 |
|
|
Bit32u dword_filler;
|
814 |
|
|
} word;
|
815 |
|
|
Bit64u rrx;
|
816 |
|
|
struct {
|
817 |
|
|
Bit32u erx; // lo 32 bits
|
818 |
|
|
Bit32u hrx; // hi 32 bits
|
819 |
|
|
} dword;
|
820 |
|
|
};
|
821 |
|
|
} bx_gen_reg_t;
|
822 |
|
|
|
823 |
|
|
#endif
|
824 |
|
|
|
825 |
|
|
#else // #if BX_SUPPORT_X86_64
|
826 |
|
|
|
827 |
|
|
#ifdef BX_BIG_ENDIAN
|
828 |
|
|
typedef struct {
|
829 |
|
|
union {
|
830 |
|
|
struct {
|
831 |
|
|
Bit32u erx;
|
832 |
|
|
} dword;
|
833 |
|
|
struct {
|
834 |
|
|
Bit16u word_filler;
|
835 |
|
|
union {
|
836 |
|
|
Bit16u rx;
|
837 |
|
|
struct {
|
838 |
|
|
Bit8u rh;
|
839 |
|
|
Bit8u rl;
|
840 |
|
|
} byte;
|
841 |
|
|
};
|
842 |
|
|
} word;
|
843 |
|
|
};
|
844 |
|
|
} bx_gen_reg_t;
|
845 |
|
|
#else
|
846 |
|
|
typedef struct {
|
847 |
|
|
union {
|
848 |
|
|
struct {
|
849 |
|
|
Bit32u erx;
|
850 |
|
|
} dword;
|
851 |
|
|
struct {
|
852 |
|
|
union {
|
853 |
|
|
Bit16u rx;
|
854 |
|
|
struct {
|
855 |
|
|
Bit8u rl;
|
856 |
|
|
Bit8u rh;
|
857 |
|
|
} byte;
|
858 |
|
|
};
|
859 |
|
|
Bit16u word_filler;
|
860 |
|
|
} word;
|
861 |
|
|
};
|
862 |
|
|
} bx_gen_reg_t;
|
863 |
|
|
#endif
|
864 |
|
|
|
865 |
|
|
#endif // #if BX_SUPPORT_X86_64
|
866 |
|
|
|
867 |
|
|
#if BX_SUPPORT_APIC
|
868 |
|
|
#include "apic.h"
|
869 |
|
|
#endif
|
870 |
|
|
|
871 |
|
|
#if BX_SUPPORT_FPU
|
872 |
|
|
#include "i387.h"
|
873 |
|
|
#include "xmm.h"
|
874 |
|
|
#endif
|
875 |
|
|
|
876 |
|
|
#if BX_SUPPORT_VMX
|
877 |
|
|
#include "vmx.h"
|
878 |
|
|
#endif
|
879 |
|
|
|
880 |
|
|
#if BX_SUPPORT_SVM
|
881 |
|
|
#include "svm.h"
|
882 |
|
|
#endif
|
883 |
|
|
|
884 |
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
885 |
|
|
struct monitor_addr_t {
|
886 |
|
|
|
887 |
|
|
bx_phy_address monitor_addr;
|
888 |
|
|
bx_bool armed;
|
889 |
|
|
|
890 |
|
|
monitor_addr_t(): monitor_addr(0xffffffff), armed(0) {}
|
891 |
|
|
|
892 |
|
|
BX_CPP_INLINE void arm(bx_phy_address addr) {
|
893 |
|
|
// align to cache line
|
894 |
|
|
monitor_addr = addr & ~((bx_phy_address)(CACHE_LINE_SIZE - 1));
|
895 |
|
|
armed = 1;
|
896 |
|
|
}
|
897 |
|
|
|
898 |
|
|
BX_CPP_INLINE void reset_monitor(void) { armed = 0; }
|
899 |
|
|
};
|
900 |
|
|
#endif
|
901 |
|
|
|
902 |
|
|
struct BX_SMM_State;
|
903 |
|
|
|
904 |
|
|
class BOCHSAPI BX_CPU_C : public logfunctions {
|
905 |
|
|
|
906 |
|
|
public: // for now...
|
907 |
|
|
|
908 |
|
|
unsigned bx_cpuid;
|
909 |
|
|
|
910 |
|
|
#if BX_CPU_LEVEL >= 4
|
911 |
|
|
bx_cpuid_t *cpuid;
|
912 |
|
|
#endif
|
913 |
|
|
|
914 |
|
|
Bit64u isa_extensions_bitmask;
|
915 |
|
|
Bit32u cpu_extensions_bitmask;
|
916 |
|
|
#if BX_SUPPORT_VMX
|
917 |
|
|
Bit32u vmx_extensions_bitmask;
|
918 |
|
|
#endif
|
919 |
|
|
#if BX_SUPPORT_SVM
|
920 |
|
|
Bit32u svm_extensions_bitmask;
|
921 |
|
|
#endif
|
922 |
|
|
|
923 |
|
|
#define BX_CPUID_SUPPORT_ISA_EXTENSION(feature) \
|
924 |
|
|
(BX_CPU_THIS_PTR isa_extensions_bitmask & (feature))
|
925 |
|
|
|
926 |
|
|
#define BX_CPUID_SUPPORT_CPU_EXTENSION(feature) \
|
927 |
|
|
(BX_CPU_THIS_PTR cpu_extensions_bitmask & (feature))
|
928 |
|
|
|
929 |
|
|
#define BX_SUPPORT_VMX_EXTENSION(feature) \
|
930 |
|
|
(BX_CPU_THIS_PTR vmx_extensions_bitmask & (feature))
|
931 |
|
|
|
932 |
|
|
#define BX_SUPPORT_SVM_EXTENSION(feature) \
|
933 |
|
|
(BX_CPU_THIS_PTR svm_extensions_bitmask & (feature))
|
934 |
|
|
|
935 |
|
|
// General register set
|
936 |
|
|
// rax: accumulator
|
937 |
|
|
// rbx: base
|
938 |
|
|
// rcx: count
|
939 |
|
|
// rdx: data
|
940 |
|
|
// rbp: base pointer
|
941 |
|
|
// rsi: source index
|
942 |
|
|
// rdi: destination index
|
943 |
|
|
// esp: stack pointer
|
944 |
|
|
// r8..r15 x86-64 extended registers
|
945 |
|
|
// rip: instruction pointer
|
946 |
|
|
// nil: null register
|
947 |
|
|
// tmp: temp register
|
948 |
|
|
bx_gen_reg_t gen_reg[BX_GENERAL_REGISTERS+3];
|
949 |
|
|
|
950 |
|
|
/* 31|30|29|28| 27|26|25|24| 23|22|21|20| 19|18|17|16
|
951 |
|
|
* ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
|
952 |
|
|
* 0| 0| 0| 0| 0| 0| 0| 0| 0| 0|ID|VP| VF|AC|VM|RF
|
953 |
|
|
*
|
954 |
|
|
* 15|14|13|12| 11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
|
955 |
|
|
* ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
|
956 |
|
|
* 0|NT| IOPL| OF|DF|IF|TF| SF|ZF| 0|AF| 0|PF| 1|CF
|
957 |
|
|
*/
|
958 |
|
|
Bit32u eflags; // Raw 32-bit value in x86 bit position.
|
959 |
|
|
|
960 |
|
|
// lazy arithmetic flags state
|
961 |
|
|
bx_lf_flags_entry oszapc;
|
962 |
|
|
|
963 |
|
|
// so that we can back up when handling faults, exceptions, etc.
|
964 |
|
|
// we need to store the value of the instruction pointer, before
|
965 |
|
|
// each fetch/execute cycle.
|
966 |
|
|
bx_address prev_rip;
|
967 |
|
|
bx_address prev_rsp;
|
968 |
|
|
bx_bool speculative_rsp;
|
969 |
|
|
|
970 |
|
|
Bit64u icount;
|
971 |
|
|
Bit64u icount_last_sync;
|
972 |
|
|
|
973 |
|
|
#define BX_INHIBIT_INTERRUPTS 0x01
|
974 |
|
|
#define BX_INHIBIT_DEBUG 0x02
|
975 |
|
|
|
976 |
|
|
#define BX_INHIBIT_INTERRUPTS_BY_MOVSS \
|
977 |
|
|
(BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG)
|
978 |
|
|
|
979 |
|
|
// What events to inhibit at any given time. Certain instructions
|
980 |
|
|
// inhibit interrupts, some debug exceptions and single-step traps.
|
981 |
|
|
unsigned inhibit_mask;
|
982 |
|
|
Bit64u inhibit_icount;
|
983 |
|
|
|
984 |
|
|
/* user segment register set */
|
985 |
|
|
bx_segment_reg_t sregs[6];
|
986 |
|
|
|
987 |
|
|
/* system segment registers */
|
988 |
|
|
bx_global_segment_reg_t gdtr; /* global descriptor table register */
|
989 |
|
|
bx_global_segment_reg_t idtr; /* interrupt descriptor table register */
|
990 |
|
|
bx_segment_reg_t ldtr; /* local descriptor table register */
|
991 |
|
|
bx_segment_reg_t tr; /* task register */
|
992 |
|
|
|
993 |
|
|
/* debug registers DR0-DR7 */
|
994 |
|
|
bx_address dr[4]; /* DR0-DR3 */
|
995 |
|
|
bx_dr6_t dr6;
|
996 |
|
|
bx_dr7_t dr7;
|
997 |
|
|
|
998 |
|
|
Bit32u debug_trap; // holds DR6 value (16bit) to be set
|
999 |
|
|
|
1000 |
|
|
/* Control registers */
|
1001 |
|
|
bx_cr0_t cr0;
|
1002 |
|
|
bx_address cr2;
|
1003 |
|
|
bx_address cr3;
|
1004 |
|
|
#if BX_CPU_LEVEL >= 5
|
1005 |
|
|
bx_cr4_t cr4;
|
1006 |
|
|
Bit32u cr4_suppmask;
|
1007 |
|
|
|
1008 |
|
|
bx_efer_t efer;
|
1009 |
|
|
Bit32u efer_suppmask;
|
1010 |
|
|
#endif
|
1011 |
|
|
|
1012 |
|
|
#if BX_CPU_LEVEL >= 5
|
1013 |
|
|
// TSC: Time Stamp Counter
|
1014 |
|
|
// Instead of storing a counter and incrementing it every instruction, we
|
1015 |
|
|
// remember the time in ticks that it was reset to zero. With a little
|
1016 |
|
|
// algebra, we can also support setting it to something other than zero.
|
1017 |
|
|
// Don't read this directly; use get_TSC and set_TSC to access the TSC.
|
1018 |
|
|
Bit64u tsc_last_reset;
|
1019 |
|
|
#if BX_SUPPORT_VMX || BX_SUPPORT_SVM
|
1020 |
|
|
Bit64s tsc_offset;
|
1021 |
|
|
#endif
|
1022 |
|
|
#endif
|
1023 |
|
|
|
1024 |
|
|
#if BX_CPU_LEVEL >= 6
|
1025 |
|
|
xcr0_t xcr0;
|
1026 |
|
|
Bit32u xcr0_suppmask;
|
1027 |
|
|
#endif
|
1028 |
|
|
|
1029 |
|
|
#if BX_SUPPORT_FPU
|
1030 |
|
|
i387_t the_i387;
|
1031 |
|
|
#endif
|
1032 |
|
|
|
1033 |
|
|
#if BX_CPU_LEVEL >= 6
|
1034 |
|
|
#if BX_SUPPORT_AVX
|
1035 |
|
|
bx_avx_reg_t vmm[BX_XMM_REGISTERS+1];
|
1036 |
|
|
#else
|
1037 |
|
|
bx_xmm_reg_t vmm[BX_XMM_REGISTERS+1];
|
1038 |
|
|
#endif
|
1039 |
|
|
bx_mxcsr_t mxcsr;
|
1040 |
|
|
Bit32u mxcsr_mask;
|
1041 |
|
|
#endif
|
1042 |
|
|
|
1043 |
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
1044 |
|
|
monitor_addr_t monitor;
|
1045 |
|
|
#endif
|
1046 |
|
|
|
1047 |
|
|
#if BX_SUPPORT_APIC
|
1048 |
|
|
bx_local_apic_c lapic;
|
1049 |
|
|
#endif
|
1050 |
|
|
|
1051 |
|
|
/* SMM base register */
|
1052 |
|
|
Bit32u smbase;
|
1053 |
|
|
|
1054 |
|
|
#if BX_CPU_LEVEL >= 5
|
1055 |
|
|
bx_regs_msr_t msr;
|
1056 |
|
|
#endif
|
1057 |
|
|
|
1058 |
|
|
#if BX_CONFIGURE_MSRS
|
1059 |
|
|
MSR *msrs[BX_MSR_MAX_INDEX];
|
1060 |
|
|
#endif
|
1061 |
|
|
|
1062 |
|
|
#if BX_SUPPORT_VMX
|
1063 |
|
|
bx_bool in_vmx;
|
1064 |
|
|
bx_bool in_vmx_guest;
|
1065 |
|
|
bx_bool in_smm_vmx; // save in_vmx and in_vmx_guest flags when in SMM mode
|
1066 |
|
|
bx_bool in_smm_vmx_guest;
|
1067 |
|
|
Bit64u vmcsptr;
|
1068 |
|
|
bx_hostpageaddr_t vmcshostptr;
|
1069 |
|
|
Bit64u vmxonptr;
|
1070 |
|
|
|
1071 |
|
|
VMCS_CACHE vmcs;
|
1072 |
|
|
VMX_CAP vmx_cap;
|
1073 |
|
|
#endif
|
1074 |
|
|
|
1075 |
|
|
#if BX_SUPPORT_SVM
|
1076 |
|
|
bx_bool in_svm_guest;
|
1077 |
|
|
bx_bool svm_gif; /* global interrupt enable flag, when zero all external interrupt disabled */
|
1078 |
|
|
bx_phy_address vmcbptr;
|
1079 |
|
|
bx_hostpageaddr_t vmcbhostptr;
|
1080 |
|
|
VMCB_CACHE vmcb;
|
1081 |
|
|
|
1082 |
|
|
// make SVM integration easier
|
1083 |
|
|
#define SVM_GIF (BX_CPU_THIS_PTR svm_gif)
|
1084 |
|
|
|
1085 |
|
|
#else
|
1086 |
|
|
|
1087 |
|
|
#define SVM_GIF (1)
|
1088 |
|
|
|
1089 |
|
|
#endif
|
1090 |
|
|
|
1091 |
|
|
#if BX_SUPPORT_VMX || BX_SUPPORT_SVM
|
1092 |
|
|
bx_bool in_event;
|
1093 |
|
|
#endif
|
1094 |
|
|
|
1095 |
|
|
#if BX_SUPPORT_VMX
|
1096 |
|
|
bx_bool nmi_unblocking_iret;
|
1097 |
|
|
#endif
|
1098 |
|
|
|
1099 |
|
|
bx_bool EXT; /* 1 if processing external interrupt or exception
|
1100 |
|
|
* or if not related to current instruction,
|
1101 |
|
|
* 0 if current CS:IP caused exception */
|
1102 |
|
|
|
1103 |
|
|
enum CPU_Activity_State {
|
1104 |
|
|
BX_ACTIVITY_STATE_ACTIVE = 0,
|
1105 |
|
|
BX_ACTIVITY_STATE_HLT,
|
1106 |
|
|
BX_ACTIVITY_STATE_SHUTDOWN,
|
1107 |
|
|
BX_ACTIVITY_STATE_WAIT_FOR_SIPI,
|
1108 |
|
|
BX_ACTIVITY_STATE_MWAIT,
|
1109 |
|
|
BX_ACTIVITY_STATE_MWAIT_IF
|
1110 |
|
|
};
|
1111 |
|
|
|
1112 |
|
|
#define BX_VMX_LAST_ACTIVITY_STATE (BX_ACTIVITY_STATE_WAIT_FOR_SIPI)
|
1113 |
|
|
|
1114 |
|
|
unsigned activity_state;
|
1115 |
|
|
|
1116 |
|
|
#define BX_EVENT_NMI (1 << 0)
|
1117 |
|
|
#define BX_EVENT_SMI (1 << 1)
|
1118 |
|
|
#define BX_EVENT_INIT (1 << 2)
|
1119 |
|
|
#define BX_EVENT_CODE_BREAKPOINT_ASSIST (1 << 3)
|
1120 |
|
|
#define BX_EVENT_VMX_MONITOR_TRAP_FLAG (1 << 4)
|
1121 |
|
|
#define BX_EVENT_VMX_PREEMPTION_TIMER_EXPIRED (1 << 5)
|
1122 |
|
|
#define BX_EVENT_VMX_INTERRUPT_WINDOW_EXITING (1 << 6)
|
1123 |
|
|
#define BX_EVENT_VMX_VIRTUAL_NMI (1 << 7)
|
1124 |
|
|
#define BX_EVENT_SVM_VIRQ_PENDING (1 << 8)
|
1125 |
|
|
#define BX_EVENT_PENDING_VMX_VIRTUAL_INTR (1 << 9)
|
1126 |
|
|
#define BX_EVENT_PENDING_INTR (1 << 10)
|
1127 |
|
|
#define BX_EVENT_PENDING_LAPIC_INTR (1 << 11)
|
1128 |
|
|
#define BX_EVENT_VMX_VTPR_UPDATE (1 << 12)
|
1129 |
|
|
#define BX_EVENT_VMX_VEOI_UPDATE (1 << 13)
|
1130 |
|
|
#define BX_EVENT_VMX_VIRTUAL_APIC_WRITE (1 << 14)
|
1131 |
|
|
Bit32u pending_event;
|
1132 |
|
|
Bit32u event_mask;
|
1133 |
|
|
Bit32u async_event;
|
1134 |
|
|
|
1135 |
|
|
BX_SMF BX_CPP_INLINE void signal_event(Bit32u event) {
|
1136 |
|
|
BX_CPU_THIS_PTR pending_event |= event;
|
1137 |
|
|
if (! is_masked_event(event)) BX_CPU_THIS_PTR async_event = 1;
|
1138 |
|
|
}
|
1139 |
|
|
|
1140 |
|
|
BX_SMF BX_CPP_INLINE void clear_event(Bit32u event) {
|
1141 |
|
|
BX_CPU_THIS_PTR pending_event &= ~event;
|
1142 |
|
|
}
|
1143 |
|
|
|
1144 |
|
|
BX_SMF BX_CPP_INLINE void mask_event(Bit32u event) {
|
1145 |
|
|
BX_CPU_THIS_PTR event_mask |= event;
|
1146 |
|
|
}
|
1147 |
|
|
BX_SMF BX_CPP_INLINE void unmask_event(Bit32u event) {
|
1148 |
|
|
BX_CPU_THIS_PTR event_mask &= ~event;
|
1149 |
|
|
if (is_pending(event)) BX_CPU_THIS_PTR async_event = 1;
|
1150 |
|
|
}
|
1151 |
|
|
|
1152 |
|
|
BX_SMF BX_CPP_INLINE bx_bool is_masked_event(Bit32u event) {
|
1153 |
|
|
return (BX_CPU_THIS_PTR event_mask & event) != 0;
|
1154 |
|
|
}
|
1155 |
|
|
|
1156 |
|
|
BX_SMF BX_CPP_INLINE bx_bool is_pending(Bit32u event) {
|
1157 |
|
|
return (BX_CPU_THIS_PTR pending_event & event) != 0;
|
1158 |
|
|
}
|
1159 |
|
|
BX_SMF BX_CPP_INLINE bx_bool is_unmasked_event_pending(Bit32u event) {
|
1160 |
|
|
return (BX_CPU_THIS_PTR pending_event & ~BX_CPU_THIS_PTR event_mask & event) != 0;
|
1161 |
|
|
}
|
1162 |
|
|
|
1163 |
|
|
BX_SMF BX_CPP_INLINE Bit32u unmasked_events_pending(void) {
|
1164 |
|
|
return (BX_CPU_THIS_PTR pending_event & ~BX_CPU_THIS_PTR event_mask);
|
1165 |
|
|
}
|
1166 |
|
|
|
1167 |
|
|
#define BX_ASYNC_EVENT_STOP_TRACE (1<<31)
|
1168 |
|
|
|
1169 |
|
|
#if BX_X86_DEBUGGER
|
1170 |
|
|
bx_bool in_repeat;
|
1171 |
|
|
#endif
|
1172 |
|
|
bx_bool in_smm;
|
1173 |
|
|
unsigned cpu_mode;
|
1174 |
|
|
bx_bool user_pl;
|
1175 |
|
|
#if BX_CPU_LEVEL >= 5
|
1176 |
|
|
bx_bool ignore_bad_msrs;
|
1177 |
|
|
#endif
|
1178 |
|
|
#if BX_CPU_LEVEL >= 6
|
1179 |
|
|
unsigned sse_ok;
|
1180 |
|
|
#if BX_SUPPORT_AVX
|
1181 |
|
|
unsigned avx_ok;
|
1182 |
|
|
#endif
|
1183 |
|
|
#endif
|
1184 |
|
|
|
1185 |
|
|
// for exceptions
|
1186 |
|
|
jmp_buf jmp_buf_env;
|
1187 |
|
|
unsigned last_exception_type;
|
1188 |
|
|
|
1189 |
|
|
// Boundaries of current code page, based on EIP
|
1190 |
|
|
bx_address eipPageBias;
|
1191 |
|
|
Bit32u eipPageWindowSize;
|
1192 |
|
|
const Bit8u *eipFetchPtr;
|
1193 |
|
|
bx_phy_address pAddrFetchPage; // Guest physical address of current instruction page
|
1194 |
|
|
|
1195 |
|
|
// Boundaries of current stack page, based on ESP
|
1196 |
|
|
bx_address espPageBias; // Linear address of current stack page
|
1197 |
|
|
Bit32u espPageWindowSize;
|
1198 |
|
|
const Bit8u *espHostPtr;
|
1199 |
|
|
bx_phy_address pAddrStackPage; // Guest physical address of current stack page
|
1200 |
|
|
|
1201 |
|
|
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
1202 |
|
|
unsigned alignment_check_mask;
|
1203 |
|
|
#endif
|
1204 |
|
|
|
1205 |
|
|
#if BX_DEBUGGER
|
1206 |
|
|
bx_phy_address watchpoint;
|
1207 |
|
|
Bit8u break_point;
|
1208 |
|
|
Bit8u magic_break;
|
1209 |
|
|
Bit8u stop_reason;
|
1210 |
|
|
bx_bool trace;
|
1211 |
|
|
bx_bool trace_reg;
|
1212 |
|
|
bx_bool trace_mem;
|
1213 |
|
|
bx_bool mode_break;
|
1214 |
|
|
#if BX_SUPPORT_VMX
|
1215 |
|
|
bx_bool vmexit_break;
|
1216 |
|
|
#endif
|
1217 |
|
|
unsigned show_flag;
|
1218 |
|
|
bx_guard_found_t guard_found;
|
1219 |
|
|
#endif
|
1220 |
|
|
|
1221 |
|
|
// for paging
|
1222 |
|
|
struct {
|
1223 |
|
|
bx_TLB_entry entry[BX_TLB_SIZE] BX_CPP_AlignN(16);
|
1224 |
|
|
#if BX_CPU_LEVEL >= 5
|
1225 |
|
|
bx_bool split_large;
|
1226 |
|
|
#endif
|
1227 |
|
|
} TLB;
|
1228 |
|
|
|
1229 |
|
|
#define BX_TLB_ENTRY_OF(lpf) (&BX_CPU_THIS_PTR TLB.entry[BX_TLB_INDEX_OF((lpf), 0)])
|
1230 |
|
|
|
1231 |
|
|
#if BX_CPU_LEVEL >= 6
|
1232 |
|
|
struct {
|
1233 |
|
|
Bit64u entry[4];
|
1234 |
|
|
} PDPTR_CACHE;
|
1235 |
|
|
#endif
|
1236 |
|
|
|
1237 |
|
|
// An instruction cache. Each entry should be exactly 32 bytes, and
|
1238 |
|
|
// this structure should be aligned on a 32-byte boundary to be friendly
|
1239 |
|
|
// with the host cache lines.
|
1240 |
|
|
bxICache_c iCache BX_CPP_AlignN(32);
|
1241 |
|
|
Bit32u fetchModeMask;
|
1242 |
|
|
|
1243 |
|
|
struct {
|
1244 |
|
|
bx_address rm_addr; // The address offset after resolution
|
1245 |
|
|
bx_phy_address paddress1; // physical address after translation of 1st len1 bytes of data
|
1246 |
|
|
bx_phy_address paddress2; // physical address after translation of 2nd len2 bytes of data
|
1247 |
|
|
Bit32u len1; // Number of bytes in page 1
|
1248 |
|
|
Bit32u len2; // Number of bytes in page 2
|
1249 |
|
|
bx_ptr_equiv_t pages; // Number of pages access spans (1 or 2). Also used
|
1250 |
|
|
// for the case when a native host pointer is
|
1251 |
|
|
// available for the R-M-W instructions. The host
|
1252 |
|
|
// pointer is stuffed here. Since this field has
|
1253 |
|
|
// to be checked anyways (and thus cached), if it
|
1254 |
|
|
// is greated than 2 (the maximum possible for
|
1255 |
|
|
// normal cases) it is a native pointer and is used
|
1256 |
|
|
// for a direct write access.
|
1257 |
|
|
} address_xlation;
|
1258 |
|
|
|
1259 |
|
|
BX_SMF void setEFlags(Bit32u val) BX_CPP_AttrRegparmN(1);
|
1260 |
|
|
|
1261 |
|
|
BX_SMF BX_CPP_INLINE void setEFlagsOSZAPC(Bit32u flags32) {
|
1262 |
|
|
set_OF(1 & ((flags32) >> 11));
|
1263 |
|
|
set_SF(1 & ((flags32) >> 7));
|
1264 |
|
|
set_ZF(1 & ((flags32) >> 6));
|
1265 |
|
|
set_AF(1 & ((flags32) >> 4));
|
1266 |
|
|
set_PF(1 & ((flags32) >> 2));
|
1267 |
|
|
set_CF(1 & ((flags32) >> 0));
|
1268 |
|
|
}
|
1269 |
|
|
|
1270 |
|
|
BX_SMF BX_CPP_INLINE void SET_FLAGS_OxxxxC(Bit32u new_of, Bit32u new_cf) {
|
1271 |
|
|
Bit32u temp_po = new_of ^ new_cf;
|
1272 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits &= ~(LF_MASK_PO | LF_MASK_CF);
|
1273 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits |=
|
1274 |
|
|
(temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF);
|
1275 |
|
|
}
|
1276 |
|
|
|
1277 |
|
|
BX_SMF BX_CPP_INLINE void ASSERT_FLAGS_OxxxxC() {
|
1278 |
|
|
SET_FLAGS_OxxxxC(1, 1);
|
1279 |
|
|
}
|
1280 |
|
|
|
1281 |
|
|
// ZF
|
1282 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_ZF(void) {
|
1283 |
|
|
return (0 == BX_CPU_THIS_PTR oszapc.result);
|
1284 |
|
|
}
|
1285 |
|
|
|
1286 |
|
|
BX_SMF BX_CPP_INLINE bx_bool get_ZF(void) { return getB_ZF(); }
|
1287 |
|
|
|
1288 |
|
|
BX_SMF BX_CPP_INLINE void set_ZF(bx_bool val) {
|
1289 |
|
|
if (val) assert_ZF();
|
1290 |
|
|
else clear_ZF();
|
1291 |
|
|
}
|
1292 |
|
|
|
1293 |
|
|
BX_SMF BX_CPP_INLINE void clear_ZF(void) {
|
1294 |
|
|
BX_CPU_THIS_PTR oszapc.result |= (1 << 8);
|
1295 |
|
|
}
|
1296 |
|
|
|
1297 |
|
|
BX_SMF BX_CPP_INLINE void assert_ZF(void) {
|
1298 |
|
|
// merge the sign bit into the Sign Delta
|
1299 |
|
|
|
1300 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits ^=
|
1301 |
|
|
(((BX_CPU_THIS_PTR oszapc.result >> BX_LF_SIGN_BIT) & 1) << LF_BIT_SD);
|
1302 |
|
|
|
1303 |
|
|
// merge the parity bits into the Parity Delta Byte
|
1304 |
|
|
|
1305 |
|
|
Bit32u temp_pdb = (255 & BX_CPU_THIS_PTR oszapc.result);
|
1306 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits ^= (temp_pdb << LF_BIT_PDB);
|
1307 |
|
|
|
1308 |
|
|
// now zero the .result value
|
1309 |
|
|
|
1310 |
|
|
BX_CPU_THIS_PTR oszapc.result = 0;
|
1311 |
|
|
}
|
1312 |
|
|
|
1313 |
|
|
// SF
|
1314 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_SF(void) {
|
1315 |
|
|
return ((BX_CPU_THIS_PTR oszapc.result >> BX_LF_SIGN_BIT) ^
|
1316 |
|
|
(BX_CPU_THIS_PTR oszapc.auxbits >> LF_BIT_SD)) & 1;
|
1317 |
|
|
}
|
1318 |
|
|
|
1319 |
|
|
BX_SMF BX_CPP_INLINE bx_bool get_SF(void) { return getB_SF(); }
|
1320 |
|
|
|
1321 |
|
|
BX_SMF BX_CPP_INLINE void set_SF(bx_bool val) {
|
1322 |
|
|
bx_bool temp_sf = getB_SF();
|
1323 |
|
|
|
1324 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits ^= (temp_sf ^ val) << LF_BIT_SD;
|
1325 |
|
|
}
|
1326 |
|
|
|
1327 |
|
|
BX_SMF BX_CPP_INLINE void clear_SF(void) {
|
1328 |
|
|
set_SF(0);
|
1329 |
|
|
}
|
1330 |
|
|
|
1331 |
|
|
BX_SMF BX_CPP_INLINE void assert_SF(void) {
|
1332 |
|
|
set_SF(1);
|
1333 |
|
|
}
|
1334 |
|
|
|
1335 |
|
|
// PF - bit 2 in EFLAGS, represented by lower 8 bits of oszapc.result
|
1336 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_PF(void) {
|
1337 |
|
|
Bit32u temp = (255 & BX_CPU_THIS_PTR oszapc.result);
|
1338 |
|
|
temp = temp ^ (255 & (BX_CPU_THIS_PTR oszapc.auxbits >> LF_BIT_PDB));
|
1339 |
|
|
temp = (temp ^ (temp >> 4)) & 0x0F;
|
1340 |
|
|
return (0x9669U >> temp) & 1;
|
1341 |
|
|
}
|
1342 |
|
|
|
1343 |
|
|
BX_SMF BX_CPP_INLINE bx_bool get_PF(void) { return getB_PF(); }
|
1344 |
|
|
|
1345 |
|
|
BX_SMF BX_CPP_INLINE void set_PF(bx_bool val) {
|
1346 |
|
|
Bit32u temp_pdb = (255 & BX_CPU_THIS_PTR oszapc.result) ^ (!val);
|
1347 |
|
|
|
1348 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits &= ~(LF_MASK_PDB);
|
1349 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits |= (temp_pdb << LF_BIT_PDB);
|
1350 |
|
|
}
|
1351 |
|
|
|
1352 |
|
|
BX_SMF BX_CPP_INLINE void clear_PF(void) {
|
1353 |
|
|
set_PF(0);
|
1354 |
|
|
}
|
1355 |
|
|
|
1356 |
|
|
BX_SMF BX_CPP_INLINE void assert_PF(void) {
|
1357 |
|
|
set_PF(1);
|
1358 |
|
|
}
|
1359 |
|
|
|
1360 |
|
|
// AF - bit 4 in EFLAGS, represented by bit LF_BIT_AF of oszapc.auxbits
|
1361 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_AF(void) {
|
1362 |
|
|
return ((BX_CPU_THIS_PTR oszapc.auxbits >> LF_BIT_AF) & 1);
|
1363 |
|
|
}
|
1364 |
|
|
|
1365 |
|
|
BX_SMF BX_CPP_INLINE bx_bool get_AF(void) { return getB_AF(); }
|
1366 |
|
|
|
1367 |
|
|
BX_SMF BX_CPP_INLINE void set_AF(bx_bool val) {
|
1368 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits &= ~(LF_MASK_AF);
|
1369 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits |= (val) << LF_BIT_AF;
|
1370 |
|
|
}
|
1371 |
|
|
|
1372 |
|
|
BX_SMF BX_CPP_INLINE void clear_AF(void) {
|
1373 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits &= ~(LF_MASK_AF);
|
1374 |
|
|
}
|
1375 |
|
|
|
1376 |
|
|
BX_SMF BX_CPP_INLINE void assert_AF(void) {
|
1377 |
|
|
BX_CPU_THIS_PTR oszapc.auxbits |= (LF_MASK_AF);
|
1378 |
|
|
}
|
1379 |
|
|
|
1380 |
|
|
// CF
|
1381 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_CF(void) {
|
1382 |
|
|
return ((BX_CPU_THIS_PTR oszapc.auxbits >> LF_BIT_CF) & 1);
|
1383 |
|
|
}
|
1384 |
|
|
|
1385 |
|
|
BX_SMF BX_CPP_INLINE bx_bool get_CF(void) {
|
1386 |
|
|
return BX_CPU_THIS_PTR oszapc.auxbits & (1U << LF_BIT_CF);
|
1387 |
|
|
}
|
1388 |
|
|
|
1389 |
|
|
BX_SMF BX_CPP_INLINE void set_CF(bx_bool val) {
|
1390 |
|
|
bx_bool temp_of = getB_OF();
|
1391 |
|
|
SET_FLAGS_OxxxxC(temp_of, (val));
|
1392 |
|
|
}
|
1393 |
|
|
|
1394 |
|
|
BX_SMF BX_CPP_INLINE void clear_CF(void) {
|
1395 |
|
|
bx_bool temp_of = getB_OF();
|
1396 |
|
|
SET_FLAGS_OxxxxC(temp_of, (0));
|
1397 |
|
|
}
|
1398 |
|
|
|
1399 |
|
|
BX_SMF BX_CPP_INLINE void assert_CF(void) {
|
1400 |
|
|
bx_bool temp_of = getB_OF();
|
1401 |
|
|
SET_FLAGS_OxxxxC(temp_of, (1));
|
1402 |
|
|
}
|
1403 |
|
|
|
1404 |
|
|
// OF
|
1405 |
|
|
BX_SMF BX_CPP_INLINE bx_bool getB_OF(void) {
|
1406 |
|
|
return ((BX_CPU_THIS_PTR oszapc.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
|
1407 |
|
|
}
|
1408 |
|
|
|
1409 |
|
|
BX_SMF BX_CPP_INLINE bx_bool get_OF(void) {
|
1410 |
|
|
return (BX_CPU_THIS_PTR oszapc.auxbits + (1U << LF_BIT_PO)) & (1U << LF_BIT_CF);
|
1411 |
|
|
}
|
1412 |
|
|
|
1413 |
|
|
BX_SMF BX_CPP_INLINE void set_OF(bx_bool val) {
|
1414 |
|
|
bx_bool temp_cf = getB_CF();
|
1415 |
|
|
SET_FLAGS_OxxxxC((val), temp_cf);
|
1416 |
|
|
}
|
1417 |
|
|
|
1418 |
|
|
BX_SMF BX_CPP_INLINE void clear_OF(void) {
|
1419 |
|
|
bx_bool temp_cf = getB_CF();
|
1420 |
|
|
SET_FLAGS_OxxxxC((0), temp_cf);
|
1421 |
|
|
}
|
1422 |
|
|
|
1423 |
|
|
BX_SMF BX_CPP_INLINE void assert_OF(void) {
|
1424 |
|
|
bx_bool temp_cf = getB_CF();
|
1425 |
|
|
SET_FLAGS_OxxxxC((1), temp_cf);
|
1426 |
|
|
}
|
1427 |
|
|
|
1428 |
|
|
// constructors & destructors...
|
1429 |
|
|
BX_CPU_C(unsigned id = 0);
|
1430 |
|
|
~BX_CPU_C();
|
1431 |
|
|
|
1432 |
|
|
void initialize(void);
|
1433 |
|
|
void after_restore_state(void);
|
1434 |
|
|
void register_state(void);
|
1435 |
|
|
static Bit64s param_save_handler(void *devptr, bx_param_c *param);
|
1436 |
|
|
static void param_restore_handler(void *devptr, bx_param_c *param, Bit64s val);
|
1437 |
|
|
#if !BX_USE_CPU_SMF
|
1438 |
|
|
Bit64s param_save(bx_param_c *param);
|
1439 |
|
|
void param_restore(bx_param_c *param, Bit64s val);
|
1440 |
|
|
#endif
|
1441 |
|
|
|
1442 |
|
|
// <TAG-CLASS-CPU-START>
|
1443 |
|
|
// prototypes for CPU instructions...
|
1444 |
|
|
BX_SMF BX_INSF_TYPE PUSH16_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1445 |
|
|
BX_SMF BX_INSF_TYPE POP16_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1446 |
|
|
BX_SMF BX_INSF_TYPE PUSH32_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1447 |
|
|
BX_SMF BX_INSF_TYPE POP32_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1448 |
|
|
|
1449 |
|
|
BX_SMF BX_INSF_TYPE DAA(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1450 |
|
|
BX_SMF BX_INSF_TYPE DAS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1451 |
|
|
BX_SMF BX_INSF_TYPE AAA(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1452 |
|
|
BX_SMF BX_INSF_TYPE AAS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1453 |
|
|
BX_SMF BX_INSF_TYPE AAM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1454 |
|
|
BX_SMF BX_INSF_TYPE AAD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1455 |
|
|
|
1456 |
|
|
BX_SMF BX_INSF_TYPE PUSHAD32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1457 |
|
|
BX_SMF BX_INSF_TYPE PUSHAD16(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1458 |
|
|
BX_SMF BX_INSF_TYPE POPAD32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1459 |
|
|
BX_SMF BX_INSF_TYPE POPAD16(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1460 |
|
|
BX_SMF BX_INSF_TYPE ARPL_EwGw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1461 |
|
|
BX_SMF BX_INSF_TYPE PUSH_Id(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1462 |
|
|
BX_SMF BX_INSF_TYPE PUSH_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1463 |
|
|
|
1464 |
|
|
BX_SMF void INSB32_YbDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1465 |
|
|
BX_SMF void INSB16_YbDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1466 |
|
|
BX_SMF void INSW32_YwDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1467 |
|
|
BX_SMF void INSW16_YwDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1468 |
|
|
BX_SMF void INSD32_YdDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1469 |
|
|
BX_SMF void INSD16_YdDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1470 |
|
|
BX_SMF void OUTSB32_DXXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1471 |
|
|
BX_SMF void OUTSB16_DXXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1472 |
|
|
BX_SMF void OUTSW32_DXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1473 |
|
|
BX_SMF void OUTSW16_DXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1474 |
|
|
BX_SMF void OUTSD32_DXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1475 |
|
|
BX_SMF void OUTSD16_DXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1476 |
|
|
|
1477 |
|
|
BX_SMF BX_INSF_TYPE REP_INSB_YbDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1478 |
|
|
BX_SMF BX_INSF_TYPE REP_INSW_YwDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1479 |
|
|
BX_SMF BX_INSF_TYPE REP_INSD_YdDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1480 |
|
|
BX_SMF BX_INSF_TYPE REP_OUTSB_DXXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1481 |
|
|
BX_SMF BX_INSF_TYPE REP_OUTSW_DXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1482 |
|
|
BX_SMF BX_INSF_TYPE REP_OUTSD_DXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1483 |
|
|
|
1484 |
|
|
BX_SMF BX_INSF_TYPE BOUND_GwMa(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1485 |
|
|
BX_SMF BX_INSF_TYPE BOUND_GdMa(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1486 |
|
|
|
1487 |
|
|
BX_SMF BX_INSF_TYPE TEST_EbGbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1488 |
|
|
BX_SMF BX_INSF_TYPE TEST_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1489 |
|
|
BX_SMF BX_INSF_TYPE TEST_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1490 |
|
|
|
1491 |
|
|
BX_SMF BX_INSF_TYPE TEST_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1492 |
|
|
BX_SMF BX_INSF_TYPE TEST_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1493 |
|
|
BX_SMF BX_INSF_TYPE TEST_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1494 |
|
|
|
1495 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EbGbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1496 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1497 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1498 |
|
|
|
1499 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1500 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1501 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1502 |
|
|
|
1503 |
|
|
BX_SMF BX_INSF_TYPE MOV_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1504 |
|
|
BX_SMF BX_INSF_TYPE MOV_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1505 |
|
|
BX_SMF BX_INSF_TYPE MOV_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1506 |
|
|
BX_SMF BX_INSF_TYPE MOV_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1507 |
|
|
BX_SMF BX_INSF_TYPE MOV_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1508 |
|
|
BX_SMF BX_INSF_TYPE MOV_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1509 |
|
|
BX_SMF BX_INSF_TYPE MOV_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1510 |
|
|
|
1511 |
|
|
BX_SMF BX_INSF_TYPE MOV32_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1512 |
|
|
BX_SMF BX_INSF_TYPE MOV32_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1513 |
|
|
|
1514 |
|
|
BX_SMF BX_INSF_TYPE MOV32S_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1515 |
|
|
BX_SMF BX_INSF_TYPE MOV32S_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1516 |
|
|
|
1517 |
|
|
BX_SMF BX_INSF_TYPE MOV_EwSwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1518 |
|
|
BX_SMF BX_INSF_TYPE MOV_EwSwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1519 |
|
|
BX_SMF BX_INSF_TYPE MOV_SwEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1520 |
|
|
|
1521 |
|
|
BX_SMF BX_INSF_TYPE LEA_GdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1522 |
|
|
BX_SMF BX_INSF_TYPE LEA_GwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1523 |
|
|
|
1524 |
|
|
BX_SMF BX_INSF_TYPE CBW(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1525 |
|
|
BX_SMF BX_INSF_TYPE CWD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1526 |
|
|
BX_SMF BX_INSF_TYPE CALL32_Ap(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1527 |
|
|
BX_SMF BX_INSF_TYPE CALL16_Ap(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1528 |
|
|
BX_SMF BX_INSF_TYPE PUSHF_Fw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1529 |
|
|
BX_SMF BX_INSF_TYPE POPF_Fw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1530 |
|
|
BX_SMF BX_INSF_TYPE PUSHF_Fd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1531 |
|
|
BX_SMF BX_INSF_TYPE POPF_Fd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1532 |
|
|
BX_SMF BX_INSF_TYPE SAHF(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1533 |
|
|
BX_SMF BX_INSF_TYPE LAHF(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1534 |
|
|
|
1535 |
|
|
BX_SMF BX_INSF_TYPE MOV_ALOd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1536 |
|
|
BX_SMF BX_INSF_TYPE MOV_EAXOd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1537 |
|
|
BX_SMF BX_INSF_TYPE MOV_AXOd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1538 |
|
|
BX_SMF BX_INSF_TYPE MOV_OdAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1539 |
|
|
BX_SMF BX_INSF_TYPE MOV_OdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1540 |
|
|
BX_SMF BX_INSF_TYPE MOV_OdAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1541 |
|
|
|
1542 |
|
|
// repeatable instructions
|
1543 |
|
|
BX_SMF BX_INSF_TYPE REP_MOVSB_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1544 |
|
|
BX_SMF BX_INSF_TYPE REP_MOVSW_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1545 |
|
|
BX_SMF BX_INSF_TYPE REP_MOVSD_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1546 |
|
|
BX_SMF BX_INSF_TYPE REP_CMPSB_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1547 |
|
|
BX_SMF BX_INSF_TYPE REP_CMPSW_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1548 |
|
|
BX_SMF BX_INSF_TYPE REP_CMPSD_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1549 |
|
|
BX_SMF BX_INSF_TYPE REP_STOSB_YbAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1550 |
|
|
BX_SMF BX_INSF_TYPE REP_LODSB_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1551 |
|
|
BX_SMF BX_INSF_TYPE REP_SCASB_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1552 |
|
|
BX_SMF BX_INSF_TYPE REP_STOSW_YwAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1553 |
|
|
BX_SMF BX_INSF_TYPE REP_LODSW_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1554 |
|
|
BX_SMF BX_INSF_TYPE REP_SCASW_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1555 |
|
|
BX_SMF BX_INSF_TYPE REP_STOSD_YdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1556 |
|
|
BX_SMF BX_INSF_TYPE REP_LODSD_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1557 |
|
|
BX_SMF BX_INSF_TYPE REP_SCASD_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1558 |
|
|
|
1559 |
|
|
// qualified by address size
|
1560 |
|
|
BX_SMF void CMPSB16_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1561 |
|
|
BX_SMF void CMPSW16_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1562 |
|
|
BX_SMF void CMPSD16_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1563 |
|
|
BX_SMF void CMPSB32_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1564 |
|
|
BX_SMF void CMPSW32_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1565 |
|
|
BX_SMF void CMPSD32_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1566 |
|
|
|
1567 |
|
|
BX_SMF void SCASB16_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1568 |
|
|
BX_SMF void SCASW16_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1569 |
|
|
BX_SMF void SCASD16_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1570 |
|
|
BX_SMF void SCASB32_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1571 |
|
|
BX_SMF void SCASW32_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1572 |
|
|
BX_SMF void SCASD32_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1573 |
|
|
|
1574 |
|
|
BX_SMF void LODSB16_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1575 |
|
|
BX_SMF void LODSW16_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1576 |
|
|
BX_SMF void LODSD16_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1577 |
|
|
BX_SMF void LODSB32_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1578 |
|
|
BX_SMF void LODSW32_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1579 |
|
|
BX_SMF void LODSD32_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1580 |
|
|
|
1581 |
|
|
BX_SMF void STOSB16_YbAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1582 |
|
|
BX_SMF void STOSW16_YwAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1583 |
|
|
BX_SMF void STOSD16_YdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1584 |
|
|
BX_SMF void STOSB32_YbAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1585 |
|
|
BX_SMF void STOSW32_YwAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1586 |
|
|
BX_SMF void STOSD32_YdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1587 |
|
|
|
1588 |
|
|
BX_SMF void MOVSB16_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1589 |
|
|
BX_SMF void MOVSW16_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1590 |
|
|
BX_SMF void MOVSD16_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1591 |
|
|
BX_SMF void MOVSB32_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1592 |
|
|
BX_SMF void MOVSW32_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1593 |
|
|
BX_SMF void MOVSD32_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1594 |
|
|
|
1595 |
|
|
BX_SMF BX_INSF_TYPE MOV_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1596 |
|
|
BX_SMF BX_INSF_TYPE MOV_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1597 |
|
|
BX_SMF BX_INSF_TYPE MOV_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1598 |
|
|
|
1599 |
|
|
BX_SMF BX_INSF_TYPE ENTER16_IwIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1600 |
|
|
BX_SMF BX_INSF_TYPE ENTER32_IwIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1601 |
|
|
BX_SMF BX_INSF_TYPE LEAVE16(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1602 |
|
|
BX_SMF BX_INSF_TYPE LEAVE32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1603 |
|
|
|
1604 |
|
|
BX_SMF BX_INSF_TYPE INT1(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1605 |
|
|
BX_SMF BX_INSF_TYPE INT3(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1606 |
|
|
BX_SMF BX_INSF_TYPE INT_Ib(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1607 |
|
|
BX_SMF BX_INSF_TYPE INTO(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1608 |
|
|
BX_SMF BX_INSF_TYPE IRET32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1609 |
|
|
BX_SMF BX_INSF_TYPE IRET16(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1610 |
|
|
|
1611 |
|
|
BX_SMF BX_INSF_TYPE SALC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1612 |
|
|
BX_SMF BX_INSF_TYPE XLAT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1613 |
|
|
|
1614 |
|
|
BX_SMF BX_INSF_TYPE LOOPNE16_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1615 |
|
|
BX_SMF BX_INSF_TYPE LOOPE16_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1616 |
|
|
BX_SMF BX_INSF_TYPE LOOP16_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1617 |
|
|
BX_SMF BX_INSF_TYPE LOOPNE32_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1618 |
|
|
BX_SMF BX_INSF_TYPE LOOPE32_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1619 |
|
|
BX_SMF BX_INSF_TYPE LOOP32_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1620 |
|
|
BX_SMF BX_INSF_TYPE JCXZ_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1621 |
|
|
BX_SMF BX_INSF_TYPE JECXZ_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1622 |
|
|
BX_SMF BX_INSF_TYPE IN_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1623 |
|
|
BX_SMF BX_INSF_TYPE IN_AXIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1624 |
|
|
BX_SMF BX_INSF_TYPE IN_EAXIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1625 |
|
|
BX_SMF BX_INSF_TYPE OUT_IbAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1626 |
|
|
BX_SMF BX_INSF_TYPE OUT_IbAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1627 |
|
|
BX_SMF BX_INSF_TYPE OUT_IbEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1628 |
|
|
BX_SMF BX_INSF_TYPE CALL_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1629 |
|
|
BX_SMF BX_INSF_TYPE CALL_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1630 |
|
|
BX_SMF BX_INSF_TYPE JMP_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1631 |
|
|
BX_SMF BX_INSF_TYPE JMP_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1632 |
|
|
BX_SMF BX_INSF_TYPE JMP_Ap(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1633 |
|
|
BX_SMF BX_INSF_TYPE IN_ALDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1634 |
|
|
BX_SMF BX_INSF_TYPE IN_AXDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1635 |
|
|
BX_SMF BX_INSF_TYPE IN_EAXDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1636 |
|
|
BX_SMF BX_INSF_TYPE OUT_DXAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1637 |
|
|
BX_SMF BX_INSF_TYPE OUT_DXAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1638 |
|
|
BX_SMF BX_INSF_TYPE OUT_DXEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1639 |
|
|
|
1640 |
|
|
BX_SMF BX_INSF_TYPE HLT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1641 |
|
|
BX_SMF BX_INSF_TYPE CMC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1642 |
|
|
BX_SMF BX_INSF_TYPE CLC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1643 |
|
|
BX_SMF BX_INSF_TYPE STC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1644 |
|
|
BX_SMF BX_INSF_TYPE CLI(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1645 |
|
|
BX_SMF BX_INSF_TYPE STI(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1646 |
|
|
BX_SMF BX_INSF_TYPE CLD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1647 |
|
|
BX_SMF BX_INSF_TYPE STD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1648 |
|
|
|
1649 |
|
|
BX_SMF BX_INSF_TYPE LAR_GvEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1650 |
|
|
BX_SMF BX_INSF_TYPE LSL_GvEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1651 |
|
|
BX_SMF BX_INSF_TYPE CLTS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1652 |
|
|
BX_SMF BX_INSF_TYPE INVD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1653 |
|
|
BX_SMF BX_INSF_TYPE WBINVD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1654 |
|
|
BX_SMF BX_INSF_TYPE CLFLUSH(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1655 |
|
|
|
1656 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR0Rd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1657 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR2Rd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1658 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR3Rd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1659 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR4Rd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1660 |
|
|
BX_SMF BX_INSF_TYPE MOV_RdCR0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1661 |
|
|
BX_SMF BX_INSF_TYPE MOV_RdCR2(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1662 |
|
|
BX_SMF BX_INSF_TYPE MOV_RdCR3(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1663 |
|
|
BX_SMF BX_INSF_TYPE MOV_RdCR4(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1664 |
|
|
BX_SMF BX_INSF_TYPE MOV_DdRd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1665 |
|
|
BX_SMF BX_INSF_TYPE MOV_RdDd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1666 |
|
|
|
1667 |
|
|
BX_SMF BX_INSF_TYPE JO_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1668 |
|
|
BX_SMF BX_INSF_TYPE JNO_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1669 |
|
|
BX_SMF BX_INSF_TYPE JB_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1670 |
|
|
BX_SMF BX_INSF_TYPE JNB_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1671 |
|
|
BX_SMF BX_INSF_TYPE JZ_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1672 |
|
|
BX_SMF BX_INSF_TYPE JNZ_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1673 |
|
|
BX_SMF BX_INSF_TYPE JBE_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1674 |
|
|
BX_SMF BX_INSF_TYPE JNBE_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1675 |
|
|
BX_SMF BX_INSF_TYPE JS_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1676 |
|
|
BX_SMF BX_INSF_TYPE JNS_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1677 |
|
|
BX_SMF BX_INSF_TYPE JP_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1678 |
|
|
BX_SMF BX_INSF_TYPE JNP_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1679 |
|
|
BX_SMF BX_INSF_TYPE JL_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1680 |
|
|
BX_SMF BX_INSF_TYPE JNL_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1681 |
|
|
BX_SMF BX_INSF_TYPE JLE_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1682 |
|
|
BX_SMF BX_INSF_TYPE JNLE_Jw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1683 |
|
|
|
1684 |
|
|
BX_SMF BX_INSF_TYPE JO_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1685 |
|
|
BX_SMF BX_INSF_TYPE JNO_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1686 |
|
|
BX_SMF BX_INSF_TYPE JB_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1687 |
|
|
BX_SMF BX_INSF_TYPE JNB_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1688 |
|
|
BX_SMF BX_INSF_TYPE JZ_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1689 |
|
|
BX_SMF BX_INSF_TYPE JNZ_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1690 |
|
|
BX_SMF BX_INSF_TYPE JBE_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1691 |
|
|
BX_SMF BX_INSF_TYPE JNBE_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1692 |
|
|
BX_SMF BX_INSF_TYPE JS_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1693 |
|
|
BX_SMF BX_INSF_TYPE JNS_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1694 |
|
|
BX_SMF BX_INSF_TYPE JP_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1695 |
|
|
BX_SMF BX_INSF_TYPE JNP_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1696 |
|
|
BX_SMF BX_INSF_TYPE JL_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1697 |
|
|
BX_SMF BX_INSF_TYPE JNL_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1698 |
|
|
BX_SMF BX_INSF_TYPE JLE_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1699 |
|
|
BX_SMF BX_INSF_TYPE JNLE_Jd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1700 |
|
|
|
1701 |
|
|
BX_SMF BX_INSF_TYPE SETO_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1702 |
|
|
BX_SMF BX_INSF_TYPE SETNO_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1703 |
|
|
BX_SMF BX_INSF_TYPE SETB_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1704 |
|
|
BX_SMF BX_INSF_TYPE SETNB_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1705 |
|
|
BX_SMF BX_INSF_TYPE SETZ_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1706 |
|
|
BX_SMF BX_INSF_TYPE SETNZ_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1707 |
|
|
BX_SMF BX_INSF_TYPE SETBE_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1708 |
|
|
BX_SMF BX_INSF_TYPE SETNBE_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1709 |
|
|
BX_SMF BX_INSF_TYPE SETS_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1710 |
|
|
BX_SMF BX_INSF_TYPE SETNS_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1711 |
|
|
BX_SMF BX_INSF_TYPE SETP_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1712 |
|
|
BX_SMF BX_INSF_TYPE SETNP_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1713 |
|
|
BX_SMF BX_INSF_TYPE SETL_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1714 |
|
|
BX_SMF BX_INSF_TYPE SETNL_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1715 |
|
|
BX_SMF BX_INSF_TYPE SETLE_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1716 |
|
|
BX_SMF BX_INSF_TYPE SETNLE_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1717 |
|
|
|
1718 |
|
|
BX_SMF BX_INSF_TYPE SETO_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1719 |
|
|
BX_SMF BX_INSF_TYPE SETNO_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1720 |
|
|
BX_SMF BX_INSF_TYPE SETB_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1721 |
|
|
BX_SMF BX_INSF_TYPE SETNB_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1722 |
|
|
BX_SMF BX_INSF_TYPE SETZ_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1723 |
|
|
BX_SMF BX_INSF_TYPE SETNZ_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1724 |
|
|
BX_SMF BX_INSF_TYPE SETBE_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1725 |
|
|
BX_SMF BX_INSF_TYPE SETNBE_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1726 |
|
|
BX_SMF BX_INSF_TYPE SETS_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1727 |
|
|
BX_SMF BX_INSF_TYPE SETNS_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1728 |
|
|
BX_SMF BX_INSF_TYPE SETP_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1729 |
|
|
BX_SMF BX_INSF_TYPE SETNP_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1730 |
|
|
BX_SMF BX_INSF_TYPE SETL_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1731 |
|
|
BX_SMF BX_INSF_TYPE SETNL_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1732 |
|
|
BX_SMF BX_INSF_TYPE SETLE_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1733 |
|
|
BX_SMF BX_INSF_TYPE SETNLE_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1734 |
|
|
|
1735 |
|
|
BX_SMF BX_INSF_TYPE CPUID(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1736 |
|
|
|
1737 |
|
|
BX_SMF BX_INSF_TYPE SHRD_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1738 |
|
|
BX_SMF BX_INSF_TYPE SHRD_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1739 |
|
|
BX_SMF BX_INSF_TYPE SHLD_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1740 |
|
|
BX_SMF BX_INSF_TYPE SHLD_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1741 |
|
|
BX_SMF BX_INSF_TYPE SHRD_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1742 |
|
|
BX_SMF BX_INSF_TYPE SHRD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1743 |
|
|
BX_SMF BX_INSF_TYPE SHLD_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1744 |
|
|
BX_SMF BX_INSF_TYPE SHLD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1745 |
|
|
|
1746 |
|
|
BX_SMF BX_INSF_TYPE BSF_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1747 |
|
|
BX_SMF BX_INSF_TYPE BSF_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1748 |
|
|
BX_SMF BX_INSF_TYPE BSR_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1749 |
|
|
BX_SMF BX_INSF_TYPE BSR_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1750 |
|
|
|
1751 |
|
|
BX_SMF BX_INSF_TYPE BT_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1752 |
|
|
BX_SMF BX_INSF_TYPE BT_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1753 |
|
|
BX_SMF BX_INSF_TYPE BTS_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1754 |
|
|
BX_SMF BX_INSF_TYPE BTS_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1755 |
|
|
BX_SMF BX_INSF_TYPE BTR_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1756 |
|
|
BX_SMF BX_INSF_TYPE BTR_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1757 |
|
|
BX_SMF BX_INSF_TYPE BTC_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1758 |
|
|
BX_SMF BX_INSF_TYPE BTC_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1759 |
|
|
|
1760 |
|
|
BX_SMF BX_INSF_TYPE BT_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1761 |
|
|
BX_SMF BX_INSF_TYPE BT_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1762 |
|
|
BX_SMF BX_INSF_TYPE BTS_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1763 |
|
|
BX_SMF BX_INSF_TYPE BTS_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1764 |
|
|
BX_SMF BX_INSF_TYPE BTR_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1765 |
|
|
BX_SMF BX_INSF_TYPE BTR_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1766 |
|
|
BX_SMF BX_INSF_TYPE BTC_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1767 |
|
|
BX_SMF BX_INSF_TYPE BTC_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1768 |
|
|
|
1769 |
|
|
BX_SMF BX_INSF_TYPE BT_EwIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1770 |
|
|
BX_SMF BX_INSF_TYPE BT_EdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1771 |
|
|
BX_SMF BX_INSF_TYPE BTS_EwIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1772 |
|
|
BX_SMF BX_INSF_TYPE BTS_EdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1773 |
|
|
BX_SMF BX_INSF_TYPE BTR_EwIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1774 |
|
|
BX_SMF BX_INSF_TYPE BTR_EdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1775 |
|
|
BX_SMF BX_INSF_TYPE BTC_EwIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1776 |
|
|
BX_SMF BX_INSF_TYPE BTC_EdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1777 |
|
|
|
1778 |
|
|
BX_SMF BX_INSF_TYPE BT_EwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1779 |
|
|
BX_SMF BX_INSF_TYPE BT_EdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1780 |
|
|
BX_SMF BX_INSF_TYPE BTS_EwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1781 |
|
|
BX_SMF BX_INSF_TYPE BTS_EdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1782 |
|
|
BX_SMF BX_INSF_TYPE BTR_EwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1783 |
|
|
BX_SMF BX_INSF_TYPE BTR_EdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1784 |
|
|
BX_SMF BX_INSF_TYPE BTC_EwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1785 |
|
|
BX_SMF BX_INSF_TYPE BTC_EdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1786 |
|
|
|
1787 |
|
|
BX_SMF BX_INSF_TYPE LES_GwMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1788 |
|
|
BX_SMF BX_INSF_TYPE LDS_GwMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1789 |
|
|
BX_SMF BX_INSF_TYPE LSS_GwMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1790 |
|
|
BX_SMF BX_INSF_TYPE LFS_GwMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1791 |
|
|
BX_SMF BX_INSF_TYPE LGS_GwMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1792 |
|
|
BX_SMF BX_INSF_TYPE LES_GdMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1793 |
|
|
BX_SMF BX_INSF_TYPE LDS_GdMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1794 |
|
|
BX_SMF BX_INSF_TYPE LSS_GdMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1795 |
|
|
BX_SMF BX_INSF_TYPE LFS_GdMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1796 |
|
|
BX_SMF BX_INSF_TYPE LGS_GdMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1797 |
|
|
|
1798 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GwEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1799 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GdEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1800 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GdEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1801 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GwEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1802 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GdEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1803 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GdEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1804 |
|
|
|
1805 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GwEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1806 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GdEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1807 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GdEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1808 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GwEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1809 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GdEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1810 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GdEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1811 |
|
|
|
1812 |
|
|
BX_SMF BX_INSF_TYPE BSWAP_RX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1813 |
|
|
BX_SMF BX_INSF_TYPE BSWAP_ERX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1814 |
|
|
|
1815 |
|
|
BX_SMF BX_INSF_TYPE ADD_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1816 |
|
|
BX_SMF BX_INSF_TYPE OR_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1817 |
|
|
BX_SMF BX_INSF_TYPE ADC_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1818 |
|
|
BX_SMF BX_INSF_TYPE SBB_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1819 |
|
|
BX_SMF BX_INSF_TYPE AND_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1820 |
|
|
BX_SMF BX_INSF_TYPE SUB_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1821 |
|
|
BX_SMF BX_INSF_TYPE XOR_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1822 |
|
|
BX_SMF BX_INSF_TYPE CMP_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1823 |
|
|
|
1824 |
|
|
BX_SMF BX_INSF_TYPE ADD_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1825 |
|
|
BX_SMF BX_INSF_TYPE OR_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1826 |
|
|
BX_SMF BX_INSF_TYPE ADC_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1827 |
|
|
BX_SMF BX_INSF_TYPE SBB_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1828 |
|
|
BX_SMF BX_INSF_TYPE AND_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1829 |
|
|
BX_SMF BX_INSF_TYPE SUB_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1830 |
|
|
BX_SMF BX_INSF_TYPE XOR_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1831 |
|
|
BX_SMF BX_INSF_TYPE CMP_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1832 |
|
|
|
1833 |
|
|
BX_SMF BX_INSF_TYPE ADD_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1834 |
|
|
BX_SMF BX_INSF_TYPE OR_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1835 |
|
|
BX_SMF BX_INSF_TYPE ADC_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1836 |
|
|
BX_SMF BX_INSF_TYPE SBB_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1837 |
|
|
BX_SMF BX_INSF_TYPE AND_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1838 |
|
|
BX_SMF BX_INSF_TYPE SUB_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1839 |
|
|
BX_SMF BX_INSF_TYPE XOR_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1840 |
|
|
BX_SMF BX_INSF_TYPE CMP_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1841 |
|
|
|
1842 |
|
|
BX_SMF BX_INSF_TYPE ADD_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1843 |
|
|
BX_SMF BX_INSF_TYPE OR_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1844 |
|
|
BX_SMF BX_INSF_TYPE ADC_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1845 |
|
|
BX_SMF BX_INSF_TYPE SBB_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1846 |
|
|
BX_SMF BX_INSF_TYPE AND_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1847 |
|
|
BX_SMF BX_INSF_TYPE SUB_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1848 |
|
|
BX_SMF BX_INSF_TYPE XOR_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1849 |
|
|
BX_SMF BX_INSF_TYPE CMP_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1850 |
|
|
|
1851 |
|
|
BX_SMF BX_INSF_TYPE ADD_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1852 |
|
|
BX_SMF BX_INSF_TYPE OR_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1853 |
|
|
BX_SMF BX_INSF_TYPE ADC_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1854 |
|
|
BX_SMF BX_INSF_TYPE SBB_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1855 |
|
|
BX_SMF BX_INSF_TYPE AND_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1856 |
|
|
BX_SMF BX_INSF_TYPE SUB_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1857 |
|
|
BX_SMF BX_INSF_TYPE XOR_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1858 |
|
|
BX_SMF BX_INSF_TYPE CMP_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1859 |
|
|
|
1860 |
|
|
BX_SMF BX_INSF_TYPE ADD_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1861 |
|
|
BX_SMF BX_INSF_TYPE OR_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1862 |
|
|
BX_SMF BX_INSF_TYPE ADC_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1863 |
|
|
BX_SMF BX_INSF_TYPE SBB_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1864 |
|
|
BX_SMF BX_INSF_TYPE AND_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1865 |
|
|
BX_SMF BX_INSF_TYPE SUB_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1866 |
|
|
BX_SMF BX_INSF_TYPE XOR_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1867 |
|
|
BX_SMF BX_INSF_TYPE CMP_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1868 |
|
|
|
1869 |
|
|
BX_SMF BX_INSF_TYPE ADD_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1870 |
|
|
BX_SMF BX_INSF_TYPE OR_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1871 |
|
|
BX_SMF BX_INSF_TYPE ADC_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1872 |
|
|
BX_SMF BX_INSF_TYPE SBB_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1873 |
|
|
BX_SMF BX_INSF_TYPE AND_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1874 |
|
|
BX_SMF BX_INSF_TYPE SUB_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1875 |
|
|
BX_SMF BX_INSF_TYPE XOR_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1876 |
|
|
BX_SMF BX_INSF_TYPE CMP_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1877 |
|
|
|
1878 |
|
|
BX_SMF BX_INSF_TYPE ADD_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1879 |
|
|
BX_SMF BX_INSF_TYPE OR_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1880 |
|
|
BX_SMF BX_INSF_TYPE ADC_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1881 |
|
|
BX_SMF BX_INSF_TYPE SBB_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1882 |
|
|
BX_SMF BX_INSF_TYPE AND_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1883 |
|
|
BX_SMF BX_INSF_TYPE SUB_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1884 |
|
|
BX_SMF BX_INSF_TYPE XOR_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1885 |
|
|
BX_SMF BX_INSF_TYPE CMP_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1886 |
|
|
|
1887 |
|
|
BX_SMF BX_INSF_TYPE ADD_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1888 |
|
|
BX_SMF BX_INSF_TYPE OR_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1889 |
|
|
BX_SMF BX_INSF_TYPE ADC_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1890 |
|
|
BX_SMF BX_INSF_TYPE SBB_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1891 |
|
|
BX_SMF BX_INSF_TYPE AND_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1892 |
|
|
BX_SMF BX_INSF_TYPE SUB_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1893 |
|
|
BX_SMF BX_INSF_TYPE XOR_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1894 |
|
|
BX_SMF BX_INSF_TYPE CMP_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1895 |
|
|
|
1896 |
|
|
BX_SMF BX_INSF_TYPE ADD_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1897 |
|
|
BX_SMF BX_INSF_TYPE OR_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1898 |
|
|
BX_SMF BX_INSF_TYPE ADC_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1899 |
|
|
BX_SMF BX_INSF_TYPE SBB_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1900 |
|
|
BX_SMF BX_INSF_TYPE AND_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1901 |
|
|
BX_SMF BX_INSF_TYPE SUB_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1902 |
|
|
BX_SMF BX_INSF_TYPE XOR_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1903 |
|
|
BX_SMF BX_INSF_TYPE CMP_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1904 |
|
|
|
1905 |
|
|
BX_SMF BX_INSF_TYPE ADD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1906 |
|
|
BX_SMF BX_INSF_TYPE OR_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1907 |
|
|
BX_SMF BX_INSF_TYPE ADC_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1908 |
|
|
BX_SMF BX_INSF_TYPE SBB_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1909 |
|
|
BX_SMF BX_INSF_TYPE AND_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1910 |
|
|
BX_SMF BX_INSF_TYPE SUB_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1911 |
|
|
BX_SMF BX_INSF_TYPE XOR_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1912 |
|
|
BX_SMF BX_INSF_TYPE CMP_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1913 |
|
|
|
1914 |
|
|
BX_SMF BX_INSF_TYPE ADD_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1915 |
|
|
BX_SMF BX_INSF_TYPE OR_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1916 |
|
|
BX_SMF BX_INSF_TYPE ADC_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1917 |
|
|
BX_SMF BX_INSF_TYPE SBB_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1918 |
|
|
BX_SMF BX_INSF_TYPE AND_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1919 |
|
|
BX_SMF BX_INSF_TYPE SUB_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1920 |
|
|
BX_SMF BX_INSF_TYPE XOR_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1921 |
|
|
BX_SMF BX_INSF_TYPE CMP_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1922 |
|
|
|
1923 |
|
|
BX_SMF BX_INSF_TYPE ADD_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1924 |
|
|
BX_SMF BX_INSF_TYPE OR_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1925 |
|
|
BX_SMF BX_INSF_TYPE ADC_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1926 |
|
|
BX_SMF BX_INSF_TYPE SBB_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1927 |
|
|
BX_SMF BX_INSF_TYPE AND_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1928 |
|
|
BX_SMF BX_INSF_TYPE SUB_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1929 |
|
|
BX_SMF BX_INSF_TYPE XOR_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1930 |
|
|
BX_SMF BX_INSF_TYPE CMP_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1931 |
|
|
|
1932 |
|
|
BX_SMF BX_INSF_TYPE ADD_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1933 |
|
|
BX_SMF BX_INSF_TYPE OR_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1934 |
|
|
BX_SMF BX_INSF_TYPE ADC_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1935 |
|
|
BX_SMF BX_INSF_TYPE SBB_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1936 |
|
|
BX_SMF BX_INSF_TYPE AND_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1937 |
|
|
BX_SMF BX_INSF_TYPE SUB_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1938 |
|
|
BX_SMF BX_INSF_TYPE CMP_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1939 |
|
|
BX_SMF BX_INSF_TYPE XOR_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1940 |
|
|
|
1941 |
|
|
BX_SMF BX_INSF_TYPE ADD_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1942 |
|
|
BX_SMF BX_INSF_TYPE OR_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1943 |
|
|
BX_SMF BX_INSF_TYPE ADC_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1944 |
|
|
BX_SMF BX_INSF_TYPE SBB_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1945 |
|
|
BX_SMF BX_INSF_TYPE AND_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1946 |
|
|
BX_SMF BX_INSF_TYPE SUB_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1947 |
|
|
BX_SMF BX_INSF_TYPE CMP_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1948 |
|
|
BX_SMF BX_INSF_TYPE XOR_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1949 |
|
|
|
1950 |
|
|
BX_SMF BX_INSF_TYPE NOT_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1951 |
|
|
BX_SMF BX_INSF_TYPE NOT_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1952 |
|
|
BX_SMF BX_INSF_TYPE NOT_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1953 |
|
|
|
1954 |
|
|
BX_SMF BX_INSF_TYPE NOT_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1955 |
|
|
BX_SMF BX_INSF_TYPE NOT_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1956 |
|
|
BX_SMF BX_INSF_TYPE NOT_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1957 |
|
|
|
1958 |
|
|
BX_SMF BX_INSF_TYPE NEG_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1959 |
|
|
BX_SMF BX_INSF_TYPE NEG_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1960 |
|
|
BX_SMF BX_INSF_TYPE NEG_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1961 |
|
|
|
1962 |
|
|
BX_SMF BX_INSF_TYPE NEG_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1963 |
|
|
BX_SMF BX_INSF_TYPE NEG_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1964 |
|
|
BX_SMF BX_INSF_TYPE NEG_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1965 |
|
|
|
1966 |
|
|
BX_SMF BX_INSF_TYPE ROL_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1967 |
|
|
BX_SMF BX_INSF_TYPE ROR_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1968 |
|
|
BX_SMF BX_INSF_TYPE RCL_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1969 |
|
|
BX_SMF BX_INSF_TYPE RCR_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1970 |
|
|
BX_SMF BX_INSF_TYPE SHL_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1971 |
|
|
BX_SMF BX_INSF_TYPE SHR_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1972 |
|
|
BX_SMF BX_INSF_TYPE SAR_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1973 |
|
|
|
1974 |
|
|
BX_SMF BX_INSF_TYPE ROL_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1975 |
|
|
BX_SMF BX_INSF_TYPE ROR_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1976 |
|
|
BX_SMF BX_INSF_TYPE RCL_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1977 |
|
|
BX_SMF BX_INSF_TYPE RCR_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1978 |
|
|
BX_SMF BX_INSF_TYPE SHL_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1979 |
|
|
BX_SMF BX_INSF_TYPE SHR_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1980 |
|
|
BX_SMF BX_INSF_TYPE SAR_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1981 |
|
|
|
1982 |
|
|
BX_SMF BX_INSF_TYPE ROL_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1983 |
|
|
BX_SMF BX_INSF_TYPE ROR_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1984 |
|
|
BX_SMF BX_INSF_TYPE RCL_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1985 |
|
|
BX_SMF BX_INSF_TYPE RCR_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1986 |
|
|
BX_SMF BX_INSF_TYPE SHL_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1987 |
|
|
BX_SMF BX_INSF_TYPE SHR_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1988 |
|
|
BX_SMF BX_INSF_TYPE SAR_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1989 |
|
|
|
1990 |
|
|
BX_SMF BX_INSF_TYPE ROL_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1991 |
|
|
BX_SMF BX_INSF_TYPE ROR_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1992 |
|
|
BX_SMF BX_INSF_TYPE RCL_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1993 |
|
|
BX_SMF BX_INSF_TYPE RCR_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1994 |
|
|
BX_SMF BX_INSF_TYPE SHL_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1995 |
|
|
BX_SMF BX_INSF_TYPE SHR_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1996 |
|
|
BX_SMF BX_INSF_TYPE SAR_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1997 |
|
|
|
1998 |
|
|
BX_SMF BX_INSF_TYPE ROL_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
1999 |
|
|
BX_SMF BX_INSF_TYPE ROR_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2000 |
|
|
BX_SMF BX_INSF_TYPE RCL_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2001 |
|
|
BX_SMF BX_INSF_TYPE RCR_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2002 |
|
|
BX_SMF BX_INSF_TYPE SHL_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2003 |
|
|
BX_SMF BX_INSF_TYPE SHR_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2004 |
|
|
BX_SMF BX_INSF_TYPE SAR_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2005 |
|
|
|
2006 |
|
|
BX_SMF BX_INSF_TYPE ROL_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2007 |
|
|
BX_SMF BX_INSF_TYPE ROR_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2008 |
|
|
BX_SMF BX_INSF_TYPE RCL_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2009 |
|
|
BX_SMF BX_INSF_TYPE RCR_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2010 |
|
|
BX_SMF BX_INSF_TYPE SHL_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2011 |
|
|
BX_SMF BX_INSF_TYPE SHR_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2012 |
|
|
BX_SMF BX_INSF_TYPE SAR_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2013 |
|
|
|
2014 |
|
|
BX_SMF BX_INSF_TYPE TEST_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2015 |
|
|
BX_SMF BX_INSF_TYPE TEST_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2016 |
|
|
BX_SMF BX_INSF_TYPE TEST_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2017 |
|
|
|
2018 |
|
|
BX_SMF BX_INSF_TYPE TEST_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2019 |
|
|
BX_SMF BX_INSF_TYPE TEST_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2020 |
|
|
BX_SMF BX_INSF_TYPE TEST_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2021 |
|
|
|
2022 |
|
|
BX_SMF BX_INSF_TYPE IMUL_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2023 |
|
|
BX_SMF BX_INSF_TYPE IMUL_GdEdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2024 |
|
|
|
2025 |
|
|
BX_SMF BX_INSF_TYPE MUL_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2026 |
|
|
BX_SMF BX_INSF_TYPE IMUL_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2027 |
|
|
BX_SMF BX_INSF_TYPE DIV_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2028 |
|
|
BX_SMF BX_INSF_TYPE IDIV_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2029 |
|
|
|
2030 |
|
|
BX_SMF BX_INSF_TYPE MUL_EAXEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2031 |
|
|
BX_SMF BX_INSF_TYPE IMUL_EAXEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2032 |
|
|
BX_SMF BX_INSF_TYPE DIV_EAXEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2033 |
|
|
BX_SMF BX_INSF_TYPE IDIV_EAXEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2034 |
|
|
|
2035 |
|
|
BX_SMF BX_INSF_TYPE INC_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2036 |
|
|
BX_SMF BX_INSF_TYPE DEC_EbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2037 |
|
|
|
2038 |
|
|
BX_SMF BX_INSF_TYPE INC_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2039 |
|
|
BX_SMF BX_INSF_TYPE INC_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2040 |
|
|
BX_SMF BX_INSF_TYPE INC_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2041 |
|
|
BX_SMF BX_INSF_TYPE DEC_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2042 |
|
|
BX_SMF BX_INSF_TYPE DEC_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2043 |
|
|
BX_SMF BX_INSF_TYPE DEC_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2044 |
|
|
|
2045 |
|
|
BX_SMF BX_INSF_TYPE CALL_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2046 |
|
|
BX_SMF BX_INSF_TYPE CALL_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2047 |
|
|
|
2048 |
|
|
BX_SMF BX_INSF_TYPE CALL32_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2049 |
|
|
BX_SMF BX_INSF_TYPE CALL16_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2050 |
|
|
BX_SMF BX_INSF_TYPE JMP32_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2051 |
|
|
BX_SMF BX_INSF_TYPE JMP16_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2052 |
|
|
|
2053 |
|
|
BX_SMF BX_INSF_TYPE JMP_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2054 |
|
|
BX_SMF BX_INSF_TYPE JMP_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2055 |
|
|
|
2056 |
|
|
BX_SMF BX_INSF_TYPE SLDT_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2057 |
|
|
BX_SMF BX_INSF_TYPE STR_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2058 |
|
|
BX_SMF BX_INSF_TYPE LLDT_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2059 |
|
|
BX_SMF BX_INSF_TYPE LTR_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2060 |
|
|
BX_SMF BX_INSF_TYPE VERR_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2061 |
|
|
BX_SMF BX_INSF_TYPE VERW_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2062 |
|
|
|
2063 |
|
|
BX_SMF BX_INSF_TYPE SGDT_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2064 |
|
|
BX_SMF BX_INSF_TYPE SIDT_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2065 |
|
|
BX_SMF BX_INSF_TYPE LGDT_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2066 |
|
|
BX_SMF BX_INSF_TYPE LIDT_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2067 |
|
|
BX_SMF BX_INSF_TYPE SMSW_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2068 |
|
|
BX_SMF BX_INSF_TYPE SMSW_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2069 |
|
|
BX_SMF BX_INSF_TYPE LMSW_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2070 |
|
|
|
2071 |
|
|
// LOAD methods
|
2072 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Eb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2073 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2074 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2075 |
|
|
#if BX_SUPPORT_X86_64
|
2076 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2077 |
|
|
#endif
|
2078 |
|
|
BX_SMF BX_INSF_TYPE LOADU_Wdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2079 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Wdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2080 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Wss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2081 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Wsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2082 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Ww(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2083 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Wb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2084 |
|
|
#if BX_SUPPORT_AVX
|
2085 |
|
|
BX_SMF BX_INSF_TYPE LOAD_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2086 |
|
|
#endif
|
2087 |
|
|
|
2088 |
|
|
#if BX_SUPPORT_FPU == 0 // if FPU is disabled
|
2089 |
|
|
BX_SMF BX_INSF_TYPE FPU_ESC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2090 |
|
|
#endif
|
2091 |
|
|
|
2092 |
|
|
BX_SMF BX_INSF_TYPE FWAIT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2093 |
|
|
|
2094 |
|
|
#if BX_SUPPORT_FPU
|
2095 |
|
|
// load/store
|
2096 |
|
|
BX_SMF BX_INSF_TYPE FLD_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2097 |
|
|
BX_SMF BX_INSF_TYPE FLD_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2098 |
|
|
BX_SMF BX_INSF_TYPE FLD_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2099 |
|
|
BX_SMF BX_INSF_TYPE FLD_EXTENDED_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2100 |
|
|
BX_SMF BX_INSF_TYPE FILD_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2101 |
|
|
BX_SMF BX_INSF_TYPE FILD_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2102 |
|
|
BX_SMF BX_INSF_TYPE FILD_QWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2103 |
|
|
BX_SMF BX_INSF_TYPE FBLD_PACKED_BCD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2104 |
|
|
|
2105 |
|
|
BX_SMF BX_INSF_TYPE FST_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2106 |
|
|
BX_SMF BX_INSF_TYPE FST_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2107 |
|
|
BX_SMF BX_INSF_TYPE FST_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2108 |
|
|
BX_SMF BX_INSF_TYPE FSTP_EXTENDED_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2109 |
|
|
BX_SMF BX_INSF_TYPE FIST_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2110 |
|
|
BX_SMF BX_INSF_TYPE FIST_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2111 |
|
|
BX_SMF BX_INSF_TYPE FISTP_QWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2112 |
|
|
BX_SMF BX_INSF_TYPE FBSTP_PACKED_BCD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2113 |
|
|
|
2114 |
|
|
BX_SMF BX_INSF_TYPE FISTTP16(bxInstruction_c *) BX_CPP_AttrRegparmN(1); // SSE3
|
2115 |
|
|
BX_SMF BX_INSF_TYPE FISTTP32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2116 |
|
|
BX_SMF BX_INSF_TYPE FISTTP64(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2117 |
|
|
|
2118 |
|
|
// control
|
2119 |
|
|
BX_SMF BX_INSF_TYPE FNINIT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2120 |
|
|
BX_SMF BX_INSF_TYPE FNCLEX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2121 |
|
|
|
2122 |
|
|
BX_SMF BX_INSF_TYPE FRSTOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2123 |
|
|
BX_SMF BX_INSF_TYPE FNSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2124 |
|
|
BX_SMF BX_INSF_TYPE FLDENV(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2125 |
|
|
BX_SMF BX_INSF_TYPE FNSTENV(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2126 |
|
|
|
2127 |
|
|
BX_SMF BX_INSF_TYPE FLDCW(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2128 |
|
|
BX_SMF BX_INSF_TYPE FNSTCW(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2129 |
|
|
BX_SMF BX_INSF_TYPE FNSTSW(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2130 |
|
|
BX_SMF BX_INSF_TYPE FNSTSW_AX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2131 |
|
|
|
2132 |
|
|
// const
|
2133 |
|
|
BX_SMF BX_INSF_TYPE FLD1(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2134 |
|
|
BX_SMF BX_INSF_TYPE FLDL2T(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2135 |
|
|
BX_SMF BX_INSF_TYPE FLDL2E(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2136 |
|
|
BX_SMF BX_INSF_TYPE FLDPI(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2137 |
|
|
BX_SMF BX_INSF_TYPE FLDLG2(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2138 |
|
|
BX_SMF BX_INSF_TYPE FLDLN2(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2139 |
|
|
BX_SMF BX_INSF_TYPE FLDZ(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2140 |
|
|
|
2141 |
|
|
// add
|
2142 |
|
|
BX_SMF BX_INSF_TYPE FADD_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2143 |
|
|
BX_SMF BX_INSF_TYPE FADD_STi_ST0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2144 |
|
|
BX_SMF BX_INSF_TYPE FADD_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2145 |
|
|
BX_SMF BX_INSF_TYPE FADD_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2146 |
|
|
BX_SMF BX_INSF_TYPE FIADD_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2147 |
|
|
BX_SMF BX_INSF_TYPE FIADD_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2148 |
|
|
|
2149 |
|
|
// mul
|
2150 |
|
|
BX_SMF BX_INSF_TYPE FMUL_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2151 |
|
|
BX_SMF BX_INSF_TYPE FMUL_STi_ST0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2152 |
|
|
BX_SMF BX_INSF_TYPE FMUL_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2153 |
|
|
BX_SMF BX_INSF_TYPE FMUL_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2154 |
|
|
BX_SMF BX_INSF_TYPE FIMUL_WORD_INTEGER (bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2155 |
|
|
BX_SMF BX_INSF_TYPE FIMUL_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2156 |
|
|
|
2157 |
|
|
// sub
|
2158 |
|
|
BX_SMF BX_INSF_TYPE FSUB_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2159 |
|
|
BX_SMF BX_INSF_TYPE FSUBR_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2160 |
|
|
BX_SMF BX_INSF_TYPE FSUB_STi_ST0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2161 |
|
|
BX_SMF BX_INSF_TYPE FSUBR_STi_ST0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2162 |
|
|
BX_SMF BX_INSF_TYPE FSUB_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2163 |
|
|
BX_SMF BX_INSF_TYPE FSUBR_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2164 |
|
|
BX_SMF BX_INSF_TYPE FSUB_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2165 |
|
|
BX_SMF BX_INSF_TYPE FSUBR_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2166 |
|
|
|
2167 |
|
|
BX_SMF BX_INSF_TYPE FISUB_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2168 |
|
|
BX_SMF BX_INSF_TYPE FISUBR_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2169 |
|
|
BX_SMF BX_INSF_TYPE FISUB_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2170 |
|
|
BX_SMF BX_INSF_TYPE FISUBR_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2171 |
|
|
|
2172 |
|
|
// div
|
2173 |
|
|
BX_SMF BX_INSF_TYPE FDIV_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2174 |
|
|
BX_SMF BX_INSF_TYPE FDIVR_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2175 |
|
|
BX_SMF BX_INSF_TYPE FDIV_STi_ST0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2176 |
|
|
BX_SMF BX_INSF_TYPE FDIVR_STi_ST0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2177 |
|
|
BX_SMF BX_INSF_TYPE FDIV_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2178 |
|
|
BX_SMF BX_INSF_TYPE FDIVR_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2179 |
|
|
BX_SMF BX_INSF_TYPE FDIV_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2180 |
|
|
BX_SMF BX_INSF_TYPE FDIVR_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2181 |
|
|
|
2182 |
|
|
BX_SMF BX_INSF_TYPE FIDIV_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2183 |
|
|
BX_SMF BX_INSF_TYPE FIDIVR_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2184 |
|
|
BX_SMF BX_INSF_TYPE FIDIV_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2185 |
|
|
BX_SMF BX_INSF_TYPE FIDIVR_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2186 |
|
|
|
2187 |
|
|
// compare
|
2188 |
|
|
BX_SMF BX_INSF_TYPE FCOM_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2189 |
|
|
BX_SMF BX_INSF_TYPE FUCOM_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2190 |
|
|
BX_SMF BX_INSF_TYPE FCOMI_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2191 |
|
|
BX_SMF BX_INSF_TYPE FUCOMI_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2192 |
|
|
BX_SMF BX_INSF_TYPE FCOM_SINGLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2193 |
|
|
BX_SMF BX_INSF_TYPE FCOM_DOUBLE_REAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2194 |
|
|
BX_SMF BX_INSF_TYPE FICOM_WORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2195 |
|
|
BX_SMF BX_INSF_TYPE FICOM_DWORD_INTEGER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2196 |
|
|
|
2197 |
|
|
BX_SMF BX_INSF_TYPE FCOMPP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2198 |
|
|
BX_SMF BX_INSF_TYPE FUCOMPP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2199 |
|
|
|
2200 |
|
|
BX_SMF BX_INSF_TYPE FCMOVB_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2201 |
|
|
BX_SMF BX_INSF_TYPE FCMOVE_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2202 |
|
|
BX_SMF BX_INSF_TYPE FCMOVBE_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2203 |
|
|
BX_SMF BX_INSF_TYPE FCMOVU_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2204 |
|
|
BX_SMF BX_INSF_TYPE FCMOVNB_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2205 |
|
|
BX_SMF BX_INSF_TYPE FCMOVNE_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2206 |
|
|
BX_SMF BX_INSF_TYPE FCMOVNBE_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2207 |
|
|
BX_SMF BX_INSF_TYPE FCMOVNU_ST0_STj(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2208 |
|
|
|
2209 |
|
|
// misc
|
2210 |
|
|
BX_SMF BX_INSF_TYPE FXCH_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2211 |
|
|
BX_SMF BX_INSF_TYPE FNOP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2212 |
|
|
BX_SMF BX_INSF_TYPE FPLEGACY(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2213 |
|
|
BX_SMF BX_INSF_TYPE FCHS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2214 |
|
|
BX_SMF BX_INSF_TYPE FABS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2215 |
|
|
BX_SMF BX_INSF_TYPE FTST(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2216 |
|
|
BX_SMF BX_INSF_TYPE FXAM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2217 |
|
|
BX_SMF BX_INSF_TYPE FDECSTP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2218 |
|
|
BX_SMF BX_INSF_TYPE FINCSTP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2219 |
|
|
BX_SMF BX_INSF_TYPE FFREE_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2220 |
|
|
BX_SMF BX_INSF_TYPE FFREEP_STi(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2221 |
|
|
|
2222 |
|
|
BX_SMF BX_INSF_TYPE F2XM1(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2223 |
|
|
BX_SMF BX_INSF_TYPE FYL2X(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2224 |
|
|
BX_SMF BX_INSF_TYPE FPTAN(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2225 |
|
|
BX_SMF BX_INSF_TYPE FPATAN(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2226 |
|
|
BX_SMF BX_INSF_TYPE FXTRACT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2227 |
|
|
BX_SMF BX_INSF_TYPE FPREM1(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2228 |
|
|
BX_SMF BX_INSF_TYPE FPREM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2229 |
|
|
BX_SMF BX_INSF_TYPE FYL2XP1(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2230 |
|
|
BX_SMF BX_INSF_TYPE FSQRT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2231 |
|
|
BX_SMF BX_INSF_TYPE FSINCOS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2232 |
|
|
BX_SMF BX_INSF_TYPE FRNDINT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2233 |
|
|
#undef FSCALE // <sys/param.h> is #included on Mac OS X from bochs.h
|
2234 |
|
|
BX_SMF BX_INSF_TYPE FSCALE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2235 |
|
|
BX_SMF BX_INSF_TYPE FSIN(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2236 |
|
|
BX_SMF BX_INSF_TYPE FCOS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2237 |
|
|
#endif
|
2238 |
|
|
|
2239 |
|
|
/* MMX */
|
2240 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKLBW_PqQd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2241 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKLWD_PqQd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2242 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKLDQ_PqQd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2243 |
|
|
BX_SMF BX_INSF_TYPE PACKSSWB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2244 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2245 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2246 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2247 |
|
|
BX_SMF BX_INSF_TYPE PACKUSWB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2248 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKHBW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2249 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKHWD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2250 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKHDQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2251 |
|
|
BX_SMF BX_INSF_TYPE PACKSSDW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2252 |
|
|
BX_SMF BX_INSF_TYPE MOVD_PqEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2253 |
|
|
BX_SMF BX_INSF_TYPE MOVD_PqEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2254 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_PqQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2255 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_PqQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2256 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2257 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2258 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2259 |
|
|
BX_SMF BX_INSF_TYPE EMMS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2260 |
|
|
BX_SMF BX_INSF_TYPE MOVD_EdPdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2261 |
|
|
BX_SMF BX_INSF_TYPE MOVD_EdPdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2262 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_QqPqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2263 |
|
|
BX_SMF BX_INSF_TYPE PSRLW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2264 |
|
|
BX_SMF BX_INSF_TYPE PSRLD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2265 |
|
|
BX_SMF BX_INSF_TYPE PSRLQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2266 |
|
|
BX_SMF BX_INSF_TYPE PMULLW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2267 |
|
|
BX_SMF BX_INSF_TYPE PSUBUSB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2268 |
|
|
BX_SMF BX_INSF_TYPE PSUBUSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2269 |
|
|
BX_SMF BX_INSF_TYPE PAND_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2270 |
|
|
BX_SMF BX_INSF_TYPE PADDUSB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2271 |
|
|
BX_SMF BX_INSF_TYPE PADDUSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2272 |
|
|
BX_SMF BX_INSF_TYPE PANDN_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2273 |
|
|
BX_SMF BX_INSF_TYPE PSRAW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2274 |
|
|
BX_SMF BX_INSF_TYPE PSRAD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2275 |
|
|
BX_SMF BX_INSF_TYPE PMULHW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2276 |
|
|
BX_SMF BX_INSF_TYPE PSUBSB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2277 |
|
|
BX_SMF BX_INSF_TYPE PSUBSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2278 |
|
|
BX_SMF BX_INSF_TYPE POR_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2279 |
|
|
BX_SMF BX_INSF_TYPE PADDSB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2280 |
|
|
BX_SMF BX_INSF_TYPE PADDSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2281 |
|
|
BX_SMF BX_INSF_TYPE PXOR_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2282 |
|
|
BX_SMF BX_INSF_TYPE PSLLW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2283 |
|
|
BX_SMF BX_INSF_TYPE PSLLD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2284 |
|
|
BX_SMF BX_INSF_TYPE PSLLQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2285 |
|
|
BX_SMF BX_INSF_TYPE PMADDWD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2286 |
|
|
BX_SMF BX_INSF_TYPE PSUBB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2287 |
|
|
BX_SMF BX_INSF_TYPE PSUBW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2288 |
|
|
BX_SMF BX_INSF_TYPE PSUBD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2289 |
|
|
BX_SMF BX_INSF_TYPE PADDB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2290 |
|
|
BX_SMF BX_INSF_TYPE PADDW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2291 |
|
|
BX_SMF BX_INSF_TYPE PADDD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2292 |
|
|
BX_SMF BX_INSF_TYPE PSRLW_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2293 |
|
|
BX_SMF BX_INSF_TYPE PSRAW_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2294 |
|
|
BX_SMF BX_INSF_TYPE PSLLW_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2295 |
|
|
BX_SMF BX_INSF_TYPE PSRLD_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2296 |
|
|
BX_SMF BX_INSF_TYPE PSRAD_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2297 |
|
|
BX_SMF BX_INSF_TYPE PSLLD_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2298 |
|
|
BX_SMF BX_INSF_TYPE PSRLQ_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2299 |
|
|
BX_SMF BX_INSF_TYPE PSLLQ_PqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2300 |
|
|
/* MMX */
|
2301 |
|
|
|
2302 |
|
|
#if BX_SUPPORT_3DNOW
|
2303 |
|
|
BX_SMF BX_INSF_TYPE PFPNACC_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2304 |
|
|
BX_SMF BX_INSF_TYPE PI2FW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2305 |
|
|
BX_SMF BX_INSF_TYPE PI2FD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2306 |
|
|
BX_SMF BX_INSF_TYPE PF2IW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2307 |
|
|
BX_SMF BX_INSF_TYPE PF2ID_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2308 |
|
|
BX_SMF BX_INSF_TYPE PFNACC_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2309 |
|
|
BX_SMF BX_INSF_TYPE PFCMPGE_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2310 |
|
|
BX_SMF BX_INSF_TYPE PFMIN_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2311 |
|
|
BX_SMF BX_INSF_TYPE PFRCP_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2312 |
|
|
BX_SMF BX_INSF_TYPE PFRSQRT_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2313 |
|
|
BX_SMF BX_INSF_TYPE PFSUB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2314 |
|
|
BX_SMF BX_INSF_TYPE PFADD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2315 |
|
|
BX_SMF BX_INSF_TYPE PFCMPGT_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2316 |
|
|
BX_SMF BX_INSF_TYPE PFMAX_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2317 |
|
|
BX_SMF BX_INSF_TYPE PFRCPIT1_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2318 |
|
|
BX_SMF BX_INSF_TYPE PFRSQIT1_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2319 |
|
|
BX_SMF BX_INSF_TYPE PFSUBR_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2320 |
|
|
BX_SMF BX_INSF_TYPE PFACC_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2321 |
|
|
BX_SMF BX_INSF_TYPE PFCMPEQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2322 |
|
|
BX_SMF BX_INSF_TYPE PFMUL_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2323 |
|
|
BX_SMF BX_INSF_TYPE PFRCPIT2_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2324 |
|
|
BX_SMF BX_INSF_TYPE PMULHRW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2325 |
|
|
BX_SMF BX_INSF_TYPE PSWAPD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2326 |
|
|
#endif
|
2327 |
|
|
|
2328 |
|
|
BX_SMF BX_INSF_TYPE SYSCALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2329 |
|
|
BX_SMF BX_INSF_TYPE SYSRET(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2330 |
|
|
|
2331 |
|
|
/* SSE */
|
2332 |
|
|
BX_SMF BX_INSF_TYPE FXSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2333 |
|
|
BX_SMF BX_INSF_TYPE FXRSTOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2334 |
|
|
BX_SMF BX_INSF_TYPE LDMXCSR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2335 |
|
|
BX_SMF BX_INSF_TYPE STMXCSR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2336 |
|
|
BX_SMF BX_INSF_TYPE PREFETCH(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2337 |
|
|
/* SSE */
|
2338 |
|
|
|
2339 |
|
|
/* SSE */
|
2340 |
|
|
BX_SMF BX_INSF_TYPE ANDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2341 |
|
|
BX_SMF BX_INSF_TYPE ORPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2342 |
|
|
BX_SMF BX_INSF_TYPE XORPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2343 |
|
|
BX_SMF BX_INSF_TYPE ANDNPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2344 |
|
|
BX_SMF BX_INSF_TYPE MOVUPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2345 |
|
|
BX_SMF BX_INSF_TYPE MOVUPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2346 |
|
|
BX_SMF BX_INSF_TYPE MOVSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2347 |
|
|
BX_SMF BX_INSF_TYPE MOVSS_VssWssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2348 |
|
|
BX_SMF BX_INSF_TYPE MOVSS_WssVssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2349 |
|
|
BX_SMF BX_INSF_TYPE MOVSD_WsdVsdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2350 |
|
|
BX_SMF BX_INSF_TYPE MOVHLPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2351 |
|
|
BX_SMF BX_INSF_TYPE MOVLPS_VpsMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2352 |
|
|
BX_SMF BX_INSF_TYPE MOVLHPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2353 |
|
|
BX_SMF BX_INSF_TYPE MOVHPS_VpsMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2354 |
|
|
BX_SMF BX_INSF_TYPE MOVHPS_MqVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2355 |
|
|
BX_SMF BX_INSF_TYPE MOVAPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2356 |
|
|
BX_SMF BX_INSF_TYPE MOVAPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2357 |
|
|
BX_SMF BX_INSF_TYPE MOVAPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2358 |
|
|
BX_SMF BX_INSF_TYPE CVTPI2PS_VpsQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2359 |
|
|
BX_SMF BX_INSF_TYPE CVTPI2PS_VpsQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2360 |
|
|
BX_SMF BX_INSF_TYPE CVTSI2SS_VssEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2361 |
|
|
BX_SMF BX_INSF_TYPE CVTTPS2PI_PqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2362 |
|
|
BX_SMF BX_INSF_TYPE CVTTSS2SI_GdWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2363 |
|
|
BX_SMF BX_INSF_TYPE CVTPS2PI_PqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2364 |
|
|
BX_SMF BX_INSF_TYPE CVTSS2SI_GdWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2365 |
|
|
BX_SMF BX_INSF_TYPE UCOMISS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2366 |
|
|
BX_SMF BX_INSF_TYPE COMISS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2367 |
|
|
BX_SMF BX_INSF_TYPE MOVMSKPS_GdVRps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2368 |
|
|
BX_SMF BX_INSF_TYPE SQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2369 |
|
|
BX_SMF BX_INSF_TYPE SQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2370 |
|
|
BX_SMF BX_INSF_TYPE RSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2371 |
|
|
BX_SMF BX_INSF_TYPE RSQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2372 |
|
|
BX_SMF BX_INSF_TYPE RCPPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2373 |
|
|
BX_SMF BX_INSF_TYPE RCPSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2374 |
|
|
BX_SMF BX_INSF_TYPE ADDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2375 |
|
|
BX_SMF BX_INSF_TYPE ADDSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2376 |
|
|
BX_SMF BX_INSF_TYPE MULPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2377 |
|
|
BX_SMF BX_INSF_TYPE MULSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2378 |
|
|
BX_SMF BX_INSF_TYPE SUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2379 |
|
|
BX_SMF BX_INSF_TYPE SUBSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2380 |
|
|
BX_SMF BX_INSF_TYPE MINPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2381 |
|
|
BX_SMF BX_INSF_TYPE MINSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2382 |
|
|
BX_SMF BX_INSF_TYPE DIVPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2383 |
|
|
BX_SMF BX_INSF_TYPE DIVSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2384 |
|
|
BX_SMF BX_INSF_TYPE MAXPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2385 |
|
|
BX_SMF BX_INSF_TYPE MAXSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2386 |
|
|
BX_SMF BX_INSF_TYPE PSHUFW_PqQqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2387 |
|
|
BX_SMF BX_INSF_TYPE PSHUFLW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2388 |
|
|
BX_SMF BX_INSF_TYPE CMPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2389 |
|
|
BX_SMF BX_INSF_TYPE CMPSS_VssWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2390 |
|
|
BX_SMF BX_INSF_TYPE PINSRW_PqEwIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2391 |
|
|
BX_SMF BX_INSF_TYPE PEXTRW_GdPqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2392 |
|
|
BX_SMF BX_INSF_TYPE SHUFPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2393 |
|
|
BX_SMF BX_INSF_TYPE PMOVMSKB_GdPRq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2394 |
|
|
BX_SMF BX_INSF_TYPE PMINUB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2395 |
|
|
BX_SMF BX_INSF_TYPE PMAXUB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2396 |
|
|
BX_SMF BX_INSF_TYPE PAVGB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2397 |
|
|
BX_SMF BX_INSF_TYPE PAVGW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2398 |
|
|
BX_SMF BX_INSF_TYPE PMULHUW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2399 |
|
|
BX_SMF BX_INSF_TYPE PMINSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2400 |
|
|
BX_SMF BX_INSF_TYPE PMAXSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2401 |
|
|
BX_SMF BX_INSF_TYPE PSADBW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2402 |
|
|
BX_SMF BX_INSF_TYPE MASKMOVQ_PqPRq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2403 |
|
|
/* SSE */
|
2404 |
|
|
|
2405 |
|
|
/* SSE2 */
|
2406 |
|
|
BX_SMF BX_INSF_TYPE MOVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2407 |
|
|
BX_SMF BX_INSF_TYPE CVTPI2PD_VpdQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2408 |
|
|
BX_SMF BX_INSF_TYPE CVTPI2PD_VpdQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2409 |
|
|
BX_SMF BX_INSF_TYPE CVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2410 |
|
|
BX_SMF BX_INSF_TYPE CVTTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2411 |
|
|
BX_SMF BX_INSF_TYPE CVTTSD2SI_GdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2412 |
|
|
BX_SMF BX_INSF_TYPE CVTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2413 |
|
|
BX_SMF BX_INSF_TYPE CVTSD2SI_GdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2414 |
|
|
BX_SMF BX_INSF_TYPE UCOMISD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2415 |
|
|
BX_SMF BX_INSF_TYPE COMISD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2416 |
|
|
BX_SMF BX_INSF_TYPE MOVMSKPD_GdVRpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2417 |
|
|
BX_SMF BX_INSF_TYPE SQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2418 |
|
|
BX_SMF BX_INSF_TYPE SQRTSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2419 |
|
|
BX_SMF BX_INSF_TYPE ADDPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2420 |
|
|
BX_SMF BX_INSF_TYPE ADDSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2421 |
|
|
BX_SMF BX_INSF_TYPE MULPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2422 |
|
|
BX_SMF BX_INSF_TYPE MULSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2423 |
|
|
BX_SMF BX_INSF_TYPE SUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2424 |
|
|
BX_SMF BX_INSF_TYPE SUBSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2425 |
|
|
BX_SMF BX_INSF_TYPE CVTPS2PD_VpdWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2426 |
|
|
BX_SMF BX_INSF_TYPE CVTPD2PS_VpsWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2427 |
|
|
BX_SMF BX_INSF_TYPE CVTSD2SS_VssWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2428 |
|
|
BX_SMF BX_INSF_TYPE CVTSS2SD_VsdWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2429 |
|
|
BX_SMF BX_INSF_TYPE CVTDQ2PS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2430 |
|
|
BX_SMF BX_INSF_TYPE CVTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2431 |
|
|
BX_SMF BX_INSF_TYPE CVTTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2432 |
|
|
BX_SMF BX_INSF_TYPE MINPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2433 |
|
|
BX_SMF BX_INSF_TYPE MINSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2434 |
|
|
BX_SMF BX_INSF_TYPE DIVPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2435 |
|
|
BX_SMF BX_INSF_TYPE DIVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2436 |
|
|
BX_SMF BX_INSF_TYPE MAXPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2437 |
|
|
BX_SMF BX_INSF_TYPE MAXSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2438 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKLBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2439 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKLWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2440 |
|
|
BX_SMF BX_INSF_TYPE UNPCKLPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2441 |
|
|
BX_SMF BX_INSF_TYPE PACKSSWB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2442 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2443 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2444 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2445 |
|
|
BX_SMF BX_INSF_TYPE PACKUSWB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2446 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKHBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2447 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKHWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2448 |
|
|
BX_SMF BX_INSF_TYPE UNPCKHPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2449 |
|
|
BX_SMF BX_INSF_TYPE PACKSSDW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2450 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKLQDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2451 |
|
|
BX_SMF BX_INSF_TYPE PUNPCKHQDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2452 |
|
|
BX_SMF BX_INSF_TYPE MOVD_VdqEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2453 |
|
|
BX_SMF BX_INSF_TYPE PSHUFD_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2454 |
|
|
BX_SMF BX_INSF_TYPE PSHUFHW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2455 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2456 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2457 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2458 |
|
|
BX_SMF BX_INSF_TYPE MOVD_EdVdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2459 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_VqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2460 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_VqWqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2461 |
|
|
BX_SMF BX_INSF_TYPE CMPPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2462 |
|
|
BX_SMF BX_INSF_TYPE CMPSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2463 |
|
|
BX_SMF BX_INSF_TYPE PINSRW_VdqHdqEwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2464 |
|
|
BX_SMF BX_INSF_TYPE PEXTRW_GdUdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2465 |
|
|
BX_SMF BX_INSF_TYPE SHUFPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2466 |
|
|
BX_SMF BX_INSF_TYPE PSRLW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2467 |
|
|
BX_SMF BX_INSF_TYPE PSRLD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2468 |
|
|
BX_SMF BX_INSF_TYPE PSRLQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2469 |
|
|
BX_SMF BX_INSF_TYPE PADDQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2470 |
|
|
BX_SMF BX_INSF_TYPE PADDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2471 |
|
|
BX_SMF BX_INSF_TYPE PMULLW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2472 |
|
|
BX_SMF BX_INSF_TYPE MOVDQ2Q_PqVRq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2473 |
|
|
BX_SMF BX_INSF_TYPE MOVQ2DQ_VdqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2474 |
|
|
BX_SMF BX_INSF_TYPE PMOVMSKB_GdUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2475 |
|
|
BX_SMF BX_INSF_TYPE PSUBUSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2476 |
|
|
BX_SMF BX_INSF_TYPE PSUBUSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2477 |
|
|
BX_SMF BX_INSF_TYPE PMINUB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2478 |
|
|
BX_SMF BX_INSF_TYPE PADDUSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2479 |
|
|
BX_SMF BX_INSF_TYPE PADDUSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2480 |
|
|
BX_SMF BX_INSF_TYPE PMAXUB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2481 |
|
|
BX_SMF BX_INSF_TYPE PAVGB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2482 |
|
|
BX_SMF BX_INSF_TYPE PSRAW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2483 |
|
|
BX_SMF BX_INSF_TYPE PSRAD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2484 |
|
|
BX_SMF BX_INSF_TYPE PAVGW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2485 |
|
|
BX_SMF BX_INSF_TYPE PMULHUW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2486 |
|
|
BX_SMF BX_INSF_TYPE PMULHW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2487 |
|
|
BX_SMF BX_INSF_TYPE CVTTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2488 |
|
|
BX_SMF BX_INSF_TYPE CVTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2489 |
|
|
BX_SMF BX_INSF_TYPE CVTDQ2PD_VpdWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2490 |
|
|
BX_SMF BX_INSF_TYPE PSUBSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2491 |
|
|
BX_SMF BX_INSF_TYPE PSUBSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2492 |
|
|
BX_SMF BX_INSF_TYPE PMINSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2493 |
|
|
BX_SMF BX_INSF_TYPE PADDSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2494 |
|
|
BX_SMF BX_INSF_TYPE PADDSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2495 |
|
|
BX_SMF BX_INSF_TYPE PMAXSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2496 |
|
|
BX_SMF BX_INSF_TYPE PSLLW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2497 |
|
|
BX_SMF BX_INSF_TYPE PSLLD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2498 |
|
|
BX_SMF BX_INSF_TYPE PSLLQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2499 |
|
|
BX_SMF BX_INSF_TYPE PMULUDQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2500 |
|
|
BX_SMF BX_INSF_TYPE PMULUDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2501 |
|
|
BX_SMF BX_INSF_TYPE PMADDWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2502 |
|
|
BX_SMF BX_INSF_TYPE PSADBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2503 |
|
|
BX_SMF BX_INSF_TYPE MASKMOVDQU_VdqUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2504 |
|
|
BX_SMF BX_INSF_TYPE PSUBB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2505 |
|
|
BX_SMF BX_INSF_TYPE PSUBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2506 |
|
|
BX_SMF BX_INSF_TYPE PSUBD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2507 |
|
|
BX_SMF BX_INSF_TYPE PSUBQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2508 |
|
|
BX_SMF BX_INSF_TYPE PSUBQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2509 |
|
|
BX_SMF BX_INSF_TYPE PADDB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2510 |
|
|
BX_SMF BX_INSF_TYPE PADDW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2511 |
|
|
BX_SMF BX_INSF_TYPE PADDD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2512 |
|
|
BX_SMF BX_INSF_TYPE PSRLW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2513 |
|
|
BX_SMF BX_INSF_TYPE PSRAW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2514 |
|
|
BX_SMF BX_INSF_TYPE PSLLW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2515 |
|
|
BX_SMF BX_INSF_TYPE PSRLD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2516 |
|
|
BX_SMF BX_INSF_TYPE PSRAD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2517 |
|
|
BX_SMF BX_INSF_TYPE PSLLD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2518 |
|
|
BX_SMF BX_INSF_TYPE PSRLQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2519 |
|
|
BX_SMF BX_INSF_TYPE PSRLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2520 |
|
|
BX_SMF BX_INSF_TYPE PSLLQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2521 |
|
|
BX_SMF BX_INSF_TYPE PSLLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2522 |
|
|
/* SSE2 */
|
2523 |
|
|
|
2524 |
|
|
/* SSE3 */
|
2525 |
|
|
BX_SMF BX_INSF_TYPE MOVDDUP_VpdWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2526 |
|
|
BX_SMF BX_INSF_TYPE MOVSLDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2527 |
|
|
BX_SMF BX_INSF_TYPE MOVSHDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2528 |
|
|
BX_SMF BX_INSF_TYPE HADDPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2529 |
|
|
BX_SMF BX_INSF_TYPE HADDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2530 |
|
|
BX_SMF BX_INSF_TYPE HSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2531 |
|
|
BX_SMF BX_INSF_TYPE HSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2532 |
|
|
BX_SMF BX_INSF_TYPE ADDSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2533 |
|
|
BX_SMF BX_INSF_TYPE ADDSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2534 |
|
|
/* SSE3 */
|
2535 |
|
|
|
2536 |
|
|
#if BX_CPU_LEVEL >= 6
|
2537 |
|
|
/* SSSE3 */
|
2538 |
|
|
BX_SMF BX_INSF_TYPE PSHUFB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2539 |
|
|
BX_SMF BX_INSF_TYPE PHADDW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2540 |
|
|
BX_SMF BX_INSF_TYPE PHADDD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2541 |
|
|
BX_SMF BX_INSF_TYPE PHADDSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2542 |
|
|
BX_SMF BX_INSF_TYPE PMADDUBSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2543 |
|
|
BX_SMF BX_INSF_TYPE PHSUBSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2544 |
|
|
BX_SMF BX_INSF_TYPE PHSUBW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2545 |
|
|
BX_SMF BX_INSF_TYPE PHSUBD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2546 |
|
|
BX_SMF BX_INSF_TYPE PSIGNB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2547 |
|
|
BX_SMF BX_INSF_TYPE PSIGNW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2548 |
|
|
BX_SMF BX_INSF_TYPE PSIGND_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2549 |
|
|
BX_SMF BX_INSF_TYPE PMULHRSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2550 |
|
|
BX_SMF BX_INSF_TYPE PABSB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2551 |
|
|
BX_SMF BX_INSF_TYPE PABSW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2552 |
|
|
BX_SMF BX_INSF_TYPE PABSD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2553 |
|
|
BX_SMF BX_INSF_TYPE PALIGNR_PqQqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2554 |
|
|
|
2555 |
|
|
BX_SMF BX_INSF_TYPE PSHUFB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2556 |
|
|
BX_SMF BX_INSF_TYPE PHADDW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2557 |
|
|
BX_SMF BX_INSF_TYPE PHADDD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2558 |
|
|
BX_SMF BX_INSF_TYPE PHADDSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2559 |
|
|
BX_SMF BX_INSF_TYPE PMADDUBSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2560 |
|
|
BX_SMF BX_INSF_TYPE PHSUBSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2561 |
|
|
BX_SMF BX_INSF_TYPE PHSUBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2562 |
|
|
BX_SMF BX_INSF_TYPE PHSUBD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2563 |
|
|
BX_SMF BX_INSF_TYPE PSIGNB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2564 |
|
|
BX_SMF BX_INSF_TYPE PSIGNW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2565 |
|
|
BX_SMF BX_INSF_TYPE PSIGND_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2566 |
|
|
BX_SMF BX_INSF_TYPE PMULHRSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2567 |
|
|
BX_SMF BX_INSF_TYPE PABSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2568 |
|
|
BX_SMF BX_INSF_TYPE PABSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2569 |
|
|
BX_SMF BX_INSF_TYPE PABSD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2570 |
|
|
BX_SMF BX_INSF_TYPE PALIGNR_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2571 |
|
|
/* SSSE3 */
|
2572 |
|
|
|
2573 |
|
|
/* SSE4.1 */
|
2574 |
|
|
BX_SMF BX_INSF_TYPE PBLENDVB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2575 |
|
|
BX_SMF BX_INSF_TYPE BLENDVPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2576 |
|
|
BX_SMF BX_INSF_TYPE BLENDVPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2577 |
|
|
BX_SMF BX_INSF_TYPE PTEST_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2578 |
|
|
BX_SMF BX_INSF_TYPE PMULDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2579 |
|
|
BX_SMF BX_INSF_TYPE PCMPEQQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2580 |
|
|
BX_SMF BX_INSF_TYPE PACKUSDW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2581 |
|
|
BX_SMF BX_INSF_TYPE PMOVSXBW_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2582 |
|
|
BX_SMF BX_INSF_TYPE PMOVSXBD_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2583 |
|
|
BX_SMF BX_INSF_TYPE PMOVSXBQ_VdqWwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2584 |
|
|
BX_SMF BX_INSF_TYPE PMOVSXWD_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2585 |
|
|
BX_SMF BX_INSF_TYPE PMOVSXWQ_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2586 |
|
|
BX_SMF BX_INSF_TYPE PMOVSXDQ_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2587 |
|
|
BX_SMF BX_INSF_TYPE PMOVZXBW_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2588 |
|
|
BX_SMF BX_INSF_TYPE PMOVZXBD_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2589 |
|
|
BX_SMF BX_INSF_TYPE PMOVZXBQ_VdqWwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2590 |
|
|
BX_SMF BX_INSF_TYPE PMOVZXWD_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2591 |
|
|
BX_SMF BX_INSF_TYPE PMOVZXWQ_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2592 |
|
|
BX_SMF BX_INSF_TYPE PMOVZXDQ_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2593 |
|
|
BX_SMF BX_INSF_TYPE PMINSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2594 |
|
|
BX_SMF BX_INSF_TYPE PMINSD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2595 |
|
|
BX_SMF BX_INSF_TYPE PMINUW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2596 |
|
|
BX_SMF BX_INSF_TYPE PMINUD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2597 |
|
|
BX_SMF BX_INSF_TYPE PMAXSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2598 |
|
|
BX_SMF BX_INSF_TYPE PMAXSD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2599 |
|
|
BX_SMF BX_INSF_TYPE PMAXUW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2600 |
|
|
BX_SMF BX_INSF_TYPE PMAXUD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2601 |
|
|
BX_SMF BX_INSF_TYPE PMULLD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2602 |
|
|
BX_SMF BX_INSF_TYPE PHMINPOSUW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2603 |
|
|
BX_SMF BX_INSF_TYPE ROUNDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2604 |
|
|
BX_SMF BX_INSF_TYPE ROUNDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2605 |
|
|
BX_SMF BX_INSF_TYPE ROUNDSS_VssWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2606 |
|
|
BX_SMF BX_INSF_TYPE ROUNDSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2607 |
|
|
BX_SMF BX_INSF_TYPE BLENDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2608 |
|
|
BX_SMF BX_INSF_TYPE BLENDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2609 |
|
|
BX_SMF BX_INSF_TYPE PBLENDW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2610 |
|
|
BX_SMF BX_INSF_TYPE PEXTRB_EbdVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2611 |
|
|
BX_SMF BX_INSF_TYPE PEXTRB_EbdVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2612 |
|
|
BX_SMF BX_INSF_TYPE PEXTRW_EwdVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2613 |
|
|
BX_SMF BX_INSF_TYPE PEXTRW_EwdVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2614 |
|
|
BX_SMF BX_INSF_TYPE PEXTRD_EdVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2615 |
|
|
BX_SMF BX_INSF_TYPE PEXTRD_EdVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2616 |
|
|
BX_SMF BX_INSF_TYPE EXTRACTPS_EdVpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2617 |
|
|
BX_SMF BX_INSF_TYPE EXTRACTPS_EdVpsIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2618 |
|
|
BX_SMF BX_INSF_TYPE PINSRB_VdqHdqEbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2619 |
|
|
BX_SMF BX_INSF_TYPE PINSRB_VdqHdqEbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2620 |
|
|
BX_SMF BX_INSF_TYPE INSERTPS_VpsHpsWssIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2621 |
|
|
BX_SMF BX_INSF_TYPE PINSRD_VdqHdqEdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2622 |
|
|
BX_SMF BX_INSF_TYPE PINSRD_VdqHdqEdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2623 |
|
|
BX_SMF BX_INSF_TYPE DPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2624 |
|
|
BX_SMF BX_INSF_TYPE DPPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2625 |
|
|
BX_SMF BX_INSF_TYPE MPSADBW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2626 |
|
|
/* SSE4.1 */
|
2627 |
|
|
|
2628 |
|
|
/* SSE4.2 */
|
2629 |
|
|
BX_SMF BX_INSF_TYPE CRC32_GdEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2630 |
|
|
BX_SMF BX_INSF_TYPE CRC32_GdEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2631 |
|
|
BX_SMF BX_INSF_TYPE CRC32_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2632 |
|
|
#if BX_SUPPORT_X86_64
|
2633 |
|
|
BX_SMF BX_INSF_TYPE CRC32_GdEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2634 |
|
|
#endif
|
2635 |
|
|
BX_SMF BX_INSF_TYPE PCMPGTQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2636 |
|
|
BX_SMF BX_INSF_TYPE PCMPESTRM_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2637 |
|
|
BX_SMF BX_INSF_TYPE PCMPESTRI_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2638 |
|
|
BX_SMF BX_INSF_TYPE PCMPISTRM_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2639 |
|
|
BX_SMF BX_INSF_TYPE PCMPISTRI_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2640 |
|
|
/* SSE4.2 */
|
2641 |
|
|
|
2642 |
|
|
/* MOVBE Intel Atom(R) instruction */
|
2643 |
|
|
BX_SMF BX_INSF_TYPE MOVBE_GwMw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2644 |
|
|
BX_SMF BX_INSF_TYPE MOVBE_GdMd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2645 |
|
|
BX_SMF BX_INSF_TYPE MOVBE_MwGw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2646 |
|
|
BX_SMF BX_INSF_TYPE MOVBE_MdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2647 |
|
|
#if BX_SUPPORT_X86_64
|
2648 |
|
|
BX_SMF BX_INSF_TYPE MOVBE_GqMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2649 |
|
|
BX_SMF BX_INSF_TYPE MOVBE_MqGq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2650 |
|
|
#endif
|
2651 |
|
|
/* MOVBE Intel Atom(R) instruction */
|
2652 |
|
|
#endif
|
2653 |
|
|
|
2654 |
|
|
/* XSAVE/XRSTOR extensions */
|
2655 |
|
|
BX_SMF BX_INSF_TYPE XSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2656 |
|
|
BX_SMF BX_INSF_TYPE XRSTOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2657 |
|
|
BX_SMF BX_INSF_TYPE XGETBV(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2658 |
|
|
BX_SMF BX_INSF_TYPE XSETBV(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2659 |
|
|
/* XSAVE/XRSTOR extensions */
|
2660 |
|
|
|
2661 |
|
|
#if BX_CPU_LEVEL >= 6
|
2662 |
|
|
/* AES instructions */
|
2663 |
|
|
BX_SMF BX_INSF_TYPE AESIMC_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2664 |
|
|
BX_SMF BX_INSF_TYPE AESENC_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2665 |
|
|
BX_SMF BX_INSF_TYPE AESENCLAST_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2666 |
|
|
BX_SMF BX_INSF_TYPE AESDEC_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2667 |
|
|
BX_SMF BX_INSF_TYPE AESDECLAST_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2668 |
|
|
BX_SMF BX_INSF_TYPE AESKEYGENASSIST_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2669 |
|
|
BX_SMF BX_INSF_TYPE PCLMULQDQ_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2670 |
|
|
/* AES instructions */
|
2671 |
|
|
#endif
|
2672 |
|
|
|
2673 |
|
|
/* VMX instructions */
|
2674 |
|
|
BX_SMF BX_INSF_TYPE VMXON(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2675 |
|
|
BX_SMF BX_INSF_TYPE VMXOFF(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2676 |
|
|
BX_SMF BX_INSF_TYPE VMCALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2677 |
|
|
BX_SMF BX_INSF_TYPE VMLAUNCH(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2678 |
|
|
BX_SMF BX_INSF_TYPE VMCLEAR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2679 |
|
|
BX_SMF BX_INSF_TYPE VMPTRLD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2680 |
|
|
BX_SMF BX_INSF_TYPE VMPTRST(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2681 |
|
|
BX_SMF BX_INSF_TYPE VMREAD_EdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2682 |
|
|
BX_SMF BX_INSF_TYPE VMWRITE_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2683 |
|
|
#if BX_SUPPORT_X86_64
|
2684 |
|
|
BX_SMF BX_INSF_TYPE VMREAD_EqGq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2685 |
|
|
BX_SMF BX_INSF_TYPE VMWRITE_GqEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2686 |
|
|
#endif
|
2687 |
|
|
BX_SMF BX_INSF_TYPE VMFUNC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2688 |
|
|
/* VMX instructions */
|
2689 |
|
|
|
2690 |
|
|
/* SVM instructions */
|
2691 |
|
|
BX_SMF BX_INSF_TYPE VMRUN(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2692 |
|
|
BX_SMF BX_INSF_TYPE VMMCALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2693 |
|
|
BX_SMF BX_INSF_TYPE VMLOAD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2694 |
|
|
BX_SMF BX_INSF_TYPE VMSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2695 |
|
|
BX_SMF BX_INSF_TYPE SKINIT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2696 |
|
|
BX_SMF BX_INSF_TYPE CLGI(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2697 |
|
|
BX_SMF BX_INSF_TYPE STGI(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2698 |
|
|
BX_SMF BX_INSF_TYPE INVLPGA(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2699 |
|
|
/* SVM instructions */
|
2700 |
|
|
|
2701 |
|
|
/* SMX instructions */
|
2702 |
|
|
BX_SMF BX_INSF_TYPE GETSEC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2703 |
|
|
/* SMX instructions */
|
2704 |
|
|
|
2705 |
|
|
#if BX_CPU_LEVEL >= 6
|
2706 |
|
|
/* VMXx2 */
|
2707 |
|
|
BX_SMF BX_INSF_TYPE INVEPT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2708 |
|
|
BX_SMF BX_INSF_TYPE INVVPID(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2709 |
|
|
/* VMXx2 */
|
2710 |
|
|
|
2711 |
|
|
BX_SMF BX_INSF_TYPE INVPCID(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2712 |
|
|
#endif
|
2713 |
|
|
|
2714 |
|
|
#if BX_SUPPORT_AVX
|
2715 |
|
|
/* AVX */
|
2716 |
|
|
BX_SMF BX_INSF_TYPE VZEROUPPER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2717 |
|
|
BX_SMF BX_INSF_TYPE VZEROALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2718 |
|
|
|
2719 |
|
|
BX_SMF BX_INSF_TYPE VMOVSS_VssHpsWssR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
2720 |
|
|
BX_SMF BX_INSF_TYPE VMOVSD_VsdHpdWsdR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
2721 |
|
|
BX_SMF BX_INSF_TYPE VMOVAPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2722 |
|
|
BX_SMF BX_INSF_TYPE VMOVAPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2723 |
|
|
BX_SMF BX_INSF_TYPE VMOVUPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2724 |
|
|
BX_SMF BX_INSF_TYPE VMOVAPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2725 |
|
|
BX_SMF BX_INSF_TYPE VMOVUPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2726 |
|
|
BX_SMF BX_INSF_TYPE VMOVLPD_VpdHpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2727 |
|
|
BX_SMF BX_INSF_TYPE VMOVHPD_VpdHpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2728 |
|
|
BX_SMF BX_INSF_TYPE VMOVLHPS_VpsHpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2729 |
|
|
BX_SMF BX_INSF_TYPE VMOVHLPS_VpsHpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2730 |
|
|
BX_SMF BX_INSF_TYPE VMOVSHDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2731 |
|
|
BX_SMF BX_INSF_TYPE VMOVSLDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2732 |
|
|
BX_SMF BX_INSF_TYPE VMOVDDUP_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2733 |
|
|
BX_SMF BX_INSF_TYPE VUNPCKLPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2734 |
|
|
BX_SMF BX_INSF_TYPE VUNPCKHPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2735 |
|
|
BX_SMF BX_INSF_TYPE VUNPCKLPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2736 |
|
|
BX_SMF BX_INSF_TYPE VUNPCKHPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2737 |
|
|
BX_SMF BX_INSF_TYPE VMOVMSKPS_GdVRps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2738 |
|
|
BX_SMF BX_INSF_TYPE VMOVMSKPD_GdVRpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2739 |
|
|
BX_SMF BX_INSF_TYPE VPMOVMSKB_GdUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2740 |
|
|
BX_SMF BX_INSF_TYPE VSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2741 |
|
|
BX_SMF BX_INSF_TYPE VSQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2742 |
|
|
BX_SMF BX_INSF_TYPE VSQRTSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2743 |
|
|
BX_SMF BX_INSF_TYPE VSQRTSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2744 |
|
|
BX_SMF BX_INSF_TYPE VHADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2745 |
|
|
BX_SMF BX_INSF_TYPE VHADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2746 |
|
|
BX_SMF BX_INSF_TYPE VHSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2747 |
|
|
BX_SMF BX_INSF_TYPE VHSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2748 |
|
|
BX_SMF BX_INSF_TYPE VADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2749 |
|
|
BX_SMF BX_INSF_TYPE VADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2750 |
|
|
BX_SMF BX_INSF_TYPE VADDSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2751 |
|
|
BX_SMF BX_INSF_TYPE VADDSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2752 |
|
|
BX_SMF BX_INSF_TYPE VMULPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2753 |
|
|
BX_SMF BX_INSF_TYPE VMULPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2754 |
|
|
BX_SMF BX_INSF_TYPE VMULSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2755 |
|
|
BX_SMF BX_INSF_TYPE VMULSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2756 |
|
|
BX_SMF BX_INSF_TYPE VSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2757 |
|
|
BX_SMF BX_INSF_TYPE VSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2758 |
|
|
BX_SMF BX_INSF_TYPE VSUBSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2759 |
|
|
BX_SMF BX_INSF_TYPE VSUBSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2760 |
|
|
BX_SMF BX_INSF_TYPE VCVTSS2SD_VsdWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2761 |
|
|
BX_SMF BX_INSF_TYPE VCVTSD2SS_VssWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2762 |
|
|
BX_SMF BX_INSF_TYPE VCVTDQ2PS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2763 |
|
|
BX_SMF BX_INSF_TYPE VCVTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2764 |
|
|
BX_SMF BX_INSF_TYPE VCVTTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2765 |
|
|
BX_SMF BX_INSF_TYPE VCVTPS2PD_VpdWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2766 |
|
|
BX_SMF BX_INSF_TYPE VCVTPD2PS_VpsWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2767 |
|
|
BX_SMF BX_INSF_TYPE VCVTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2768 |
|
|
BX_SMF BX_INSF_TYPE VCVTDQ2PD_VpdWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2769 |
|
|
BX_SMF BX_INSF_TYPE VCVTTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2770 |
|
|
BX_SMF BX_INSF_TYPE VCVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2771 |
|
|
BX_SMF BX_INSF_TYPE VCVTSI2SS_VssEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2772 |
|
|
BX_SMF BX_INSF_TYPE VCVTSI2SD_VsdEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2773 |
|
|
BX_SMF BX_INSF_TYPE VCVTSI2SS_VssEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2774 |
|
|
BX_SMF BX_INSF_TYPE VMINPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2775 |
|
|
BX_SMF BX_INSF_TYPE VMINPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2776 |
|
|
BX_SMF BX_INSF_TYPE VMINSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2777 |
|
|
BX_SMF BX_INSF_TYPE VMINSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2778 |
|
|
BX_SMF BX_INSF_TYPE VDIVPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2779 |
|
|
BX_SMF BX_INSF_TYPE VDIVPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2780 |
|
|
BX_SMF BX_INSF_TYPE VDIVSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2781 |
|
|
BX_SMF BX_INSF_TYPE VDIVSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2782 |
|
|
BX_SMF BX_INSF_TYPE VMAXPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2783 |
|
|
BX_SMF BX_INSF_TYPE VMAXPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2784 |
|
|
BX_SMF BX_INSF_TYPE VMAXSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2785 |
|
|
BX_SMF BX_INSF_TYPE VMAXSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2786 |
|
|
BX_SMF BX_INSF_TYPE VCMPPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2787 |
|
|
BX_SMF BX_INSF_TYPE VCMPSS_VssHpsWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2788 |
|
|
BX_SMF BX_INSF_TYPE VCMPPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2789 |
|
|
BX_SMF BX_INSF_TYPE VCMPSD_VsdHpdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2790 |
|
|
BX_SMF BX_INSF_TYPE VADDSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2791 |
|
|
BX_SMF BX_INSF_TYPE VADDSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2792 |
|
|
BX_SMF BX_INSF_TYPE VROUNDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2793 |
|
|
BX_SMF BX_INSF_TYPE VROUNDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2794 |
|
|
BX_SMF BX_INSF_TYPE VROUNDSS_VssHpsWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2795 |
|
|
BX_SMF BX_INSF_TYPE VROUNDSD_VsdHpdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2796 |
|
|
BX_SMF BX_INSF_TYPE VDPPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2797 |
|
|
BX_SMF BX_INSF_TYPE VRSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2798 |
|
|
BX_SMF BX_INSF_TYPE VRSQRTSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2799 |
|
|
BX_SMF BX_INSF_TYPE VRCPPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2800 |
|
|
BX_SMF BX_INSF_TYPE VRCPSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2801 |
|
|
BX_SMF BX_INSF_TYPE VSHUFPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2802 |
|
|
BX_SMF BX_INSF_TYPE VSHUFPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2803 |
|
|
BX_SMF BX_INSF_TYPE VBLENDPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2804 |
|
|
BX_SMF BX_INSF_TYPE VBLENDPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2805 |
|
|
BX_SMF BX_INSF_TYPE VPBLENDVB_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2806 |
|
|
BX_SMF BX_INSF_TYPE VPTEST_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2807 |
|
|
BX_SMF BX_INSF_TYPE VTESTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2808 |
|
|
BX_SMF BX_INSF_TYPE VTESTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2809 |
|
|
BX_SMF BX_INSF_TYPE VANDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2810 |
|
|
BX_SMF BX_INSF_TYPE VANDNPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2811 |
|
|
BX_SMF BX_INSF_TYPE VORPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2812 |
|
|
BX_SMF BX_INSF_TYPE VXORPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2813 |
|
|
BX_SMF BX_INSF_TYPE VBROADCASTF128_VdqMdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2814 |
|
|
BX_SMF BX_INSF_TYPE VBLENDVPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2815 |
|
|
BX_SMF BX_INSF_TYPE VBLENDVPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2816 |
|
|
BX_SMF BX_INSF_TYPE VINSERTF128_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2817 |
|
|
BX_SMF BX_INSF_TYPE VEXTRACTF128_WdqVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2818 |
|
|
BX_SMF BX_INSF_TYPE VEXTRACTF128_WdqVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2819 |
|
|
BX_SMF BX_INSF_TYPE VPERMILPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2820 |
|
|
BX_SMF BX_INSF_TYPE VPERMILPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2821 |
|
|
BX_SMF BX_INSF_TYPE VPERMILPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2822 |
|
|
BX_SMF BX_INSF_TYPE VPERMILPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2823 |
|
|
BX_SMF BX_INSF_TYPE VPERM2F128_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2824 |
|
|
BX_SMF BX_INSF_TYPE VMASKMOVPS_VpsHpsMps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2825 |
|
|
BX_SMF BX_INSF_TYPE VMASKMOVPD_VpdHpdMpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2826 |
|
|
BX_SMF BX_INSF_TYPE VMASKMOVPS_MpsHpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2827 |
|
|
BX_SMF BX_INSF_TYPE VMASKMOVPD_MpdHpdVpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2828 |
|
|
|
2829 |
|
|
BX_SMF BX_INSF_TYPE VCVTPH2PS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2830 |
|
|
BX_SMF BX_INSF_TYPE VCVTPS2PH_WpsVpsIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2831 |
|
|
/* AVX */
|
2832 |
|
|
|
2833 |
|
|
/* AVX2 */
|
2834 |
|
|
BX_SMF BX_INSF_TYPE VPCMPEQB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2835 |
|
|
BX_SMF BX_INSF_TYPE VPCMPEQW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2836 |
|
|
BX_SMF BX_INSF_TYPE VPCMPEQD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2837 |
|
|
BX_SMF BX_INSF_TYPE VPCMPEQQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2838 |
|
|
BX_SMF BX_INSF_TYPE VPCMPGTB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2839 |
|
|
BX_SMF BX_INSF_TYPE VPCMPGTW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2840 |
|
|
BX_SMF BX_INSF_TYPE VPCMPGTD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2841 |
|
|
BX_SMF BX_INSF_TYPE VPCMPGTQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2842 |
|
|
BX_SMF BX_INSF_TYPE VPMINSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2843 |
|
|
BX_SMF BX_INSF_TYPE VPMINSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2844 |
|
|
BX_SMF BX_INSF_TYPE VPMINSD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2845 |
|
|
BX_SMF BX_INSF_TYPE VPMINUB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2846 |
|
|
BX_SMF BX_INSF_TYPE VPMINUW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2847 |
|
|
BX_SMF BX_INSF_TYPE VPMINUD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2848 |
|
|
BX_SMF BX_INSF_TYPE VPMAXSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2849 |
|
|
BX_SMF BX_INSF_TYPE VPMAXSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2850 |
|
|
BX_SMF BX_INSF_TYPE VPMAXSD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2851 |
|
|
BX_SMF BX_INSF_TYPE VPMAXUB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2852 |
|
|
BX_SMF BX_INSF_TYPE VPMAXUW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2853 |
|
|
BX_SMF BX_INSF_TYPE VPMAXUD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2854 |
|
|
BX_SMF BX_INSF_TYPE VPSIGNB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2855 |
|
|
BX_SMF BX_INSF_TYPE VPSIGNW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2856 |
|
|
BX_SMF BX_INSF_TYPE VPSIGND_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2857 |
|
|
|
2858 |
|
|
BX_SMF BX_INSF_TYPE VPADDB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2859 |
|
|
BX_SMF BX_INSF_TYPE VPADDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2860 |
|
|
BX_SMF BX_INSF_TYPE VPADDD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2861 |
|
|
BX_SMF BX_INSF_TYPE VPADDQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2862 |
|
|
BX_SMF BX_INSF_TYPE VPSUBB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2863 |
|
|
BX_SMF BX_INSF_TYPE VPSUBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2864 |
|
|
BX_SMF BX_INSF_TYPE VPSUBD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2865 |
|
|
BX_SMF BX_INSF_TYPE VPSUBQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2866 |
|
|
BX_SMF BX_INSF_TYPE VPABSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2867 |
|
|
BX_SMF BX_INSF_TYPE VPABSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2868 |
|
|
BX_SMF BX_INSF_TYPE VPABSD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2869 |
|
|
BX_SMF BX_INSF_TYPE VPSUBSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2870 |
|
|
BX_SMF BX_INSF_TYPE VPSUBSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2871 |
|
|
BX_SMF BX_INSF_TYPE VPSUBUSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2872 |
|
|
BX_SMF BX_INSF_TYPE VPSUBUSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2873 |
|
|
BX_SMF BX_INSF_TYPE VPADDSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2874 |
|
|
BX_SMF BX_INSF_TYPE VPADDSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2875 |
|
|
BX_SMF BX_INSF_TYPE VPADDUSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2876 |
|
|
BX_SMF BX_INSF_TYPE VPADDUSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2877 |
|
|
BX_SMF BX_INSF_TYPE VPAVGB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2878 |
|
|
BX_SMF BX_INSF_TYPE VPAVGW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2879 |
|
|
BX_SMF BX_INSF_TYPE VPHADDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2880 |
|
|
BX_SMF BX_INSF_TYPE VPHADDD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2881 |
|
|
BX_SMF BX_INSF_TYPE VPHADDSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2882 |
|
|
BX_SMF BX_INSF_TYPE VPHSUBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2883 |
|
|
BX_SMF BX_INSF_TYPE VPHSUBD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2884 |
|
|
BX_SMF BX_INSF_TYPE VPHSUBSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2885 |
|
|
BX_SMF BX_INSF_TYPE VPSHUFHW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2886 |
|
|
BX_SMF BX_INSF_TYPE VPSHUFLW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2887 |
|
|
BX_SMF BX_INSF_TYPE VPACKUSWB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2888 |
|
|
BX_SMF BX_INSF_TYPE VPACKSSWB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2889 |
|
|
BX_SMF BX_INSF_TYPE VPACKUSDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2890 |
|
|
BX_SMF BX_INSF_TYPE VPACKSSDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2891 |
|
|
BX_SMF BX_INSF_TYPE VPUNPCKLBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2892 |
|
|
BX_SMF BX_INSF_TYPE VPUNPCKHBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2893 |
|
|
BX_SMF BX_INSF_TYPE VPUNPCKLWD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2894 |
|
|
BX_SMF BX_INSF_TYPE VPUNPCKHWD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2895 |
|
|
BX_SMF BX_INSF_TYPE VPMULLD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2896 |
|
|
BX_SMF BX_INSF_TYPE VPMULLW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2897 |
|
|
BX_SMF BX_INSF_TYPE VPMULHW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2898 |
|
|
BX_SMF BX_INSF_TYPE VPMULHUW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2899 |
|
|
BX_SMF BX_INSF_TYPE VPMULDQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2900 |
|
|
BX_SMF BX_INSF_TYPE VPMULUDQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2901 |
|
|
BX_SMF BX_INSF_TYPE VPMULHRSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2902 |
|
|
BX_SMF BX_INSF_TYPE VPMADDUBSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2903 |
|
|
BX_SMF BX_INSF_TYPE VPMADDWD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2904 |
|
|
BX_SMF BX_INSF_TYPE VMPSADBW_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2905 |
|
|
BX_SMF BX_INSF_TYPE VPBLENDW_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2906 |
|
|
BX_SMF BX_INSF_TYPE VPSADBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2907 |
|
|
BX_SMF BX_INSF_TYPE VPSHUFB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2908 |
|
|
BX_SMF BX_INSF_TYPE VPSRLW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2909 |
|
|
BX_SMF BX_INSF_TYPE VPSRLD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2910 |
|
|
BX_SMF BX_INSF_TYPE VPSRLQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2911 |
|
|
BX_SMF BX_INSF_TYPE VPSLLW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2912 |
|
|
BX_SMF BX_INSF_TYPE VPSLLD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2913 |
|
|
BX_SMF BX_INSF_TYPE VPSLLQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2914 |
|
|
BX_SMF BX_INSF_TYPE VPSRAW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2915 |
|
|
BX_SMF BX_INSF_TYPE VPSRAD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2916 |
|
|
BX_SMF BX_INSF_TYPE VPSRLW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2917 |
|
|
BX_SMF BX_INSF_TYPE VPSRLD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2918 |
|
|
BX_SMF BX_INSF_TYPE VPSRLQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2919 |
|
|
BX_SMF BX_INSF_TYPE VPSLLW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2920 |
|
|
BX_SMF BX_INSF_TYPE VPSLLD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2921 |
|
|
BX_SMF BX_INSF_TYPE VPSLLQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2922 |
|
|
BX_SMF BX_INSF_TYPE VPSRAW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2923 |
|
|
BX_SMF BX_INSF_TYPE VPSRAD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2924 |
|
|
BX_SMF BX_INSF_TYPE VPSRLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2925 |
|
|
BX_SMF BX_INSF_TYPE VPSLLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2926 |
|
|
BX_SMF BX_INSF_TYPE VPALIGNR_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2927 |
|
|
|
2928 |
|
|
BX_SMF BX_INSF_TYPE VPMOVSXBW256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2929 |
|
|
BX_SMF BX_INSF_TYPE VPMOVSXBD256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2930 |
|
|
BX_SMF BX_INSF_TYPE VPMOVSXBQ256_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2931 |
|
|
BX_SMF BX_INSF_TYPE VPMOVSXWD256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2932 |
|
|
BX_SMF BX_INSF_TYPE VPMOVSXWQ256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2933 |
|
|
BX_SMF BX_INSF_TYPE VPMOVSXDQ256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2934 |
|
|
BX_SMF BX_INSF_TYPE VPMOVZXBW256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2935 |
|
|
BX_SMF BX_INSF_TYPE VPMOVZXBD256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2936 |
|
|
BX_SMF BX_INSF_TYPE VPMOVZXBQ256_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2937 |
|
|
BX_SMF BX_INSF_TYPE VPMOVZXWD256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2938 |
|
|
BX_SMF BX_INSF_TYPE VPMOVZXWQ256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2939 |
|
|
BX_SMF BX_INSF_TYPE VPMOVZXDQ256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2940 |
|
|
|
2941 |
|
|
BX_SMF BX_INSF_TYPE VPERMD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2942 |
|
|
BX_SMF BX_INSF_TYPE VPERMQ_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2943 |
|
|
BX_SMF BX_INSF_TYPE VPSRAVD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2944 |
|
|
BX_SMF BX_INSF_TYPE VPSLLVD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2945 |
|
|
BX_SMF BX_INSF_TYPE VPSLLVQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2946 |
|
|
BX_SMF BX_INSF_TYPE VPSRLVD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2947 |
|
|
BX_SMF BX_INSF_TYPE VPSRLVQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2948 |
|
|
|
2949 |
|
|
BX_SMF BX_INSF_TYPE VPBROADCASTB_VdqWb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2950 |
|
|
BX_SMF BX_INSF_TYPE VPBROADCASTW_VdqWw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2951 |
|
|
BX_SMF BX_INSF_TYPE VPBROADCASTD_VdqWd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2952 |
|
|
BX_SMF BX_INSF_TYPE VPBROADCASTQ_VdqWq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2953 |
|
|
|
2954 |
|
|
BX_SMF BX_INSF_TYPE VGATHERDPS_VpsHps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2955 |
|
|
BX_SMF BX_INSF_TYPE VGATHERQPS_VpsHps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2956 |
|
|
BX_SMF BX_INSF_TYPE VGATHERDPD_VpdHpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2957 |
|
|
BX_SMF BX_INSF_TYPE VGATHERQPD_VpdHpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2958 |
|
|
/* AVX2 */
|
2959 |
|
|
|
2960 |
|
|
/* AVX2 FMA */
|
2961 |
|
|
BX_SMF BX_INSF_TYPE VFMADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2962 |
|
|
BX_SMF BX_INSF_TYPE VFMADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2963 |
|
|
BX_SMF BX_INSF_TYPE VFMADDSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2964 |
|
|
BX_SMF BX_INSF_TYPE VFMADDSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2965 |
|
|
BX_SMF BX_INSF_TYPE VFMADDSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2966 |
|
|
BX_SMF BX_INSF_TYPE VFMADDSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2967 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2968 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2969 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2970 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2971 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2972 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2973 |
|
|
BX_SMF BX_INSF_TYPE VFNMADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2974 |
|
|
BX_SMF BX_INSF_TYPE VFNMADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2975 |
|
|
BX_SMF BX_INSF_TYPE VFNMADDSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2976 |
|
|
BX_SMF BX_INSF_TYPE VFNMADDSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2977 |
|
|
BX_SMF BX_INSF_TYPE VFNMSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2978 |
|
|
BX_SMF BX_INSF_TYPE VFNMSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2979 |
|
|
BX_SMF BX_INSF_TYPE VFNMSUBSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2980 |
|
|
BX_SMF BX_INSF_TYPE VFNMSUBSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2981 |
|
|
/* AVX2 FMA */
|
2982 |
|
|
|
2983 |
|
|
/* BMI */
|
2984 |
|
|
BX_SMF BX_INSF_TYPE ANDN_GdBdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2985 |
|
|
BX_SMF BX_INSF_TYPE MULX_GdBdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2986 |
|
|
BX_SMF BX_INSF_TYPE BLSI_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2987 |
|
|
BX_SMF BX_INSF_TYPE BLSMSK_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2988 |
|
|
BX_SMF BX_INSF_TYPE BLSR_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2989 |
|
|
BX_SMF BX_INSF_TYPE RORX_GdEdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2990 |
|
|
BX_SMF BX_INSF_TYPE SHLX_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2991 |
|
|
BX_SMF BX_INSF_TYPE SHRX_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2992 |
|
|
BX_SMF BX_INSF_TYPE SARX_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2993 |
|
|
BX_SMF BX_INSF_TYPE BEXTR_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2994 |
|
|
BX_SMF BX_INSF_TYPE BZHI_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2995 |
|
|
BX_SMF BX_INSF_TYPE PEXT_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2996 |
|
|
BX_SMF BX_INSF_TYPE PDEP_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2997 |
|
|
|
2998 |
|
|
BX_SMF BX_INSF_TYPE ANDN_GqBqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
2999 |
|
|
BX_SMF BX_INSF_TYPE MULX_GqBqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3000 |
|
|
BX_SMF BX_INSF_TYPE BLSI_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3001 |
|
|
BX_SMF BX_INSF_TYPE BLSMSK_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3002 |
|
|
BX_SMF BX_INSF_TYPE BLSR_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3003 |
|
|
BX_SMF BX_INSF_TYPE RORX_GqEqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3004 |
|
|
BX_SMF BX_INSF_TYPE SHLX_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3005 |
|
|
BX_SMF BX_INSF_TYPE SHRX_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3006 |
|
|
BX_SMF BX_INSF_TYPE SARX_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3007 |
|
|
BX_SMF BX_INSF_TYPE BEXTR_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3008 |
|
|
BX_SMF BX_INSF_TYPE BZHI_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3009 |
|
|
BX_SMF BX_INSF_TYPE PEXT_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3010 |
|
|
BX_SMF BX_INSF_TYPE PDEP_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3011 |
|
|
/* BMI */
|
3012 |
|
|
|
3013 |
|
|
/* FMA4 specific handlers (AMD) */
|
3014 |
|
|
BX_SMF BX_INSF_TYPE VFMADDSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3015 |
|
|
BX_SMF BX_INSF_TYPE VFMADDSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3016 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3017 |
|
|
BX_SMF BX_INSF_TYPE VFMSUBSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3018 |
|
|
BX_SMF BX_INSF_TYPE VFNMADDSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3019 |
|
|
BX_SMF BX_INSF_TYPE VFNMADDSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3020 |
|
|
BX_SMF BX_INSF_TYPE VFNMSUBSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3021 |
|
|
BX_SMF BX_INSF_TYPE VFNMSUBSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3022 |
|
|
/* FMA4 specific handlers (AMD) */
|
3023 |
|
|
|
3024 |
|
|
/* XOP (AMD) */
|
3025 |
|
|
BX_SMF BX_INSF_TYPE VPCMOV_VdqHdqWdqVIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3026 |
|
|
BX_SMF BX_INSF_TYPE VPPERM_VdqHdqWdqVIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3027 |
|
|
BX_SMF BX_INSF_TYPE VPSHAB_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3028 |
|
|
BX_SMF BX_INSF_TYPE VPSHAW_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3029 |
|
|
BX_SMF BX_INSF_TYPE VPSHAD_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3030 |
|
|
BX_SMF BX_INSF_TYPE VPSHAQ_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3031 |
|
|
BX_SMF BX_INSF_TYPE VPROTB_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3032 |
|
|
BX_SMF BX_INSF_TYPE VPROTW_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3033 |
|
|
BX_SMF BX_INSF_TYPE VPROTD_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3034 |
|
|
BX_SMF BX_INSF_TYPE VPROTQ_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3035 |
|
|
BX_SMF BX_INSF_TYPE VPSHLB_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3036 |
|
|
BX_SMF BX_INSF_TYPE VPSHLW_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3037 |
|
|
BX_SMF BX_INSF_TYPE VPSHLD_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3038 |
|
|
BX_SMF BX_INSF_TYPE VPSHLQ_VdqWdqHdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3039 |
|
|
BX_SMF BX_INSF_TYPE VPMACSSWW_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3040 |
|
|
BX_SMF BX_INSF_TYPE VPMACSSWD_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3041 |
|
|
BX_SMF BX_INSF_TYPE VPMACSSDQL_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3042 |
|
|
BX_SMF BX_INSF_TYPE VPMACSSDD_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3043 |
|
|
BX_SMF BX_INSF_TYPE VPMACSSDQH_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3044 |
|
|
BX_SMF BX_INSF_TYPE VPMACSWW_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3045 |
|
|
BX_SMF BX_INSF_TYPE VPMACSWD_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3046 |
|
|
BX_SMF BX_INSF_TYPE VPMACSDQL_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3047 |
|
|
BX_SMF BX_INSF_TYPE VPMACSDD_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3048 |
|
|
BX_SMF BX_INSF_TYPE VPMACSDQH_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3049 |
|
|
BX_SMF BX_INSF_TYPE VPMADCSSWD_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3050 |
|
|
BX_SMF BX_INSF_TYPE VPMADCSWD_VdqHdqWdqVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3051 |
|
|
BX_SMF BX_INSF_TYPE VPROTB_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3052 |
|
|
BX_SMF BX_INSF_TYPE VPROTW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3053 |
|
|
BX_SMF BX_INSF_TYPE VPROTD_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3054 |
|
|
BX_SMF BX_INSF_TYPE VPROTQ_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3055 |
|
|
BX_SMF BX_INSF_TYPE VPCOMB_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3056 |
|
|
BX_SMF BX_INSF_TYPE VPCOMW_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3057 |
|
|
BX_SMF BX_INSF_TYPE VPCOMD_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3058 |
|
|
BX_SMF BX_INSF_TYPE VPCOMQ_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3059 |
|
|
BX_SMF BX_INSF_TYPE VPCOMUB_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3060 |
|
|
BX_SMF BX_INSF_TYPE VPCOMUW_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3061 |
|
|
BX_SMF BX_INSF_TYPE VPCOMUD_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3062 |
|
|
BX_SMF BX_INSF_TYPE VPCOMUQ_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3063 |
|
|
BX_SMF BX_INSF_TYPE VFRCZPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3064 |
|
|
BX_SMF BX_INSF_TYPE VFRCZPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3065 |
|
|
BX_SMF BX_INSF_TYPE VFRCZSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3066 |
|
|
BX_SMF BX_INSF_TYPE VFRCZSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3067 |
|
|
BX_SMF BX_INSF_TYPE VPHADDBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3068 |
|
|
BX_SMF BX_INSF_TYPE VPHADDBD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3069 |
|
|
BX_SMF BX_INSF_TYPE VPHADDBQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3070 |
|
|
BX_SMF BX_INSF_TYPE VPHADDWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3071 |
|
|
BX_SMF BX_INSF_TYPE VPHADDWQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3072 |
|
|
BX_SMF BX_INSF_TYPE VPHADDDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3073 |
|
|
BX_SMF BX_INSF_TYPE VPHADDUBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3074 |
|
|
BX_SMF BX_INSF_TYPE VPHADDUBD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3075 |
|
|
BX_SMF BX_INSF_TYPE VPHADDUBQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3076 |
|
|
BX_SMF BX_INSF_TYPE VPHADDUWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3077 |
|
|
BX_SMF BX_INSF_TYPE VPHADDUWQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3078 |
|
|
BX_SMF BX_INSF_TYPE VPHADDUDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3079 |
|
|
BX_SMF BX_INSF_TYPE VPHSUBBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3080 |
|
|
BX_SMF BX_INSF_TYPE VPHSUBWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3081 |
|
|
BX_SMF BX_INSF_TYPE VPHSUBDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3082 |
|
|
BX_SMF BX_INSF_TYPE VPERMIL2PS_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3083 |
|
|
BX_SMF BX_INSF_TYPE VPERMIL2PD_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3084 |
|
|
/* XOP (AMD) */
|
3085 |
|
|
|
3086 |
|
|
/* TBM (AMD) */
|
3087 |
|
|
BX_SMF BX_INSF_TYPE BEXTR_GdEdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3088 |
|
|
BX_SMF BX_INSF_TYPE BLCFILL_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3089 |
|
|
BX_SMF BX_INSF_TYPE BLCI_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3090 |
|
|
BX_SMF BX_INSF_TYPE BLCIC_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3091 |
|
|
BX_SMF BX_INSF_TYPE BLCMSK_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3092 |
|
|
BX_SMF BX_INSF_TYPE BLCS_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3093 |
|
|
BX_SMF BX_INSF_TYPE BLSFILL_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3094 |
|
|
BX_SMF BX_INSF_TYPE BLSIC_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3095 |
|
|
BX_SMF BX_INSF_TYPE T1MSKC_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3096 |
|
|
BX_SMF BX_INSF_TYPE TZMSK_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3097 |
|
|
|
3098 |
|
|
BX_SMF BX_INSF_TYPE BEXTR_GqEqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3099 |
|
|
BX_SMF BX_INSF_TYPE BLCFILL_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3100 |
|
|
BX_SMF BX_INSF_TYPE BLCI_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3101 |
|
|
BX_SMF BX_INSF_TYPE BLCIC_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3102 |
|
|
BX_SMF BX_INSF_TYPE BLCMSK_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3103 |
|
|
BX_SMF BX_INSF_TYPE BLCS_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3104 |
|
|
BX_SMF BX_INSF_TYPE BLSFILL_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3105 |
|
|
BX_SMF BX_INSF_TYPE BLSIC_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3106 |
|
|
BX_SMF BX_INSF_TYPE T1MSKC_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3107 |
|
|
BX_SMF BX_INSF_TYPE TZMSK_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3108 |
|
|
/* TBM (AMD) */
|
3109 |
|
|
#endif
|
3110 |
|
|
|
3111 |
|
|
BX_SMF BX_INSF_TYPE LZCNT_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3112 |
|
|
BX_SMF BX_INSF_TYPE LZCNT_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3113 |
|
|
#if BX_SUPPORT_X86_64
|
3114 |
|
|
BX_SMF BX_INSF_TYPE LZCNT_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3115 |
|
|
#endif
|
3116 |
|
|
|
3117 |
|
|
/* BMI - TZCNT */
|
3118 |
|
|
BX_SMF BX_INSF_TYPE TZCNT_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3119 |
|
|
BX_SMF BX_INSF_TYPE TZCNT_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3120 |
|
|
#if BX_SUPPORT_X86_64
|
3121 |
|
|
BX_SMF BX_INSF_TYPE TZCNT_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3122 |
|
|
#endif
|
3123 |
|
|
/* BMI - TZCNT */
|
3124 |
|
|
|
3125 |
|
|
/* SSE4A */
|
3126 |
|
|
BX_SMF BX_INSF_TYPE EXTRQ_UdqIbIb(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
3127 |
|
|
BX_SMF BX_INSF_TYPE EXTRQ_VdqUq(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
3128 |
|
|
BX_SMF BX_INSF_TYPE INSERTQ_VdqUqIbIb(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
3129 |
|
|
BX_SMF BX_INSF_TYPE INSERTQ_VdqUdq(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
3130 |
|
|
/* SSE4A */
|
3131 |
|
|
|
3132 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG8B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3133 |
|
|
BX_SMF BX_INSF_TYPE RETnear32_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3134 |
|
|
BX_SMF BX_INSF_TYPE RETnear32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3135 |
|
|
BX_SMF BX_INSF_TYPE RETnear16_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3136 |
|
|
BX_SMF BX_INSF_TYPE RETnear16(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3137 |
|
|
BX_SMF BX_INSF_TYPE RETfar32_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3138 |
|
|
BX_SMF BX_INSF_TYPE RETfar16_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3139 |
|
|
|
3140 |
|
|
BX_SMF BX_INSF_TYPE XADD_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3141 |
|
|
BX_SMF BX_INSF_TYPE XADD_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3142 |
|
|
BX_SMF BX_INSF_TYPE XADD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3143 |
|
|
|
3144 |
|
|
BX_SMF BX_INSF_TYPE XADD_EbGbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3145 |
|
|
BX_SMF BX_INSF_TYPE XADD_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3146 |
|
|
BX_SMF BX_INSF_TYPE XADD_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3147 |
|
|
|
3148 |
|
|
BX_SMF BX_INSF_TYPE CMOVO_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3149 |
|
|
BX_SMF BX_INSF_TYPE CMOVNO_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3150 |
|
|
BX_SMF BX_INSF_TYPE CMOVB_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3151 |
|
|
BX_SMF BX_INSF_TYPE CMOVNB_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3152 |
|
|
BX_SMF BX_INSF_TYPE CMOVZ_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3153 |
|
|
BX_SMF BX_INSF_TYPE CMOVNZ_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3154 |
|
|
BX_SMF BX_INSF_TYPE CMOVBE_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3155 |
|
|
BX_SMF BX_INSF_TYPE CMOVNBE_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3156 |
|
|
BX_SMF BX_INSF_TYPE CMOVS_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3157 |
|
|
BX_SMF BX_INSF_TYPE CMOVNS_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3158 |
|
|
BX_SMF BX_INSF_TYPE CMOVP_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3159 |
|
|
BX_SMF BX_INSF_TYPE CMOVNP_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3160 |
|
|
BX_SMF BX_INSF_TYPE CMOVL_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3161 |
|
|
BX_SMF BX_INSF_TYPE CMOVNL_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3162 |
|
|
BX_SMF BX_INSF_TYPE CMOVLE_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3163 |
|
|
BX_SMF BX_INSF_TYPE CMOVNLE_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3164 |
|
|
|
3165 |
|
|
BX_SMF BX_INSF_TYPE CMOVO_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3166 |
|
|
BX_SMF BX_INSF_TYPE CMOVNO_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3167 |
|
|
BX_SMF BX_INSF_TYPE CMOVB_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3168 |
|
|
BX_SMF BX_INSF_TYPE CMOVNB_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3169 |
|
|
BX_SMF BX_INSF_TYPE CMOVZ_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3170 |
|
|
BX_SMF BX_INSF_TYPE CMOVNZ_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3171 |
|
|
BX_SMF BX_INSF_TYPE CMOVBE_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3172 |
|
|
BX_SMF BX_INSF_TYPE CMOVNBE_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3173 |
|
|
BX_SMF BX_INSF_TYPE CMOVS_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3174 |
|
|
BX_SMF BX_INSF_TYPE CMOVNS_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3175 |
|
|
BX_SMF BX_INSF_TYPE CMOVP_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3176 |
|
|
BX_SMF BX_INSF_TYPE CMOVNP_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3177 |
|
|
BX_SMF BX_INSF_TYPE CMOVL_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3178 |
|
|
BX_SMF BX_INSF_TYPE CMOVNL_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3179 |
|
|
BX_SMF BX_INSF_TYPE CMOVLE_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3180 |
|
|
BX_SMF BX_INSF_TYPE CMOVNLE_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3181 |
|
|
|
3182 |
|
|
BX_SMF BX_INSF_TYPE CWDE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3183 |
|
|
BX_SMF BX_INSF_TYPE CDQ(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3184 |
|
|
|
3185 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3186 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3187 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3188 |
|
|
|
3189 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EbGbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3190 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3191 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3192 |
|
|
|
3193 |
|
|
BX_SMF BX_INSF_TYPE MUL_AXEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3194 |
|
|
BX_SMF BX_INSF_TYPE IMUL_AXEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3195 |
|
|
BX_SMF BX_INSF_TYPE DIV_AXEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3196 |
|
|
BX_SMF BX_INSF_TYPE IDIV_AXEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3197 |
|
|
BX_SMF BX_INSF_TYPE IMUL_GwEwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3198 |
|
|
BX_SMF BX_INSF_TYPE IMUL_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3199 |
|
|
|
3200 |
|
|
BX_SMF BX_INSF_TYPE NOP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3201 |
|
|
BX_SMF BX_INSF_TYPE PAUSE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3202 |
|
|
BX_SMF BX_INSF_TYPE MOV_RLIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3203 |
|
|
BX_SMF BX_INSF_TYPE MOV_RHIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3204 |
|
|
BX_SMF BX_INSF_TYPE MOV_RXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3205 |
|
|
BX_SMF BX_INSF_TYPE MOV_ERXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3206 |
|
|
BX_SMF BX_INSF_TYPE INC_RX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3207 |
|
|
BX_SMF BX_INSF_TYPE DEC_RX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3208 |
|
|
BX_SMF BX_INSF_TYPE INC_ERX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3209 |
|
|
BX_SMF BX_INSF_TYPE DEC_ERX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3210 |
|
|
BX_SMF BX_INSF_TYPE XCHG_RXAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3211 |
|
|
BX_SMF BX_INSF_TYPE XCHG_ERXEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3212 |
|
|
|
3213 |
|
|
BX_SMF BX_INSF_TYPE PUSH_RX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3214 |
|
|
BX_SMF BX_INSF_TYPE PUSH_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3215 |
|
|
BX_SMF BX_INSF_TYPE PUSH_ERX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3216 |
|
|
BX_SMF BX_INSF_TYPE PUSH_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3217 |
|
|
|
3218 |
|
|
BX_SMF BX_INSF_TYPE POP_RX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3219 |
|
|
BX_SMF BX_INSF_TYPE POP_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3220 |
|
|
BX_SMF BX_INSF_TYPE POP_ERX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3221 |
|
|
BX_SMF BX_INSF_TYPE POP_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3222 |
|
|
|
3223 |
|
|
BX_SMF BX_INSF_TYPE POPCNT_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3224 |
|
|
BX_SMF BX_INSF_TYPE POPCNT_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3225 |
|
|
#if BX_SUPPORT_X86_64
|
3226 |
|
|
BX_SMF BX_INSF_TYPE POPCNT_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3227 |
|
|
#endif
|
3228 |
|
|
|
3229 |
|
|
BX_SMF BX_INSF_TYPE ADCX_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3230 |
|
|
BX_SMF BX_INSF_TYPE ADOX_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3231 |
|
|
#if BX_SUPPORT_X86_64
|
3232 |
|
|
BX_SMF BX_INSF_TYPE ADCX_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3233 |
|
|
BX_SMF BX_INSF_TYPE ADOX_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3234 |
|
|
#endif
|
3235 |
|
|
|
3236 |
|
|
// SMAP
|
3237 |
|
|
BX_SMF BX_INSF_TYPE CLAC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3238 |
|
|
BX_SMF BX_INSF_TYPE STAC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3239 |
|
|
// SMAP
|
3240 |
|
|
|
3241 |
|
|
// RDRAND/RDSEED
|
3242 |
|
|
BX_SMF BX_INSF_TYPE RDRAND_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3243 |
|
|
BX_SMF BX_INSF_TYPE RDRAND_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3244 |
|
|
#if BX_SUPPORT_X86_64
|
3245 |
|
|
BX_SMF BX_INSF_TYPE RDRAND_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3246 |
|
|
#endif
|
3247 |
|
|
|
3248 |
|
|
BX_SMF BX_INSF_TYPE RDSEED_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3249 |
|
|
BX_SMF BX_INSF_TYPE RDSEED_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3250 |
|
|
#if BX_SUPPORT_X86_64
|
3251 |
|
|
BX_SMF BX_INSF_TYPE RDSEED_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3252 |
|
|
#endif
|
3253 |
|
|
|
3254 |
|
|
#if BX_SUPPORT_X86_64
|
3255 |
|
|
// 64 bit extensions
|
3256 |
|
|
BX_SMF BX_INSF_TYPE ADD_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3257 |
|
|
BX_SMF BX_INSF_TYPE OR_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3258 |
|
|
BX_SMF BX_INSF_TYPE ADC_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3259 |
|
|
BX_SMF BX_INSF_TYPE SBB_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3260 |
|
|
BX_SMF BX_INSF_TYPE AND_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3261 |
|
|
BX_SMF BX_INSF_TYPE SUB_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3262 |
|
|
BX_SMF BX_INSF_TYPE XOR_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3263 |
|
|
BX_SMF BX_INSF_TYPE CMP_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3264 |
|
|
|
3265 |
|
|
BX_SMF BX_INSF_TYPE ADD_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3266 |
|
|
BX_SMF BX_INSF_TYPE OR_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3267 |
|
|
BX_SMF BX_INSF_TYPE ADC_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3268 |
|
|
BX_SMF BX_INSF_TYPE SBB_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3269 |
|
|
BX_SMF BX_INSF_TYPE AND_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3270 |
|
|
BX_SMF BX_INSF_TYPE SUB_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3271 |
|
|
BX_SMF BX_INSF_TYPE XOR_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3272 |
|
|
BX_SMF BX_INSF_TYPE CMP_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3273 |
|
|
|
3274 |
|
|
BX_SMF BX_INSF_TYPE ADD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3275 |
|
|
BX_SMF BX_INSF_TYPE OR_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3276 |
|
|
BX_SMF BX_INSF_TYPE ADC_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3277 |
|
|
BX_SMF BX_INSF_TYPE SBB_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3278 |
|
|
BX_SMF BX_INSF_TYPE AND_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3279 |
|
|
BX_SMF BX_INSF_TYPE SUB_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3280 |
|
|
BX_SMF BX_INSF_TYPE XOR_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3281 |
|
|
BX_SMF BX_INSF_TYPE CMP_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3282 |
|
|
|
3283 |
|
|
BX_SMF BX_INSF_TYPE ADD_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3284 |
|
|
BX_SMF BX_INSF_TYPE OR_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3285 |
|
|
BX_SMF BX_INSF_TYPE ADC_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3286 |
|
|
BX_SMF BX_INSF_TYPE SBB_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3287 |
|
|
BX_SMF BX_INSF_TYPE AND_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3288 |
|
|
BX_SMF BX_INSF_TYPE SUB_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3289 |
|
|
BX_SMF BX_INSF_TYPE XOR_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3290 |
|
|
BX_SMF BX_INSF_TYPE CMP_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3291 |
|
|
|
3292 |
|
|
BX_SMF BX_INSF_TYPE ADD_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3293 |
|
|
BX_SMF BX_INSF_TYPE OR_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3294 |
|
|
BX_SMF BX_INSF_TYPE ADC_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3295 |
|
|
BX_SMF BX_INSF_TYPE SBB_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3296 |
|
|
BX_SMF BX_INSF_TYPE AND_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3297 |
|
|
BX_SMF BX_INSF_TYPE SUB_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3298 |
|
|
BX_SMF BX_INSF_TYPE XOR_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3299 |
|
|
BX_SMF BX_INSF_TYPE CMP_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3300 |
|
|
|
3301 |
|
|
BX_SMF BX_INSF_TYPE TEST_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3302 |
|
|
BX_SMF BX_INSF_TYPE TEST_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3303 |
|
|
BX_SMF BX_INSF_TYPE TEST_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3304 |
|
|
|
3305 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3306 |
|
|
BX_SMF BX_INSF_TYPE XCHG_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3307 |
|
|
|
3308 |
|
|
BX_SMF BX_INSF_TYPE LEA_GqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3309 |
|
|
|
3310 |
|
|
BX_SMF BX_INSF_TYPE MOV_RAXOq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3311 |
|
|
BX_SMF BX_INSF_TYPE MOV_OqRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3312 |
|
|
BX_SMF BX_INSF_TYPE MOV_EAXOq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3313 |
|
|
BX_SMF BX_INSF_TYPE MOV_OqEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3314 |
|
|
BX_SMF BX_INSF_TYPE MOV_AXOq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3315 |
|
|
BX_SMF BX_INSF_TYPE MOV_OqAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3316 |
|
|
BX_SMF BX_INSF_TYPE MOV_ALOq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3317 |
|
|
BX_SMF BX_INSF_TYPE MOV_OqAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3318 |
|
|
|
3319 |
|
|
BX_SMF BX_INSF_TYPE MOV_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3320 |
|
|
BX_SMF BX_INSF_TYPE MOV_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3321 |
|
|
BX_SMF BX_INSF_TYPE MOV_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3322 |
|
|
BX_SMF BX_INSF_TYPE MOV_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3323 |
|
|
BX_SMF BX_INSF_TYPE MOV_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3324 |
|
|
|
3325 |
|
|
BX_SMF BX_INSF_TYPE MOV64S_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3326 |
|
|
BX_SMF BX_INSF_TYPE MOV64S_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3327 |
|
|
|
3328 |
|
|
// repeatable instructions
|
3329 |
|
|
BX_SMF BX_INSF_TYPE REP_MOVSQ_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3330 |
|
|
BX_SMF BX_INSF_TYPE REP_CMPSQ_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3331 |
|
|
BX_SMF BX_INSF_TYPE REP_STOSQ_YqRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3332 |
|
|
BX_SMF BX_INSF_TYPE REP_LODSQ_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3333 |
|
|
BX_SMF BX_INSF_TYPE REP_SCASQ_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3334 |
|
|
|
3335 |
|
|
// qualified by address size
|
3336 |
|
|
BX_SMF void CMPSB64_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3337 |
|
|
BX_SMF void CMPSW64_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3338 |
|
|
BX_SMF void CMPSD64_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3339 |
|
|
BX_SMF void SCASB64_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3340 |
|
|
BX_SMF void SCASW64_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3341 |
|
|
BX_SMF void SCASD64_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3342 |
|
|
BX_SMF void LODSB64_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3343 |
|
|
BX_SMF void LODSW64_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3344 |
|
|
BX_SMF void LODSD64_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3345 |
|
|
BX_SMF void STOSB64_YbAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3346 |
|
|
BX_SMF void STOSW64_YwAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3347 |
|
|
BX_SMF void STOSD64_YdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3348 |
|
|
BX_SMF void MOVSB64_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3349 |
|
|
BX_SMF void MOVSW64_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3350 |
|
|
BX_SMF void MOVSD64_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3351 |
|
|
|
3352 |
|
|
BX_SMF void CMPSQ32_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3353 |
|
|
BX_SMF void CMPSQ64_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3354 |
|
|
BX_SMF void SCASQ32_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3355 |
|
|
BX_SMF void SCASQ64_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3356 |
|
|
BX_SMF void LODSQ32_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3357 |
|
|
BX_SMF void LODSQ64_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3358 |
|
|
BX_SMF void STOSQ32_YqRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3359 |
|
|
BX_SMF void STOSQ64_YqRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3360 |
|
|
BX_SMF void MOVSQ32_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3361 |
|
|
BX_SMF void MOVSQ64_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3362 |
|
|
|
3363 |
|
|
BX_SMF void INSB64_YbDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3364 |
|
|
BX_SMF void INSW64_YwDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3365 |
|
|
BX_SMF void INSD64_YdDX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3366 |
|
|
|
3367 |
|
|
BX_SMF void OUTSB64_DXXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3368 |
|
|
BX_SMF void OUTSW64_DXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3369 |
|
|
BX_SMF void OUTSD64_DXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3370 |
|
|
|
3371 |
|
|
BX_SMF BX_INSF_TYPE CALL_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3372 |
|
|
BX_SMF BX_INSF_TYPE JMP_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3373 |
|
|
|
3374 |
|
|
BX_SMF BX_INSF_TYPE JO_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3375 |
|
|
BX_SMF BX_INSF_TYPE JNO_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3376 |
|
|
BX_SMF BX_INSF_TYPE JB_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3377 |
|
|
BX_SMF BX_INSF_TYPE JNB_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3378 |
|
|
BX_SMF BX_INSF_TYPE JZ_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3379 |
|
|
BX_SMF BX_INSF_TYPE JNZ_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3380 |
|
|
BX_SMF BX_INSF_TYPE JBE_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3381 |
|
|
BX_SMF BX_INSF_TYPE JNBE_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3382 |
|
|
BX_SMF BX_INSF_TYPE JS_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3383 |
|
|
BX_SMF BX_INSF_TYPE JNS_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3384 |
|
|
BX_SMF BX_INSF_TYPE JP_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3385 |
|
|
BX_SMF BX_INSF_TYPE JNP_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3386 |
|
|
BX_SMF BX_INSF_TYPE JL_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3387 |
|
|
BX_SMF BX_INSF_TYPE JNL_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3388 |
|
|
BX_SMF BX_INSF_TYPE JLE_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3389 |
|
|
BX_SMF BX_INSF_TYPE JNLE_Jq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3390 |
|
|
|
3391 |
|
|
BX_SMF BX_INSF_TYPE ENTER64_IwIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3392 |
|
|
BX_SMF BX_INSF_TYPE LEAVE64(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3393 |
|
|
BX_SMF BX_INSF_TYPE IRET64(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3394 |
|
|
|
3395 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR0Rq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3396 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR2Rq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3397 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR3Rq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3398 |
|
|
BX_SMF BX_INSF_TYPE MOV_CR4Rq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3399 |
|
|
BX_SMF BX_INSF_TYPE MOV_RqCR0(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3400 |
|
|
BX_SMF BX_INSF_TYPE MOV_RqCR2(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3401 |
|
|
BX_SMF BX_INSF_TYPE MOV_RqCR3(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3402 |
|
|
BX_SMF BX_INSF_TYPE MOV_RqCR4(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3403 |
|
|
BX_SMF BX_INSF_TYPE MOV_DqRq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3404 |
|
|
BX_SMF BX_INSF_TYPE MOV_RqDq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3405 |
|
|
|
3406 |
|
|
BX_SMF BX_INSF_TYPE SHLD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3407 |
|
|
BX_SMF BX_INSF_TYPE SHLD_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3408 |
|
|
BX_SMF BX_INSF_TYPE SHRD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3409 |
|
|
BX_SMF BX_INSF_TYPE SHRD_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3410 |
|
|
|
3411 |
|
|
BX_SMF BX_INSF_TYPE MOV64_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3412 |
|
|
BX_SMF BX_INSF_TYPE MOV64_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3413 |
|
|
|
3414 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GqEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3415 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GqEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3416 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GqEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3417 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GqEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3418 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GqEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3419 |
|
|
|
3420 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GqEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3421 |
|
|
BX_SMF BX_INSF_TYPE MOVZX_GqEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3422 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GqEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3423 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GqEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3424 |
|
|
BX_SMF BX_INSF_TYPE MOVSX_GqEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3425 |
|
|
|
3426 |
|
|
BX_SMF BX_INSF_TYPE BSF_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3427 |
|
|
BX_SMF BX_INSF_TYPE BSR_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3428 |
|
|
|
3429 |
|
|
BX_SMF BX_INSF_TYPE BT_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3430 |
|
|
BX_SMF BX_INSF_TYPE BTS_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3431 |
|
|
BX_SMF BX_INSF_TYPE BTR_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3432 |
|
|
BX_SMF BX_INSF_TYPE BTC_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3433 |
|
|
|
3434 |
|
|
BX_SMF BX_INSF_TYPE BT_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3435 |
|
|
BX_SMF BX_INSF_TYPE BTS_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3436 |
|
|
BX_SMF BX_INSF_TYPE BTR_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3437 |
|
|
BX_SMF BX_INSF_TYPE BTC_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3438 |
|
|
|
3439 |
|
|
BX_SMF BX_INSF_TYPE BT_EqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3440 |
|
|
BX_SMF BX_INSF_TYPE BTS_EqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3441 |
|
|
BX_SMF BX_INSF_TYPE BTR_EqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3442 |
|
|
BX_SMF BX_INSF_TYPE BTC_EqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3443 |
|
|
|
3444 |
|
|
BX_SMF BX_INSF_TYPE BT_EqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3445 |
|
|
BX_SMF BX_INSF_TYPE BTS_EqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3446 |
|
|
BX_SMF BX_INSF_TYPE BTR_EqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3447 |
|
|
BX_SMF BX_INSF_TYPE BTC_EqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3448 |
|
|
|
3449 |
|
|
BX_SMF BX_INSF_TYPE BSWAP_RRX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3450 |
|
|
|
3451 |
|
|
BX_SMF BX_INSF_TYPE ROL_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3452 |
|
|
BX_SMF BX_INSF_TYPE ROR_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3453 |
|
|
BX_SMF BX_INSF_TYPE RCL_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3454 |
|
|
BX_SMF BX_INSF_TYPE RCR_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3455 |
|
|
BX_SMF BX_INSF_TYPE SHL_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3456 |
|
|
BX_SMF BX_INSF_TYPE SHR_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3457 |
|
|
BX_SMF BX_INSF_TYPE SAR_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3458 |
|
|
|
3459 |
|
|
BX_SMF BX_INSF_TYPE ROL_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3460 |
|
|
BX_SMF BX_INSF_TYPE ROR_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3461 |
|
|
BX_SMF BX_INSF_TYPE RCL_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3462 |
|
|
BX_SMF BX_INSF_TYPE RCR_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3463 |
|
|
BX_SMF BX_INSF_TYPE SHL_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3464 |
|
|
BX_SMF BX_INSF_TYPE SHR_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3465 |
|
|
BX_SMF BX_INSF_TYPE SAR_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3466 |
|
|
|
3467 |
|
|
BX_SMF BX_INSF_TYPE NOT_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3468 |
|
|
BX_SMF BX_INSF_TYPE NEG_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3469 |
|
|
BX_SMF BX_INSF_TYPE NOT_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3470 |
|
|
BX_SMF BX_INSF_TYPE NEG_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3471 |
|
|
|
3472 |
|
|
BX_SMF BX_INSF_TYPE TEST_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3473 |
|
|
BX_SMF BX_INSF_TYPE TEST_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3474 |
|
|
|
3475 |
|
|
BX_SMF BX_INSF_TYPE MUL_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3476 |
|
|
BX_SMF BX_INSF_TYPE IMUL_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3477 |
|
|
BX_SMF BX_INSF_TYPE DIV_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3478 |
|
|
BX_SMF BX_INSF_TYPE IDIV_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3479 |
|
|
BX_SMF BX_INSF_TYPE IMUL_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3480 |
|
|
BX_SMF BX_INSF_TYPE IMUL_GqEqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3481 |
|
|
|
3482 |
|
|
BX_SMF BX_INSF_TYPE INC_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3483 |
|
|
BX_SMF BX_INSF_TYPE DEC_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3484 |
|
|
BX_SMF BX_INSF_TYPE INC_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3485 |
|
|
BX_SMF BX_INSF_TYPE DEC_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3486 |
|
|
BX_SMF BX_INSF_TYPE CALL_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3487 |
|
|
BX_SMF BX_INSF_TYPE CALL64_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3488 |
|
|
BX_SMF BX_INSF_TYPE JMP_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3489 |
|
|
BX_SMF BX_INSF_TYPE JMP64_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3490 |
|
|
BX_SMF BX_INSF_TYPE PUSHF_Fq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3491 |
|
|
BX_SMF BX_INSF_TYPE POPF_Fq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3492 |
|
|
|
3493 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3494 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3495 |
|
|
|
3496 |
|
|
BX_SMF BX_INSF_TYPE CDQE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3497 |
|
|
BX_SMF BX_INSF_TYPE CQO(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3498 |
|
|
|
3499 |
|
|
BX_SMF BX_INSF_TYPE XADD_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3500 |
|
|
BX_SMF BX_INSF_TYPE XADD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3501 |
|
|
|
3502 |
|
|
BX_SMF BX_INSF_TYPE RETnear64_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3503 |
|
|
BX_SMF BX_INSF_TYPE RETnear64(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3504 |
|
|
BX_SMF BX_INSF_TYPE RETfar64_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3505 |
|
|
|
3506 |
|
|
BX_SMF BX_INSF_TYPE CMOVO_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3507 |
|
|
BX_SMF BX_INSF_TYPE CMOVNO_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3508 |
|
|
BX_SMF BX_INSF_TYPE CMOVB_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3509 |
|
|
BX_SMF BX_INSF_TYPE CMOVNB_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3510 |
|
|
BX_SMF BX_INSF_TYPE CMOVZ_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3511 |
|
|
BX_SMF BX_INSF_TYPE CMOVNZ_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3512 |
|
|
BX_SMF BX_INSF_TYPE CMOVBE_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3513 |
|
|
BX_SMF BX_INSF_TYPE CMOVNBE_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3514 |
|
|
BX_SMF BX_INSF_TYPE CMOVS_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3515 |
|
|
BX_SMF BX_INSF_TYPE CMOVNS_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3516 |
|
|
BX_SMF BX_INSF_TYPE CMOVP_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3517 |
|
|
BX_SMF BX_INSF_TYPE CMOVNP_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3518 |
|
|
BX_SMF BX_INSF_TYPE CMOVL_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3519 |
|
|
BX_SMF BX_INSF_TYPE CMOVNL_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3520 |
|
|
BX_SMF BX_INSF_TYPE CMOVLE_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3521 |
|
|
BX_SMF BX_INSF_TYPE CMOVNLE_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3522 |
|
|
|
3523 |
|
|
BX_SMF BX_INSF_TYPE MOV_RRXIq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3524 |
|
|
BX_SMF BX_INSF_TYPE PUSH_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3525 |
|
|
BX_SMF BX_INSF_TYPE PUSH_RRX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3526 |
|
|
BX_SMF BX_INSF_TYPE POP_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3527 |
|
|
BX_SMF BX_INSF_TYPE POP_RRX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3528 |
|
|
BX_SMF BX_INSF_TYPE XCHG_RRXRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3529 |
|
|
|
3530 |
|
|
BX_SMF BX_INSF_TYPE PUSH64_Id(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3531 |
|
|
BX_SMF BX_INSF_TYPE PUSH64_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3532 |
|
|
BX_SMF BX_INSF_TYPE POP64_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3533 |
|
|
|
3534 |
|
|
BX_SMF BX_INSF_TYPE LSS_GqMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3535 |
|
|
BX_SMF BX_INSF_TYPE LFS_GqMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3536 |
|
|
BX_SMF BX_INSF_TYPE LGS_GqMp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3537 |
|
|
|
3538 |
|
|
BX_SMF BX_INSF_TYPE SGDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3539 |
|
|
BX_SMF BX_INSF_TYPE SIDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3540 |
|
|
BX_SMF BX_INSF_TYPE LGDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3541 |
|
|
BX_SMF BX_INSF_TYPE LIDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3542 |
|
|
|
3543 |
|
|
BX_SMF BX_INSF_TYPE CMPXCHG16B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3544 |
|
|
|
3545 |
|
|
BX_SMF BX_INSF_TYPE SWAPGS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3546 |
|
|
BX_SMF BX_INSF_TYPE RDFSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3547 |
|
|
BX_SMF BX_INSF_TYPE RDGSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3548 |
|
|
BX_SMF BX_INSF_TYPE WRFSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3549 |
|
|
BX_SMF BX_INSF_TYPE WRGSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3550 |
|
|
|
3551 |
|
|
BX_SMF BX_INSF_TYPE LOOPNE64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3552 |
|
|
BX_SMF BX_INSF_TYPE LOOPE64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3553 |
|
|
BX_SMF BX_INSF_TYPE LOOP64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3554 |
|
|
BX_SMF BX_INSF_TYPE JRCXZ_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3555 |
|
|
|
3556 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_EqPqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3557 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_EqVqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3558 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_PqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3559 |
|
|
BX_SMF BX_INSF_TYPE MOVQ_VdqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3560 |
|
|
|
3561 |
|
|
BX_SMF BX_INSF_TYPE CVTSI2SS_VssEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3562 |
|
|
BX_SMF BX_INSF_TYPE CVTSI2SD_VsdEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3563 |
|
|
BX_SMF BX_INSF_TYPE CVTTSD2SI_GqWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3564 |
|
|
BX_SMF BX_INSF_TYPE CVTTSS2SI_GqWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3565 |
|
|
BX_SMF BX_INSF_TYPE CVTSD2SI_GqWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3566 |
|
|
BX_SMF BX_INSF_TYPE CVTSS2SI_GqWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3567 |
|
|
#endif // #if BX_SUPPORT_X86_64
|
3568 |
|
|
|
3569 |
|
|
BX_SMF BX_INSF_TYPE RDTSCP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3570 |
|
|
|
3571 |
|
|
BX_SMF BX_INSF_TYPE INVLPG(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3572 |
|
|
BX_SMF BX_INSF_TYPE RSM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3573 |
|
|
|
3574 |
|
|
BX_SMF BX_INSF_TYPE WRMSR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3575 |
|
|
BX_SMF BX_INSF_TYPE RDTSC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3576 |
|
|
BX_SMF BX_INSF_TYPE RDPMC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3577 |
|
|
BX_SMF BX_INSF_TYPE RDMSR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3578 |
|
|
BX_SMF BX_INSF_TYPE SYSENTER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3579 |
|
|
BX_SMF BX_INSF_TYPE SYSEXIT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3580 |
|
|
|
3581 |
|
|
BX_SMF BX_INSF_TYPE MONITOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3582 |
|
|
BX_SMF BX_INSF_TYPE MWAIT(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3583 |
|
|
|
3584 |
|
|
BX_SMF BX_INSF_TYPE UndefinedOpcode(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3585 |
|
|
BX_SMF BX_INSF_TYPE BxError(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3586 |
|
|
#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
|
3587 |
|
|
BX_SMF BX_INSF_TYPE BxEndTrace(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3588 |
|
|
#endif
|
3589 |
|
|
#if BX_CPU_LEVEL >= 6
|
3590 |
|
|
BX_SMF BX_INSF_TYPE BxNoSSE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3591 |
|
|
BX_SMF BX_INSF_TYPE BxNoAVX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3592 |
|
|
#endif
|
3593 |
|
|
|
3594 |
|
|
BX_SMF bx_address BxResolve16BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3595 |
|
|
BX_SMF bx_address BxResolve32Base(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3596 |
|
|
BX_SMF bx_address BxResolve32BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3597 |
|
|
#if BX_SUPPORT_X86_64
|
3598 |
|
|
BX_SMF bx_address BxResolve64Base(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3599 |
|
|
BX_SMF bx_address BxResolve64BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3600 |
|
|
#endif
|
3601 |
|
|
#if BX_SUPPORT_AVX
|
3602 |
|
|
BX_SMF bx_address BxResolveGatherD(bxInstruction_c *, unsigned) BX_CPP_AttrRegparmN(2);
|
3603 |
|
|
BX_SMF bx_address BxResolveGatherQ(bxInstruction_c *, unsigned) BX_CPP_AttrRegparmN(2);
|
3604 |
|
|
#endif
|
3605 |
|
|
// <TAG-CLASS-CPU-END>
|
3606 |
|
|
|
3607 |
|
|
#if BX_DEBUGGER
|
3608 |
|
|
BX_SMF void dbg_take_dma(void);
|
3609 |
|
|
BX_SMF bx_bool dbg_set_eflags(Bit32u val);
|
3610 |
|
|
BX_SMF void dbg_set_eip(bx_address val);
|
3611 |
|
|
BX_SMF bx_bool dbg_get_sreg(bx_dbg_sreg_t *sreg, unsigned sreg_no);
|
3612 |
|
|
BX_SMF bx_bool dbg_set_sreg(unsigned sreg_no, bx_segment_reg_t *sreg);
|
3613 |
|
|
BX_SMF void dbg_get_tr(bx_dbg_sreg_t *sreg);
|
3614 |
|
|
BX_SMF void dbg_get_ldtr(bx_dbg_sreg_t *sreg);
|
3615 |
|
|
BX_SMF void dbg_get_gdtr(bx_dbg_global_sreg_t *sreg);
|
3616 |
|
|
BX_SMF void dbg_get_idtr(bx_dbg_global_sreg_t *sreg);
|
3617 |
|
|
BX_SMF unsigned dbg_query_pending(void);
|
3618 |
|
|
#endif
|
3619 |
|
|
#if BX_DEBUGGER || BX_GDBSTUB
|
3620 |
|
|
BX_SMF bx_bool dbg_instruction_epilog(void);
|
3621 |
|
|
#endif
|
3622 |
|
|
#if BX_DEBUGGER || BX_DISASM || BX_INSTRUMENTATION || BX_GDBSTUB
|
3623 |
|
|
BX_SMF bx_bool dbg_xlate_linear2phy(bx_address linear, bx_phy_address *phy, bx_bool verbose = 0);
|
3624 |
|
|
#if BX_SUPPORT_VMX >= 2
|
3625 |
|
|
BX_SMF bx_bool dbg_translate_guest_physical(bx_phy_address guest_paddr, bx_phy_address *phy, bx_bool verbose = 0);
|
3626 |
|
|
#endif
|
3627 |
|
|
#endif
|
3628 |
|
|
#if BX_LARGE_RAMFILE
|
3629 |
|
|
BX_SMF bx_bool check_addr_in_tlb_buffers(const Bit8u *addr, const Bit8u *end);
|
3630 |
|
|
#endif
|
3631 |
|
|
BX_SMF void atexit(void);
|
3632 |
|
|
|
3633 |
|
|
// now for some ancillary functions...
|
3634 |
|
|
BX_SMF void cpu_loop(void);
|
3635 |
|
|
#if BX_SUPPORT_SMP
|
3636 |
|
|
BX_SMF void cpu_run_trace(void);
|
3637 |
|
|
#endif
|
3638 |
|
|
BX_SMF bx_bool handleAsyncEvent(void);
|
3639 |
|
|
BX_SMF bx_bool handleWaitForEvent(void);
|
3640 |
|
|
BX_SMF void InterruptAcknowledge(void);
|
3641 |
|
|
|
3642 |
|
|
BX_SMF int fetchDecode32(const Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3);
|
3643 |
|
|
#if BX_SUPPORT_X86_64
|
3644 |
|
|
BX_SMF int fetchDecode64(const Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3);
|
3645 |
|
|
#endif
|
3646 |
|
|
BX_SMF void boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *);
|
3647 |
|
|
BX_SMF bxICacheEntry_c *serveICacheMiss(bxICacheEntry_c *entry, Bit32u eipBiased, bx_phy_address pAddr);
|
3648 |
|
|
BX_SMF bxICacheEntry_c* getICacheEntry(void);
|
3649 |
|
|
BX_SMF bx_bool mergeTraces(bxICacheEntry_c *entry, bxInstruction_c *i, bx_phy_address pAddr);
|
3650 |
|
|
#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
|
3651 |
|
|
BX_SMF BX_INSF_TYPE linkTrace(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
3652 |
|
|
#endif
|
3653 |
|
|
BX_SMF void prefetch(void);
|
3654 |
|
|
BX_SMF void updateFetchModeMask(void);
|
3655 |
|
|
BX_SMF BX_CPP_INLINE void invalidate_prefetch_q(void)
|
3656 |
|
|
{
|
3657 |
|
|
BX_CPU_THIS_PTR eipPageWindowSize = 0;
|
3658 |
|
|
}
|
3659 |
|
|
|
3660 |
|
|
BX_SMF BX_CPP_INLINE void invalidate_stack_cache(void)
|
3661 |
|
|
{
|
3662 |
|
|
BX_CPU_THIS_PTR espPageWindowSize = 0;
|
3663 |
|
|
}
|
3664 |
|
|
|
3665 |
|
|
BX_SMF bx_bool write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len) BX_CPP_AttrRegparmN(3);
|
3666 |
|
|
BX_SMF bx_bool read_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len) BX_CPP_AttrRegparmN(3);
|
3667 |
|
|
BX_SMF bx_bool execute_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len) BX_CPP_AttrRegparmN(3);
|
3668 |
|
|
|
3669 |
|
|
BX_SMF Bit8u read_virtual_byte_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3670 |
|
|
BX_SMF Bit16u read_virtual_word_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3671 |
|
|
BX_SMF Bit32u read_virtual_dword_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3672 |
|
|
BX_SMF Bit64u read_virtual_qword_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3673 |
|
|
#if BX_CPU_LEVEL >= 6
|
3674 |
|
|
BX_SMF void read_virtual_xmmword_32(unsigned seg, Bit32u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3675 |
|
|
BX_SMF void read_virtual_xmmword_aligned_32(unsigned seg, Bit32u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3676 |
|
|
#if BX_SUPPORT_AVX
|
3677 |
|
|
BX_SMF void read_virtual_ymmword_32(unsigned seg, Bit32u off, BxPackedAvxRegister *data);
|
3678 |
|
|
BX_SMF void read_virtual_ymmword_aligned_32(unsigned seg, Bit32u off, BxPackedAvxRegister *data);
|
3679 |
|
|
#endif
|
3680 |
|
|
#endif
|
3681 |
|
|
|
3682 |
|
|
BX_SMF void write_virtual_byte_32(unsigned seg, Bit32u offset, Bit8u data) BX_CPP_AttrRegparmN(3);
|
3683 |
|
|
BX_SMF void write_virtual_word_32(unsigned seg, Bit32u offset, Bit16u data) BX_CPP_AttrRegparmN(3);
|
3684 |
|
|
BX_SMF void write_virtual_dword_32(unsigned seg, Bit32u offset, Bit32u data) BX_CPP_AttrRegparmN(3);
|
3685 |
|
|
BX_SMF void write_virtual_qword_32(unsigned seg, Bit32u offset, Bit64u data) BX_CPP_AttrRegparmN(3);
|
3686 |
|
|
#if BX_CPU_LEVEL >= 6
|
3687 |
|
|
BX_SMF void write_virtual_xmmword_32(unsigned seg, Bit32u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3688 |
|
|
BX_SMF void write_virtual_xmmword_aligned_32(unsigned seg, Bit32u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3689 |
|
|
#if BX_SUPPORT_AVX
|
3690 |
|
|
BX_SMF void write_virtual_ymmword_32(unsigned seg, Bit32u off, const BxPackedAvxRegister *data);
|
3691 |
|
|
BX_SMF void write_virtual_ymmword_aligned_32(unsigned seg, Bit32u off, const BxPackedAvxRegister *data);
|
3692 |
|
|
#endif
|
3693 |
|
|
#endif
|
3694 |
|
|
|
3695 |
|
|
BX_SMF Bit8u read_RMW_virtual_byte_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3696 |
|
|
BX_SMF Bit16u read_RMW_virtual_word_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3697 |
|
|
BX_SMF Bit32u read_RMW_virtual_dword_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3698 |
|
|
BX_SMF Bit64u read_RMW_virtual_qword_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
|
3699 |
|
|
|
3700 |
|
|
BX_SMF void write_RMW_virtual_byte(Bit8u val8) BX_CPP_AttrRegparmN(1);
|
3701 |
|
|
BX_SMF void write_RMW_virtual_word(Bit16u val16) BX_CPP_AttrRegparmN(1);
|
3702 |
|
|
BX_SMF void write_RMW_virtual_dword(Bit32u val32) BX_CPP_AttrRegparmN(1);
|
3703 |
|
|
BX_SMF void write_RMW_virtual_qword(Bit64u val64) BX_CPP_AttrRegparmN(1);
|
3704 |
|
|
|
3705 |
|
|
#if BX_SUPPORT_X86_64
|
3706 |
|
|
BX_SMF void write_virtual_byte_64(unsigned seg, Bit64u offset, Bit8u data) BX_CPP_AttrRegparmN(3);
|
3707 |
|
|
BX_SMF void write_virtual_word_64(unsigned seg, Bit64u offset, Bit16u data) BX_CPP_AttrRegparmN(3);
|
3708 |
|
|
BX_SMF void write_virtual_dword_64(unsigned seg, Bit64u offset, Bit32u data) BX_CPP_AttrRegparmN(3);
|
3709 |
|
|
BX_SMF void write_virtual_qword_64(unsigned seg, Bit64u offset, Bit64u data) BX_CPP_AttrRegparmN(3);
|
3710 |
|
|
BX_SMF void write_virtual_xmmword_64(unsigned seg, Bit64u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3711 |
|
|
BX_SMF void write_virtual_xmmword_aligned_64(unsigned seg, Bit64u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3712 |
|
|
#if BX_SUPPORT_AVX
|
3713 |
|
|
BX_SMF void write_virtual_ymmword_64(unsigned seg, Bit64u offset, const BxPackedAvxRegister *data);
|
3714 |
|
|
BX_SMF void write_virtual_ymmword_aligned_64(unsigned seg, Bit64u offset, const BxPackedAvxRegister *data);
|
3715 |
|
|
#endif
|
3716 |
|
|
|
3717 |
|
|
BX_SMF Bit8u read_virtual_byte_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3718 |
|
|
BX_SMF Bit16u read_virtual_word_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3719 |
|
|
BX_SMF Bit32u read_virtual_dword_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3720 |
|
|
BX_SMF Bit64u read_virtual_qword_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3721 |
|
|
BX_SMF void read_virtual_xmmword_64(unsigned seg, Bit64u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3722 |
|
|
BX_SMF void read_virtual_xmmword_aligned_64(unsigned seg, Bit64u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
|
3723 |
|
|
#if BX_SUPPORT_AVX
|
3724 |
|
|
BX_SMF void read_virtual_ymmword_64(unsigned seg, Bit64u offset, BxPackedAvxRegister *data);
|
3725 |
|
|
BX_SMF void read_virtual_ymmword_aligned_64(unsigned seg, Bit64u offset, BxPackedAvxRegister *data);
|
3726 |
|
|
#endif
|
3727 |
|
|
|
3728 |
|
|
BX_SMF Bit8u read_RMW_virtual_byte_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3729 |
|
|
BX_SMF Bit16u read_RMW_virtual_word_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3730 |
|
|
BX_SMF Bit32u read_RMW_virtual_dword_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3731 |
|
|
BX_SMF Bit64u read_RMW_virtual_qword_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
|
3732 |
|
|
#endif
|
3733 |
|
|
|
3734 |
|
|
// write of word/dword to new stack could happen only in legacy mode
|
3735 |
|
|
BX_SMF void write_new_stack_word_32(bx_segment_reg_t *seg, Bit32u offset, unsigned curr_pl, Bit16u data);
|
3736 |
|
|
BX_SMF void write_new_stack_dword_32(bx_segment_reg_t *seg, Bit32u offset, unsigned curr_pl, Bit32u data);
|
3737 |
|
|
BX_SMF void write_new_stack_qword_32(bx_segment_reg_t *seg, Bit32u offset, unsigned curr_pl, Bit64u data);
|
3738 |
|
|
#if BX_SUPPORT_X86_64
|
3739 |
|
|
BX_SMF void write_new_stack_word_64(Bit64u offset, unsigned curr_pl, Bit16u data);
|
3740 |
|
|
BX_SMF void write_new_stack_dword_64(Bit64u offset, unsigned curr_pl, Bit32u data);
|
3741 |
|
|
BX_SMF void write_new_stack_qword_64(Bit64u offset, unsigned curr_pl, Bit64u data);
|
3742 |
|
|
#endif
|
3743 |
|
|
|
3744 |
|
|
#if BX_SUPPORT_X86_64
|
3745 |
|
|
|
3746 |
|
|
// write
|
3747 |
|
|
#define write_virtual_byte(seg, offset, data) \
|
3748 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3749 |
|
|
write_virtual_byte_64(seg, (Bit64u) offset, data) : \
|
3750 |
|
|
write_virtual_byte_32(seg, (Bit32u) offset, data)
|
3751 |
|
|
|
3752 |
|
|
#define write_virtual_word(seg, offset, data) \
|
3753 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3754 |
|
|
write_virtual_word_64(seg, (Bit64u) offset, data) : \
|
3755 |
|
|
write_virtual_word_32(seg, (Bit32u) offset, data)
|
3756 |
|
|
|
3757 |
|
|
#define write_virtual_dword(seg, offset, data) \
|
3758 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3759 |
|
|
write_virtual_dword_64(seg, (Bit64u) offset, data) : \
|
3760 |
|
|
write_virtual_dword_32(seg, (Bit32u) offset, data)
|
3761 |
|
|
|
3762 |
|
|
#define write_virtual_qword(seg, offset, data) \
|
3763 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3764 |
|
|
write_virtual_qword_64(seg, (Bit64u) offset, data) : \
|
3765 |
|
|
write_virtual_qword_32(seg, (Bit32u) offset, data)
|
3766 |
|
|
|
3767 |
|
|
#define write_virtual_xmmword(seg, offset, data) \
|
3768 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3769 |
|
|
write_virtual_xmmword_64(seg, (Bit64u) offset, (const BxPackedXmmRegister*)(data)) : \
|
3770 |
|
|
write_virtual_xmmword_32(seg, (Bit32u) offset, (const BxPackedXmmRegister*)(data))
|
3771 |
|
|
|
3772 |
|
|
#define write_virtual_xmmword_aligned(seg, offset, data) \
|
3773 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3774 |
|
|
write_virtual_xmmword_aligned_64(seg, (Bit64u) offset, (const BxPackedXmmRegister*)(data)) : \
|
3775 |
|
|
write_virtual_xmmword_aligned_32(seg, (Bit32u) offset, (const BxPackedXmmRegister*)(data))
|
3776 |
|
|
|
3777 |
|
|
#if BX_SUPPORT_AVX
|
3778 |
|
|
|
3779 |
|
|
#define write_virtual_ymmword(seg, offset, data) \
|
3780 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3781 |
|
|
write_virtual_ymmword_64(seg, (Bit64u) offset, (const BxPackedAvxRegister*)(data)) : \
|
3782 |
|
|
write_virtual_ymmword_32(seg, (Bit32u) offset, (const BxPackedAvxRegister*)(data))
|
3783 |
|
|
|
3784 |
|
|
#define write_virtual_ymmword_aligned(seg, offset, data) \
|
3785 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3786 |
|
|
write_virtual_ymmword_aligned_64(seg, (Bit64u) offset, (const BxPackedAvxRegister*)(data)) : \
|
3787 |
|
|
write_virtual_ymmword_aligned_32(seg, (Bit32u) offset, (const BxPackedAvxRegister*)(data))
|
3788 |
|
|
|
3789 |
|
|
#endif
|
3790 |
|
|
|
3791 |
|
|
// read
|
3792 |
|
|
#define read_virtual_byte(seg, offset) \
|
3793 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3794 |
|
|
read_virtual_byte_64(seg, (Bit64u) offset) : \
|
3795 |
|
|
read_virtual_byte_32(seg, (Bit32u) offset)
|
3796 |
|
|
|
3797 |
|
|
#define read_virtual_word(seg, offset) \
|
3798 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3799 |
|
|
read_virtual_word_64(seg, (Bit64u) offset) : \
|
3800 |
|
|
read_virtual_word_32(seg, (Bit32u) offset)
|
3801 |
|
|
|
3802 |
|
|
#define read_virtual_dword(seg, offset) \
|
3803 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3804 |
|
|
read_virtual_dword_64(seg, (Bit64u) offset) : \
|
3805 |
|
|
read_virtual_dword_32(seg, (Bit32u) offset)
|
3806 |
|
|
|
3807 |
|
|
#define read_virtual_qword(seg, offset) \
|
3808 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3809 |
|
|
read_virtual_qword_64(seg, (Bit64u) offset) : \
|
3810 |
|
|
read_virtual_qword_32(seg, (Bit32u) offset)
|
3811 |
|
|
|
3812 |
|
|
#define read_virtual_xmmword(seg, offset, data) \
|
3813 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3814 |
|
|
read_virtual_xmmword_64(seg, (Bit64u) offset, (BxPackedXmmRegister*)(data)) : \
|
3815 |
|
|
read_virtual_xmmword_32(seg, (Bit32u) offset, (BxPackedXmmRegister*)(data))
|
3816 |
|
|
|
3817 |
|
|
#define read_virtual_xmmword_aligned(seg, offset, data) \
|
3818 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3819 |
|
|
read_virtual_xmmword_aligned_64(seg, (Bit64u) offset, (BxPackedXmmRegister*)(data)) : \
|
3820 |
|
|
read_virtual_xmmword_aligned_32(seg, (Bit32u) offset, (BxPackedXmmRegister*)(data))
|
3821 |
|
|
|
3822 |
|
|
#if BX_SUPPORT_AVX
|
3823 |
|
|
|
3824 |
|
|
#define read_virtual_ymmword(seg, offset, data) \
|
3825 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3826 |
|
|
read_virtual_ymmword_64(seg, (Bit64u) offset, (BxPackedAvxRegister*)(data)) : \
|
3827 |
|
|
read_virtual_ymmword_32(seg, (Bit32u) offset, (BxPackedAvxRegister*)(data))
|
3828 |
|
|
|
3829 |
|
|
#define read_virtual_ymmword_aligned(seg, offset, data) \
|
3830 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3831 |
|
|
read_virtual_ymmword_aligned_64(seg, (Bit64u) offset, (BxPackedAvxRegister*)(data)) : \
|
3832 |
|
|
read_virtual_ymmword_aligned_32(seg, (Bit32u) offset, (BxPackedAvxRegister*)(data))
|
3833 |
|
|
|
3834 |
|
|
#endif
|
3835 |
|
|
|
3836 |
|
|
// RMW
|
3837 |
|
|
#define read_RMW_virtual_byte(seg, offset) \
|
3838 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3839 |
|
|
read_RMW_virtual_byte_64(seg, (Bit64u) offset) : \
|
3840 |
|
|
read_RMW_virtual_byte_32(seg, (Bit32u) offset)
|
3841 |
|
|
|
3842 |
|
|
#define read_RMW_virtual_word(seg, offset) \
|
3843 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3844 |
|
|
read_RMW_virtual_word_64(seg, (Bit64u) offset) : \
|
3845 |
|
|
read_RMW_virtual_word_32(seg, (Bit32u) offset)
|
3846 |
|
|
|
3847 |
|
|
#define read_RMW_virtual_dword(seg, offset) \
|
3848 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3849 |
|
|
read_RMW_virtual_dword_64(seg, (Bit64u) offset) : \
|
3850 |
|
|
read_RMW_virtual_dword_32(seg, (Bit32u) offset)
|
3851 |
|
|
|
3852 |
|
|
#define read_RMW_virtual_qword(seg, offset) \
|
3853 |
|
|
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
|
3854 |
|
|
read_RMW_virtual_qword_64(seg, (Bit64u) offset) : \
|
3855 |
|
|
read_RMW_virtual_qword_32(seg, (Bit32u) offset)
|
3856 |
|
|
|
3857 |
|
|
#else
|
3858 |
|
|
|
3859 |
|
|
// write
|
3860 |
|
|
#define write_virtual_byte(seg, offset, data) \
|
3861 |
|
|
write_virtual_byte_32(seg, offset, data)
|
3862 |
|
|
#define write_virtual_word(seg, offset, data) \
|
3863 |
|
|
write_virtual_word_32(seg, offset, data)
|
3864 |
|
|
#define write_virtual_dword(seg, offset, data) \
|
3865 |
|
|
write_virtual_dword_32(seg, offset, data)
|
3866 |
|
|
#define write_virtual_qword(seg, offset, data) \
|
3867 |
|
|
write_virtual_qword_32(seg, offset, data)
|
3868 |
|
|
#define write_virtual_xmmword(seg, offset, data) \
|
3869 |
|
|
write_virtual_xmmword_32(seg, offset, (const BxPackedXmmRegister*)(data))
|
3870 |
|
|
#define write_virtual_xmmword_aligned(seg, offset, data) \
|
3871 |
|
|
write_virtual_xmmword_aligned_32(seg, offset, (const BxPackedXmmRegister*)(data))
|
3872 |
|
|
|
3873 |
|
|
#if BX_SUPPORT_AVX
|
3874 |
|
|
|
3875 |
|
|
#define write_virtual_ymmword(seg, offset, data) \
|
3876 |
|
|
write_virtual_ymmword_32(seg, offset, (const BxPackedAvxRegister*)(data))
|
3877 |
|
|
#define write_virtual_ymmword_aligned(seg, offset, data) \
|
3878 |
|
|
write_virtual_ymmword_aligned_32(seg, offset, (const BxPackedAvxRegister*)(data))
|
3879 |
|
|
|
3880 |
|
|
#endif
|
3881 |
|
|
|
3882 |
|
|
// read
|
3883 |
|
|
#define read_virtual_byte(seg, offset) \
|
3884 |
|
|
read_virtual_byte_32(seg, offset)
|
3885 |
|
|
#define read_virtual_word(seg, offset) \
|
3886 |
|
|
read_virtual_word_32(seg, offset)
|
3887 |
|
|
#define read_virtual_dword(seg, offset) \
|
3888 |
|
|
read_virtual_dword_32(seg, offset)
|
3889 |
|
|
#define read_virtual_qword(seg, offset) \
|
3890 |
|
|
read_virtual_qword_32(seg, offset)
|
3891 |
|
|
#define read_virtual_xmmword(seg, offset, data) \
|
3892 |
|
|
read_virtual_xmmword_32(seg, offset, (BxPackedXmmRegister*)(data))
|
3893 |
|
|
#define read_virtual_xmmword_aligned(seg, offset, data) \
|
3894 |
|
|
read_virtual_xmmword_aligned_32(seg, offset, (BxPackedXmmRegister*)(data))
|
3895 |
|
|
|
3896 |
|
|
#if BX_SUPPORT_AVX
|
3897 |
|
|
|
3898 |
|
|
#define read_virtual_ymmword(seg, offset, data) \
|
3899 |
|
|
read_virtual_ymmword_32(seg, offset, (BxPackedAvxRegister*)(data))
|
3900 |
|
|
#define read_virtual_ymmword_aligned(seg, offset, data) \
|
3901 |
|
|
read_virtual_ymmword_aligned_32(seg, offset, (BxPackedAvxRegister*)(data))
|
3902 |
|
|
|
3903 |
|
|
#endif
|
3904 |
|
|
|
3905 |
|
|
// RMW
|
3906 |
|
|
#define read_RMW_virtual_byte(seg, offset) \
|
3907 |
|
|
read_RMW_virtual_byte_32(seg, offset)
|
3908 |
|
|
#define read_RMW_virtual_word(seg, offset) \
|
3909 |
|
|
read_RMW_virtual_word_32(seg, offset)
|
3910 |
|
|
#define read_RMW_virtual_dword(seg, offset) \
|
3911 |
|
|
read_RMW_virtual_dword_32(seg, offset)
|
3912 |
|
|
#define read_RMW_virtual_qword(seg, offset) \
|
3913 |
|
|
read_RMW_virtual_qword_32(seg, offset)
|
3914 |
|
|
|
3915 |
|
|
#endif
|
3916 |
|
|
|
3917 |
|
|
BX_SMF void stack_write_byte(bx_address offset, Bit8u data) BX_CPP_AttrRegparmN(2);
|
3918 |
|
|
BX_SMF void stack_write_word(bx_address offset, Bit16u data) BX_CPP_AttrRegparmN(2);
|
3919 |
|
|
BX_SMF void stack_write_dword(bx_address offset, Bit32u data) BX_CPP_AttrRegparmN(2);
|
3920 |
|
|
BX_SMF void stack_write_qword(bx_address offset, Bit64u data) BX_CPP_AttrRegparmN(2);
|
3921 |
|
|
|
3922 |
|
|
BX_SMF Bit8u stack_read_byte(bx_address offset) BX_CPP_AttrRegparmN(1);
|
3923 |
|
|
BX_SMF Bit16u stack_read_word(bx_address offset) BX_CPP_AttrRegparmN(1);
|
3924 |
|
|
BX_SMF Bit32u stack_read_dword(bx_address offset) BX_CPP_AttrRegparmN(1);
|
3925 |
|
|
BX_SMF Bit64u stack_read_qword(bx_address offset) BX_CPP_AttrRegparmN(1);
|
3926 |
|
|
|
3927 |
|
|
BX_SMF void stackPrefetch(bx_address offset, unsigned len) BX_CPP_AttrRegparmN(2);
|
3928 |
|
|
|
3929 |
|
|
BX_SMF Bit8u system_read_byte(bx_address laddr) BX_CPP_AttrRegparmN(1);
|
3930 |
|
|
BX_SMF Bit16u system_read_word(bx_address laddr) BX_CPP_AttrRegparmN(1);
|
3931 |
|
|
BX_SMF Bit32u system_read_dword(bx_address laddr) BX_CPP_AttrRegparmN(1);
|
3932 |
|
|
BX_SMF Bit64u system_read_qword(bx_address laddr) BX_CPP_AttrRegparmN(1);
|
3933 |
|
|
|
3934 |
|
|
BX_SMF void system_write_byte(bx_address laddr, Bit8u data) BX_CPP_AttrRegparmN(2);
|
3935 |
|
|
BX_SMF void system_write_word(bx_address laddr, Bit16u data) BX_CPP_AttrRegparmN(2);
|
3936 |
|
|
BX_SMF void system_write_dword(bx_address laddr, Bit32u data) BX_CPP_AttrRegparmN(2);
|
3937 |
|
|
|
3938 |
|
|
BX_SMF Bit8u* v2h_read_byte(bx_address laddr, bx_bool user) BX_CPP_AttrRegparmN(2);
|
3939 |
|
|
BX_SMF Bit8u* v2h_write_byte(bx_address laddr, bx_bool user) BX_CPP_AttrRegparmN(2);
|
3940 |
|
|
|
3941 |
|
|
BX_SMF void branch_near16(Bit16u new_IP) BX_CPP_AttrRegparmN(1);
|
3942 |
|
|
BX_SMF void branch_near32(Bit32u new_EIP) BX_CPP_AttrRegparmN(1);
|
3943 |
|
|
#if BX_SUPPORT_X86_64
|
3944 |
|
|
BX_SMF void branch_near64(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
3945 |
|
|
#endif
|
3946 |
|
|
BX_SMF void branch_far32(bx_selector_t *selector,
|
3947 |
|
|
bx_descriptor_t *descriptor, Bit32u eip, Bit8u cpl);
|
3948 |
|
|
BX_SMF void branch_far64(bx_selector_t *selector,
|
3949 |
|
|
bx_descriptor_t *descriptor, bx_address rip, Bit8u cpl);
|
3950 |
|
|
|
3951 |
|
|
#if BX_SUPPORT_REPEAT_SPEEDUPS
|
3952 |
|
|
BX_SMF Bit32u FastRepMOVSB(bxInstruction_c *i, unsigned srcSeg, bx_address srcOff,
|
3953 |
|
|
unsigned dstSeg, bx_address dstOff, Bit32u byteCount);
|
3954 |
|
|
BX_SMF Bit32u FastRepMOVSW(bxInstruction_c *i, unsigned srcSeg, bx_address srcOff,
|
3955 |
|
|
unsigned dstSeg, bx_address dstOff, Bit32u wordCount);
|
3956 |
|
|
BX_SMF Bit32u FastRepMOVSD(bxInstruction_c *i, unsigned srcSeg, bx_address srcOff,
|
3957 |
|
|
unsigned dstSeg, bx_address dstOff, Bit32u dwordCount);
|
3958 |
|
|
|
3959 |
|
|
BX_SMF Bit32u FastRepSTOSB(bxInstruction_c *i, unsigned dstSeg, bx_address dstOff,
|
3960 |
|
|
Bit8u val, Bit32u byteCount);
|
3961 |
|
|
BX_SMF Bit32u FastRepSTOSW(bxInstruction_c *i, unsigned dstSeg, bx_address dstOff,
|
3962 |
|
|
Bit16u val, Bit32u wordCount);
|
3963 |
|
|
BX_SMF Bit32u FastRepSTOSD(bxInstruction_c *i, unsigned dstSeg, bx_address dstOff,
|
3964 |
|
|
Bit32u val, Bit32u dwordCount);
|
3965 |
|
|
|
3966 |
|
|
BX_SMF Bit32u FastRepINSW(bxInstruction_c *i, bx_address dstOff,
|
3967 |
|
|
Bit16u port, Bit32u wordCount);
|
3968 |
|
|
BX_SMF Bit32u FastRepOUTSW(bxInstruction_c *i, unsigned srcSeg, bx_address srcOff,
|
3969 |
|
|
Bit16u port, Bit32u wordCount);
|
3970 |
|
|
#endif
|
3971 |
|
|
|
3972 |
|
|
BX_SMF void repeat(bxInstruction_c *i, BxRepIterationPtr_tR execute) BX_CPP_AttrRegparmN(2);
|
3973 |
|
|
BX_SMF void repeat_ZF(bxInstruction_c *i, BxRepIterationPtr_tR execute) BX_CPP_AttrRegparmN(2);
|
3974 |
|
|
|
3975 |
|
|
// linear address for access_linear expected to be canonical !
|
3976 |
|
|
BX_SMF void access_read_linear(bx_address laddr, unsigned len, unsigned curr_pl,
|
3977 |
|
|
unsigned rw, void *data);
|
3978 |
|
|
BX_SMF void access_write_linear(bx_address laddr, unsigned len, unsigned curr_pl,
|
3979 |
|
|
void *data);
|
3980 |
|
|
BX_SMF void page_fault(unsigned fault, bx_address laddr, unsigned user, unsigned rw);
|
3981 |
|
|
|
3982 |
|
|
BX_SMF void access_read_physical(bx_phy_address paddr, unsigned len, void *data);
|
3983 |
|
|
BX_SMF void access_write_physical(bx_phy_address paddr, unsigned len, void *data);
|
3984 |
|
|
|
3985 |
|
|
BX_SMF bx_hostpageaddr_t getHostMemAddr(bx_phy_address addr, unsigned rw);
|
3986 |
|
|
|
3987 |
|
|
// linear address for translate_linear expected to be canonical !
|
3988 |
|
|
BX_SMF bx_phy_address translate_linear(bx_TLB_entry *entry, bx_address laddr, unsigned user, unsigned rw);
|
3989 |
|
|
BX_SMF bx_phy_address translate_linear_legacy(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw);
|
3990 |
|
|
BX_SMF void update_access_dirty(bx_phy_address *entry_addr, Bit32u *entry, unsigned leaf, unsigned write);
|
3991 |
|
|
#if BX_CPU_LEVEL >= 6
|
3992 |
|
|
BX_SMF bx_phy_address translate_linear_load_PDPTR(bx_address laddr, unsigned user, unsigned rw);
|
3993 |
|
|
BX_SMF bx_phy_address translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw);
|
3994 |
|
|
BX_SMF int check_entry_PAE(const char *s, Bit64u entry, Bit64u reserved, unsigned rw, bx_bool *nx_fault);
|
3995 |
|
|
BX_SMF void update_access_dirty_PAE(bx_phy_address *entry_addr, Bit64u *entry, unsigned max_level, unsigned leaf, unsigned write);
|
3996 |
|
|
#endif
|
3997 |
|
|
#if BX_SUPPORT_X86_64
|
3998 |
|
|
BX_SMF bx_phy_address translate_linear_long_mode(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw);
|
3999 |
|
|
#endif
|
4000 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4001 |
|
|
BX_SMF bx_phy_address translate_guest_physical(bx_phy_address guest_paddr, bx_address guest_laddr, bx_bool guest_laddr_valid, bx_bool is_page_walk, unsigned rw);
|
4002 |
|
|
BX_SMF void update_ept_access_dirty(bx_phy_address *entry_addr, Bit64u *entry, unsigned leaf, unsigned write);
|
4003 |
|
|
BX_SMF bx_bool is_eptptr_valid(Bit64u eptptr);
|
4004 |
|
|
#endif
|
4005 |
|
|
#if BX_SUPPORT_SVM
|
4006 |
|
|
BX_SMF void nested_page_fault(unsigned fault, bx_phy_address guest_paddr, unsigned rw, unsigned is_page_walk);
|
4007 |
|
|
BX_SMF bx_phy_address nested_walk_long_mode(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk);
|
4008 |
|
|
BX_SMF bx_phy_address nested_walk_PAE(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk);
|
4009 |
|
|
BX_SMF bx_phy_address nested_walk_legacy(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk);
|
4010 |
|
|
BX_SMF bx_phy_address nested_walk(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk);
|
4011 |
|
|
#endif
|
4012 |
|
|
|
4013 |
|
|
#if BX_CPU_LEVEL >= 6
|
4014 |
|
|
BX_SMF void TLB_flushNonGlobal(void);
|
4015 |
|
|
#endif
|
4016 |
|
|
BX_SMF void TLB_flush(void);
|
4017 |
|
|
BX_SMF void TLB_invlpg(bx_address laddr);
|
4018 |
|
|
BX_SMF void inhibit_interrupts(unsigned mask);
|
4019 |
|
|
BX_SMF bx_bool interrupts_inhibited(unsigned mask);
|
4020 |
|
|
BX_SMF const char *strseg(bx_segment_reg_t *seg);
|
4021 |
|
|
BX_SMF void interrupt(Bit8u vector, unsigned type, bx_bool push_error,
|
4022 |
|
|
Bit16u error_code);
|
4023 |
|
|
BX_SMF void real_mode_int(Bit8u vector, bx_bool push_error, Bit16u error_code);
|
4024 |
|
|
BX_SMF void protected_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error,
|
4025 |
|
|
Bit16u error_code);
|
4026 |
|
|
#if BX_SUPPORT_X86_64
|
4027 |
|
|
BX_SMF void long_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error,
|
4028 |
|
|
Bit16u error_code);
|
4029 |
|
|
#endif
|
4030 |
|
|
BX_SMF void exception(unsigned vector, Bit16u error_code)
|
4031 |
|
|
BX_CPP_AttrNoReturn();
|
4032 |
|
|
BX_SMF void init_SMRAM(void);
|
4033 |
|
|
BX_SMF int int_number(unsigned s);
|
4034 |
|
|
|
4035 |
|
|
BX_SMF bx_bool SetCR0(bxInstruction_c *i, bx_address val);
|
4036 |
|
|
BX_SMF bx_bool check_CR0(bx_address val) BX_CPP_AttrRegparmN(1);
|
4037 |
|
|
BX_SMF bx_bool SetCR3(bx_address val) BX_CPP_AttrRegparmN(1);
|
4038 |
|
|
#if BX_CPU_LEVEL >= 5
|
4039 |
|
|
BX_SMF bx_bool SetCR4(bxInstruction_c *i, bx_address val);
|
4040 |
|
|
BX_SMF bx_bool check_CR4(bx_address val) BX_CPP_AttrRegparmN(1);
|
4041 |
|
|
BX_SMF Bit32u get_cr4_allow_mask(void);
|
4042 |
|
|
#endif
|
4043 |
|
|
#if BX_CPU_LEVEL >= 6
|
4044 |
|
|
BX_SMF bx_bool CheckPDPTR(bx_phy_address cr3_val) BX_CPP_AttrRegparmN(1);
|
4045 |
|
|
#endif
|
4046 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4047 |
|
|
BX_SMF bx_bool CheckPDPTR(Bit64u *pdptr) BX_CPP_AttrRegparmN(1);
|
4048 |
|
|
#endif
|
4049 |
|
|
#if BX_CPU_LEVEL >= 5
|
4050 |
|
|
BX_SMF bx_bool SetEFER(bx_address val) BX_CPP_AttrRegparmN(1);
|
4051 |
|
|
#endif
|
4052 |
|
|
|
4053 |
|
|
BX_SMF bx_address read_CR0(void);
|
4054 |
|
|
#if BX_CPU_LEVEL >= 5
|
4055 |
|
|
BX_SMF bx_address read_CR4(void);
|
4056 |
|
|
#endif
|
4057 |
|
|
#if BX_CPU_LEVEL >= 6
|
4058 |
|
|
BX_SMF Bit32u ReadCR8(bxInstruction_c *i);
|
4059 |
|
|
BX_SMF void WriteCR8(bxInstruction_c *i, bx_address val);
|
4060 |
|
|
#endif
|
4061 |
|
|
|
4062 |
|
|
BX_SMF void reset(unsigned source);
|
4063 |
|
|
BX_SMF void shutdown(void);
|
4064 |
|
|
BX_SMF void enter_sleep_state(unsigned state);
|
4065 |
|
|
BX_SMF void handleCpuModeChange(void);
|
4066 |
|
|
BX_SMF void handleCpuContextChange(void);
|
4067 |
|
|
BX_SMF void handleInterruptMaskChange(void);
|
4068 |
|
|
#if BX_CPU_LEVEL >= 4
|
4069 |
|
|
BX_SMF void handleAlignmentCheck(void);
|
4070 |
|
|
#endif
|
4071 |
|
|
#if BX_CPU_LEVEL >= 6
|
4072 |
|
|
BX_SMF void handleSseModeChange(void);
|
4073 |
|
|
BX_SMF void handleAvxModeChange(void);
|
4074 |
|
|
#endif
|
4075 |
|
|
|
4076 |
|
|
#if BX_CPU_LEVEL >= 5
|
4077 |
|
|
BX_SMF bx_bool rdmsr(Bit32u index, Bit64u *val_64) BX_CPP_AttrRegparmN(2);
|
4078 |
|
|
BX_SMF bx_bool handle_unknown_rdmsr(Bit32u index, Bit64u *val_64) BX_CPP_AttrRegparmN(2);
|
4079 |
|
|
BX_SMF bx_bool wrmsr(Bit32u index, Bit64u val_64) BX_CPP_AttrRegparmN(2);
|
4080 |
|
|
BX_SMF bx_bool handle_unknown_wrmsr(Bit32u index, Bit64u val_64) BX_CPP_AttrRegparmN(2);
|
4081 |
|
|
#endif
|
4082 |
|
|
|
4083 |
|
|
#if BX_SUPPORT_APIC
|
4084 |
|
|
BX_SMF bx_bool relocate_apic(Bit64u val_64);
|
4085 |
|
|
#endif
|
4086 |
|
|
|
4087 |
|
|
BX_SMF void task_gate(bxInstruction_c *i, bx_selector_t *selector, bx_descriptor_t *gate_descriptor, unsigned source);
|
4088 |
|
|
BX_SMF void jump_protected(bxInstruction_c *i, Bit16u cs, bx_address disp) BX_CPP_AttrRegparmN(3);
|
4089 |
|
|
BX_SMF void jmp_call_gate(bx_selector_t *selector, bx_descriptor_t *gate_descriptor) BX_CPP_AttrRegparmN(2);
|
4090 |
|
|
BX_SMF void call_gate(bx_descriptor_t *gate_descriptor) BX_CPP_AttrRegparmN(1);
|
4091 |
|
|
#if BX_SUPPORT_X86_64
|
4092 |
|
|
BX_SMF void jmp_call_gate64(bx_selector_t *selector) BX_CPP_AttrRegparmN(1);
|
4093 |
|
|
#endif
|
4094 |
|
|
BX_SMF void call_protected(bxInstruction_c *i, Bit16u cs, bx_address disp) BX_CPP_AttrRegparmN(3);
|
4095 |
|
|
#if BX_SUPPORT_X86_64
|
4096 |
|
|
BX_SMF void call_gate64(bx_selector_t *selector) BX_CPP_AttrRegparmN(1);
|
4097 |
|
|
#endif
|
4098 |
|
|
BX_SMF void return_protected(bxInstruction_c *i, Bit16u pop_bytes) BX_CPP_AttrRegparmN(2);
|
4099 |
|
|
BX_SMF void iret_protected(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
4100 |
|
|
#if BX_SUPPORT_X86_64
|
4101 |
|
|
BX_SMF void long_iret(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
4102 |
|
|
#endif
|
4103 |
|
|
BX_SMF void validate_seg_reg(unsigned seg);
|
4104 |
|
|
BX_SMF void validate_seg_regs(void);
|
4105 |
|
|
BX_SMF void stack_return_to_v86(Bit32u new_eip, Bit32u raw_cs_selector, Bit32u flags32);
|
4106 |
|
|
BX_SMF void iret16_stack_return_from_v86(bxInstruction_c *);
|
4107 |
|
|
BX_SMF void iret32_stack_return_from_v86(bxInstruction_c *);
|
4108 |
|
|
BX_SMF int v86_redirect_interrupt(Bit8u vector);
|
4109 |
|
|
BX_SMF void init_v8086_mode(void);
|
4110 |
|
|
BX_SMF void task_switch_load_selector(bx_segment_reg_t *seg,
|
4111 |
|
|
bx_selector_t *selector, Bit16u raw_selector, Bit8u cs_rpl);
|
4112 |
|
|
BX_SMF void task_switch(bxInstruction_c *i, bx_selector_t *selector, bx_descriptor_t *descriptor,
|
4113 |
|
|
unsigned source, Bit32u dword1, Bit32u dword2, bx_bool push_error = 0, Bit32u error_code = 0);
|
4114 |
|
|
BX_SMF void get_SS_ESP_from_TSS(unsigned pl, Bit16u *ss, Bit32u *esp);
|
4115 |
|
|
#if BX_SUPPORT_X86_64
|
4116 |
|
|
BX_SMF Bit64u get_RSP_from_TSS(unsigned pl);
|
4117 |
|
|
#endif
|
4118 |
|
|
BX_SMF void write_flags(Bit16u flags, bx_bool change_IOPL, bx_bool change_IF) BX_CPP_AttrRegparmN(3);
|
4119 |
|
|
BX_SMF void writeEFlags(Bit32u eflags, Bit32u changeMask) BX_CPP_AttrRegparmN(2); // Newer variant.
|
4120 |
|
|
BX_SMF void write_eflags_fpu_compare(int float_relation);
|
4121 |
|
|
BX_SMF Bit32u force_flags(void);
|
4122 |
|
|
BX_SMF Bit32u read_eflags(void) { return BX_CPU_THIS_PTR force_flags(); }
|
4123 |
|
|
|
4124 |
|
|
BX_SMF bx_bool allow_io(bxInstruction_c *i, Bit16u addr, unsigned len) BX_CPP_AttrRegparmN(3);
|
4125 |
|
|
BX_SMF Bit32u get_descriptor_l(const bx_descriptor_t *) BX_CPP_AttrRegparmN(1);
|
4126 |
|
|
BX_SMF Bit32u get_descriptor_h(const bx_descriptor_t *) BX_CPP_AttrRegparmN(1);
|
4127 |
|
|
BX_SMF bx_bool set_segment_ar_data(bx_segment_reg_t *seg, bx_bool valid, Bit16u raw_selector,
|
4128 |
|
|
bx_address base, Bit32u limit_scaled, Bit16u ar_data);
|
4129 |
|
|
BX_SMF void check_cs(bx_descriptor_t *descriptor, Bit16u cs_raw, Bit8u check_rpl, Bit8u check_cpl);
|
4130 |
|
|
// the basic assumption of the code that load_cs and load_ss cannot fail !
|
4131 |
|
|
BX_SMF void load_cs(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cpl) BX_CPP_AttrRegparmN(3);
|
4132 |
|
|
BX_SMF void load_ss(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cpl) BX_CPP_AttrRegparmN(3);
|
4133 |
|
|
BX_SMF void touch_segment(bx_selector_t *selector, bx_descriptor_t *descriptor) BX_CPP_AttrRegparmN(2);
|
4134 |
|
|
BX_SMF void fetch_raw_descriptor(const bx_selector_t *selector,
|
4135 |
|
|
Bit32u *dword1, Bit32u *dword2, unsigned exception_no);
|
4136 |
|
|
BX_SMF bx_bool fetch_raw_descriptor2(const bx_selector_t *selector,
|
4137 |
|
|
Bit32u *dword1, Bit32u *dword2) BX_CPP_AttrRegparmN(3);
|
4138 |
|
|
BX_SMF void load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value) BX_CPP_AttrRegparmN(2);
|
4139 |
|
|
BX_SMF void load_null_selector(bx_segment_reg_t *seg, unsigned value) BX_CPP_AttrRegparmN(2);
|
4140 |
|
|
#if BX_SUPPORT_X86_64
|
4141 |
|
|
BX_SMF void fetch_raw_descriptor_64(const bx_selector_t *selector,
|
4142 |
|
|
Bit32u *dword1, Bit32u *dword2, Bit32u *dword3, unsigned exception_no);
|
4143 |
|
|
BX_SMF bx_bool fetch_raw_descriptor2_64(const bx_selector_t *selector,
|
4144 |
|
|
Bit32u *dword1, Bit32u *dword2, Bit32u *dword3);
|
4145 |
|
|
#endif
|
4146 |
|
|
BX_SMF void push_16(Bit16u value16) BX_CPP_AttrRegparmN(1);
|
4147 |
|
|
BX_SMF void push_32(Bit32u value32) BX_CPP_AttrRegparmN(1);
|
4148 |
|
|
BX_SMF Bit16u pop_16(void);
|
4149 |
|
|
BX_SMF Bit32u pop_32(void);
|
4150 |
|
|
#if BX_SUPPORT_X86_64
|
4151 |
|
|
BX_SMF void push_64(Bit64u value64) BX_CPP_AttrRegparmN(1);
|
4152 |
|
|
BX_SMF Bit64u pop_64(void);
|
4153 |
|
|
#endif
|
4154 |
|
|
BX_SMF void sanity_checks(void);
|
4155 |
|
|
BX_SMF void assert_checks(void);
|
4156 |
|
|
|
4157 |
|
|
BX_SMF void enter_system_management_mode(void);
|
4158 |
|
|
BX_SMF bx_bool resume_from_system_management_mode(BX_SMM_State *smm_state);
|
4159 |
|
|
BX_SMF void smram_save_state(Bit32u *smm_saved_state);
|
4160 |
|
|
BX_SMF bx_bool smram_restore_state(const Bit32u *smm_saved_state);
|
4161 |
|
|
|
4162 |
|
|
BX_SMF void raise_INTR(void);
|
4163 |
|
|
BX_SMF void clear_INTR(void);
|
4164 |
|
|
|
4165 |
|
|
BX_SMF void deliver_INIT(void);
|
4166 |
|
|
BX_SMF void deliver_NMI(void);
|
4167 |
|
|
BX_SMF void deliver_SMI(void);
|
4168 |
|
|
BX_SMF void deliver_SIPI(unsigned vector);
|
4169 |
|
|
BX_SMF void debug(bx_address offset);
|
4170 |
|
|
#if BX_DISASM
|
4171 |
|
|
BX_SMF void debug_disasm_instruction(bx_address offset);
|
4172 |
|
|
#endif
|
4173 |
|
|
|
4174 |
|
|
#if BX_X86_DEBUGGER
|
4175 |
|
|
// x86 hardware debug support
|
4176 |
|
|
BX_SMF bx_bool hwbreakpoint_check(bx_address laddr, unsigned opa, unsigned opb);
|
4177 |
|
|
#if BX_CPU_LEVEL >= 5
|
4178 |
|
|
BX_SMF void iobreakpoint_match(unsigned port, unsigned len);
|
4179 |
|
|
#endif
|
4180 |
|
|
BX_SMF Bit32u code_breakpoint_match(bx_address laddr);
|
4181 |
|
|
BX_SMF void hwbreakpoint_match(bx_address laddr, unsigned len, unsigned rw);
|
4182 |
|
|
BX_SMF Bit32u hwdebug_compare(bx_address laddr, unsigned len, unsigned opa, unsigned opb);
|
4183 |
|
|
#endif
|
4184 |
|
|
|
4185 |
|
|
BX_SMF void init_FetchDecodeTables(void);
|
4186 |
|
|
|
4187 |
|
|
#if BX_SUPPORT_APIC
|
4188 |
|
|
BX_SMF BX_CPP_INLINE Bit8u get_apic_id(void) { return BX_CPU_THIS_PTR bx_cpuid; }
|
4189 |
|
|
#endif
|
4190 |
|
|
|
4191 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_x86_64(void);
|
4192 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_debug_extensions(void);
|
4193 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_1g_paging(void);
|
4194 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_vme(void);
|
4195 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_tsc(void);
|
4196 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_pae(void);
|
4197 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_pge(void);
|
4198 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse(void);
|
4199 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_pat(void);
|
4200 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_mtrr(void);
|
4201 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_mmx(void);
|
4202 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_sse(void);
|
4203 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_sep(void);
|
4204 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_fxsave_fxrstor(void);
|
4205 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_pcid(void);
|
4206 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_xsave(void);
|
4207 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_fsgsbase(void);
|
4208 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_smep(void);
|
4209 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_x2apic(void);
|
4210 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_smx(void);
|
4211 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_vmx(void);
|
4212 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_svm(void);
|
4213 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_rdtscp(void);
|
4214 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_tsc_deadline(void);
|
4215 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_xapic_extensions(void);
|
4216 |
|
|
BX_SMF BX_CPP_INLINE int bx_cpuid_support_smap(void);
|
4217 |
|
|
|
4218 |
|
|
BX_SMF BX_CPP_INLINE unsigned which_cpu(void) { return BX_CPU_THIS_PTR bx_cpuid; }
|
4219 |
|
|
BX_SMF BX_CPP_INLINE const bx_gen_reg_t *get_gen_regfile() { return BX_CPU_THIS_PTR gen_reg; }
|
4220 |
|
|
|
4221 |
|
|
BX_SMF BX_CPP_INLINE Bit64u get_icount(void) { return BX_CPU_THIS_PTR icount; }
|
4222 |
|
|
BX_SMF BX_CPP_INLINE void sync_icount(void) { BX_CPU_THIS_PTR icount_last_sync = BX_CPU_THIS_PTR icount; }
|
4223 |
|
|
BX_SMF BX_CPP_INLINE Bit64u get_icount_last_sync(void) { return BX_CPU_THIS_PTR icount_last_sync; }
|
4224 |
|
|
|
4225 |
|
|
BX_SMF BX_CPP_INLINE bx_address get_instruction_pointer(void);
|
4226 |
|
|
|
4227 |
|
|
BX_SMF BX_CPP_INLINE Bit32u get_eip(void) { return (BX_CPU_THIS_PTR gen_reg[BX_32BIT_REG_EIP].dword.erx); }
|
4228 |
|
|
BX_SMF BX_CPP_INLINE Bit16u get_ip (void) { return (BX_CPU_THIS_PTR gen_reg[BX_16BIT_REG_IP].word.rx); }
|
4229 |
|
|
#if BX_SUPPORT_X86_64
|
4230 |
|
|
BX_SMF BX_CPP_INLINE Bit64u get_rip(void) { return (BX_CPU_THIS_PTR gen_reg[BX_64BIT_REG_RIP].rrx); }
|
4231 |
|
|
#endif
|
4232 |
|
|
|
4233 |
|
|
BX_SMF BX_CPP_INLINE Bit8u get_reg8l(unsigned reg);
|
4234 |
|
|
BX_SMF BX_CPP_INLINE Bit8u get_reg8h(unsigned reg);
|
4235 |
|
|
BX_SMF BX_CPP_INLINE void set_reg8l(unsigned reg, Bit8u val);
|
4236 |
|
|
BX_SMF BX_CPP_INLINE void set_reg8h(unsigned reg, Bit8u val);
|
4237 |
|
|
|
4238 |
|
|
BX_SMF BX_CPP_INLINE Bit16u get_reg16(unsigned reg);
|
4239 |
|
|
BX_SMF BX_CPP_INLINE void set_reg16(unsigned reg, Bit16u val);
|
4240 |
|
|
BX_SMF BX_CPP_INLINE Bit32u get_reg32(unsigned reg);
|
4241 |
|
|
BX_SMF BX_CPP_INLINE void set_reg32(unsigned reg, Bit32u val);
|
4242 |
|
|
#if BX_SUPPORT_X86_64
|
4243 |
|
|
BX_SMF BX_CPP_INLINE Bit64u get_reg64(unsigned reg);
|
4244 |
|
|
BX_SMF BX_CPP_INLINE void set_reg64(unsigned reg, Bit64u val);
|
4245 |
|
|
#endif
|
4246 |
|
|
|
4247 |
|
|
#if BX_CPU_LEVEL >= 6
|
4248 |
|
|
BX_SMF BX_CPP_INLINE unsigned get_cr8();
|
4249 |
|
|
#endif
|
4250 |
|
|
|
4251 |
|
|
BX_SMF bx_address get_segment_base(unsigned seg);
|
4252 |
|
|
|
4253 |
|
|
// The linear address must be truncated to the 32-bit when CPU is not
|
4254 |
|
|
// executing in long64 mode. The function must be used to compute
|
4255 |
|
|
// linear address everywhere when a code is shared between long64 and
|
4256 |
|
|
// legacy mode. For legacy mode only just use Bit32u to store linear
|
4257 |
|
|
// address value.
|
4258 |
|
|
BX_SMF bx_address get_laddr(unsigned seg, bx_address offset);
|
4259 |
|
|
|
4260 |
|
|
BX_SMF Bit32u get_laddr32(unsigned seg, Bit32u offset);
|
4261 |
|
|
#if BX_SUPPORT_X86_64
|
4262 |
|
|
BX_SMF Bit64u get_laddr64(unsigned seg, Bit64u offset);
|
4263 |
|
|
#endif
|
4264 |
|
|
|
4265 |
|
|
DECLARE_EFLAG_ACCESSOR (ID, 21)
|
4266 |
|
|
DECLARE_EFLAG_ACCESSOR (VIP, 20)
|
4267 |
|
|
DECLARE_EFLAG_ACCESSOR (VIF, 19)
|
4268 |
|
|
DECLARE_EFLAG_ACCESSOR (AC, 18)
|
4269 |
|
|
DECLARE_EFLAG_ACCESSOR (VM, 17)
|
4270 |
|
|
DECLARE_EFLAG_ACCESSOR (RF, 16)
|
4271 |
|
|
DECLARE_EFLAG_ACCESSOR (NT, 14)
|
4272 |
|
|
DECLARE_EFLAG_ACCESSOR_IOPL( 12)
|
4273 |
|
|
DECLARE_EFLAG_ACCESSOR (DF, 10)
|
4274 |
|
|
DECLARE_EFLAG_ACCESSOR (IF, 9)
|
4275 |
|
|
DECLARE_EFLAG_ACCESSOR (TF, 8)
|
4276 |
|
|
|
4277 |
|
|
BX_SMF BX_CPP_INLINE bx_bool real_mode(void);
|
4278 |
|
|
BX_SMF BX_CPP_INLINE bx_bool smm_mode(void);
|
4279 |
|
|
BX_SMF BX_CPP_INLINE bx_bool protected_mode(void);
|
4280 |
|
|
BX_SMF BX_CPP_INLINE bx_bool v8086_mode(void);
|
4281 |
|
|
BX_SMF BX_CPP_INLINE bx_bool long_mode(void);
|
4282 |
|
|
BX_SMF BX_CPP_INLINE bx_bool long64_mode(void);
|
4283 |
|
|
BX_SMF BX_CPP_INLINE unsigned get_cpu_mode(void);
|
4284 |
|
|
|
4285 |
|
|
#if BX_SUPPORT_ALIGNMENT_CHECK && BX_CPU_LEVEL >= 4
|
4286 |
|
|
BX_SMF BX_CPP_INLINE bx_bool alignment_check(void);
|
4287 |
|
|
#endif
|
4288 |
|
|
|
4289 |
|
|
#if BX_CPU_LEVEL >= 5
|
4290 |
|
|
BX_SMF Bit64u get_TSC();
|
4291 |
|
|
BX_SMF void set_TSC(Bit64u tsc);
|
4292 |
|
|
#endif
|
4293 |
|
|
|
4294 |
|
|
#if BX_SUPPORT_FPU
|
4295 |
|
|
BX_SMF void print_state_FPU(void);
|
4296 |
|
|
BX_SMF void prepareFPU(bxInstruction_c *i, bx_bool = 1);
|
4297 |
|
|
BX_SMF void FPU_check_pending_exceptions(void);
|
4298 |
|
|
BX_SMF void FPU_update_last_instruction(bxInstruction_c *i);
|
4299 |
|
|
BX_SMF void FPU_stack_underflow(int stnr, int pop_stack = 0);
|
4300 |
|
|
BX_SMF void FPU_stack_overflow(void);
|
4301 |
|
|
BX_SMF unsigned FPU_exception(unsigned exception, bx_bool = 0);
|
4302 |
|
|
BX_SMF bx_address fpu_save_environment(bxInstruction_c *i);
|
4303 |
|
|
BX_SMF bx_address fpu_load_environment(bxInstruction_c *i);
|
4304 |
|
|
BX_SMF Bit8u pack_FPU_TW(Bit16u tag_word);
|
4305 |
|
|
BX_SMF Bit16u unpack_FPU_TW(Bit16u tag_byte);
|
4306 |
|
|
#endif
|
4307 |
|
|
|
4308 |
|
|
#if BX_CPU_LEVEL >= 5
|
4309 |
|
|
BX_SMF void prepareMMX(void);
|
4310 |
|
|
BX_SMF void prepareFPU2MMX(void); /* cause transition from FPU to MMX technology state */
|
4311 |
|
|
BX_SMF void print_state_MMX(void);
|
4312 |
|
|
#endif
|
4313 |
|
|
|
4314 |
|
|
#if BX_CPU_LEVEL >= 6
|
4315 |
|
|
BX_SMF void check_exceptionsSSE(int);
|
4316 |
|
|
BX_SMF void print_state_SSE(void);
|
4317 |
|
|
|
4318 |
|
|
BX_SMF void prepareXSAVE(void);
|
4319 |
|
|
BX_SMF void print_state_AVX(void);
|
4320 |
|
|
#endif
|
4321 |
|
|
|
4322 |
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
4323 |
|
|
BX_SMF bx_bool is_monitor(bx_phy_address addr, unsigned len);
|
4324 |
|
|
BX_SMF void check_monitor(bx_phy_address addr, unsigned len);
|
4325 |
|
|
#endif
|
4326 |
|
|
|
4327 |
|
|
#if BX_SUPPORT_VMX
|
4328 |
|
|
BX_SMF Bit16u VMread16(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4329 |
|
|
BX_SMF Bit32u VMread32(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4330 |
|
|
BX_SMF Bit64u VMread64(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4331 |
|
|
BX_SMF bx_address VMread_natural(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4332 |
|
|
BX_SMF void VMwrite16(unsigned encoding, Bit16u val_16) BX_CPP_AttrRegparmN(2);
|
4333 |
|
|
BX_SMF void VMwrite32(unsigned encoding, Bit32u val_32) BX_CPP_AttrRegparmN(2);
|
4334 |
|
|
BX_SMF void VMwrite64(unsigned encoding, Bit64u val_64) BX_CPP_AttrRegparmN(2);
|
4335 |
|
|
BX_SMF void VMwrite_natural(unsigned encoding, bx_address val) BX_CPP_AttrRegparmN(2);
|
4336 |
|
|
|
4337 |
|
|
BX_SMF Bit64u vmread(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4338 |
|
|
BX_SMF void vmwrite(unsigned encoding, Bit64u val_64) BX_CPP_AttrRegparmN(2);
|
4339 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4340 |
|
|
BX_SMF Bit64u vmread_shadow(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4341 |
|
|
BX_SMF void vmwrite_shadow(unsigned encoding, Bit64u val_64) BX_CPP_AttrRegparmN(2);
|
4342 |
|
|
#endif
|
4343 |
|
|
|
4344 |
|
|
BX_SMF BX_CPP_INLINE void VMsucceed(void) { setEFlagsOSZAPC(0); }
|
4345 |
|
|
BX_SMF BX_CPP_INLINE void VMfailInvalid(void) { setEFlagsOSZAPC(EFlagsCFMask); }
|
4346 |
|
|
BX_SMF void VMfail(Bit32u error_code);
|
4347 |
|
|
BX_SMF void VMabort(VMX_vmabort_code error_code);
|
4348 |
|
|
|
4349 |
|
|
BX_SMF Bit32u LoadMSRs(Bit32u msr_cnt, bx_phy_address pAddr);
|
4350 |
|
|
BX_SMF Bit32u StoreMSRs(Bit32u msr_cnt, bx_phy_address pAddr);
|
4351 |
|
|
BX_SMF Bit32u VMXReadRevisionID(bx_phy_address pAddr);
|
4352 |
|
|
BX_SMF VMX_error_code VMenterLoadCheckVmControls(void);
|
4353 |
|
|
BX_SMF VMX_error_code VMenterLoadCheckHostState(void);
|
4354 |
|
|
BX_SMF Bit32u VMenterLoadCheckGuestState(Bit64u *qualification);
|
4355 |
|
|
BX_SMF void VMenterInjectEvents(void);
|
4356 |
|
|
BX_SMF void VMexit(Bit32u reason, Bit64u qualification);
|
4357 |
|
|
BX_SMF void VMexitSaveGuestState(void);
|
4358 |
|
|
BX_SMF void VMexitSaveGuestMSRs(void);
|
4359 |
|
|
BX_SMF void VMexitLoadHostState(void);
|
4360 |
|
|
BX_SMF void set_VMCSPTR(Bit64u vmxptr);
|
4361 |
|
|
BX_SMF void init_vmx_capabilities();
|
4362 |
|
|
BX_SMF void init_VMCS(void);
|
4363 |
|
|
BX_SMF bx_bool vmcs_field_supported(Bit32u encoding);
|
4364 |
|
|
BX_SMF void register_vmx_state(bx_param_c *parent);
|
4365 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4366 |
|
|
BX_SMF Bit16u VMX_Get_Current_VPID(void);
|
4367 |
|
|
#endif
|
4368 |
|
|
#if BX_SUPPORT_X86_64
|
4369 |
|
|
BX_SMF bx_bool is_virtual_apic_page(bx_phy_address paddr) BX_CPP_AttrRegparmN(1);
|
4370 |
|
|
BX_SMF bx_bool virtual_apic_access_vmexit(unsigned offset, unsigned len) BX_CPP_AttrRegparmN(2);
|
4371 |
|
|
BX_SMF bx_phy_address VMX_Virtual_Apic_Read(bx_phy_address paddr, unsigned len, void *data);
|
4372 |
|
|
BX_SMF void VMX_Virtual_Apic_Write(bx_phy_address paddr, unsigned len, void *data);
|
4373 |
|
|
BX_SMF Bit32u VMX_Read_Virtual_APIC(unsigned offset);
|
4374 |
|
|
BX_SMF void VMX_Write_Virtual_APIC(unsigned offset, Bit32u val32);
|
4375 |
|
|
BX_SMF void VMX_TPR_Virtualization(void);
|
4376 |
|
|
BX_SMF bx_bool Virtualize_X2APIC_Write(unsigned msr, Bit64u val_64);
|
4377 |
|
|
BX_SMF void VMX_Virtual_Apic_Access_Trap(void);
|
4378 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4379 |
|
|
BX_SMF void vapic_set_vector(unsigned apic_arrbase, Bit8u vector);
|
4380 |
|
|
BX_SMF Bit8u vapic_clear_and_find_highest_priority_int(unsigned apic_arrbase, Bit8u vector);
|
4381 |
|
|
BX_SMF void VMX_Write_VICR(void);
|
4382 |
|
|
BX_SMF void VMX_PPR_Virtualization(void);
|
4383 |
|
|
BX_SMF void VMX_EOI_Virtualization(void);
|
4384 |
|
|
BX_SMF void VMX_Self_IPI_Virtualization(Bit8u vector);
|
4385 |
|
|
BX_SMF void VMX_Evaluate_Pending_Virtual_Interrupts(void);
|
4386 |
|
|
BX_SMF void VMX_Deliver_Virtual_Interrupt(void);
|
4387 |
|
|
#endif
|
4388 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4389 |
|
|
BX_SMF Bit16u VMread16_Shadow(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4390 |
|
|
BX_SMF Bit32u VMread32_Shadow(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4391 |
|
|
BX_SMF Bit64u VMread64_Shadow(unsigned encoding) BX_CPP_AttrRegparmN(1);
|
4392 |
|
|
BX_SMF void VMwrite16_Shadow(unsigned encoding, Bit16u val_16) BX_CPP_AttrRegparmN(2);
|
4393 |
|
|
BX_SMF void VMwrite32_Shadow(unsigned encoding, Bit32u val_32) BX_CPP_AttrRegparmN(2);
|
4394 |
|
|
BX_SMF void VMwrite64_Shadow(unsigned encoding, Bit64u val_64) BX_CPP_AttrRegparmN(2);
|
4395 |
|
|
BX_SMF bx_bool Vmexit_Vmread(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
4396 |
|
|
BX_SMF bx_bool Vmexit_Vmwrite(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
4397 |
|
|
#endif
|
4398 |
|
|
#endif
|
4399 |
|
|
// vmexit reasons
|
4400 |
|
|
BX_SMF void VMexit_Instruction(bxInstruction_c *i, Bit32u reason, bx_bool rw = BX_READ) BX_CPP_AttrRegparmN(3);
|
4401 |
|
|
BX_SMF void VMexit_Event(unsigned type, unsigned vector,
|
4402 |
|
|
Bit16u errcode, bx_bool errcode_valid, Bit64u qualification = 0);
|
4403 |
|
|
BX_SMF void VMexit_TripleFault(void);
|
4404 |
|
|
BX_SMF void VMexit_ExtInterrupt(void);
|
4405 |
|
|
BX_SMF void VMexit_TaskSwitch(Bit16u tss_selector, unsigned source) BX_CPP_AttrRegparmN(2);
|
4406 |
|
|
BX_SMF void VMexit_PAUSE(void);
|
4407 |
|
|
BX_SMF bx_bool VMexit_CLTS(void);
|
4408 |
|
|
BX_SMF void VMexit_MSR(unsigned op, Bit32u msr) BX_CPP_AttrRegparmN(2);
|
4409 |
|
|
BX_SMF void VMexit_IO(bxInstruction_c *i, unsigned port, unsigned len) BX_CPP_AttrRegparmN(3);
|
4410 |
|
|
BX_SMF Bit32u VMexit_LMSW(bxInstruction_c *i, Bit32u msw) BX_CPP_AttrRegparmN(2);
|
4411 |
|
|
BX_SMF bx_address VMexit_CR0_Write(bxInstruction_c *i, bx_address) BX_CPP_AttrRegparmN(2);
|
4412 |
|
|
BX_SMF void VMexit_CR3_Read(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
4413 |
|
|
BX_SMF void VMexit_CR3_Write(bxInstruction_c *i, bx_address) BX_CPP_AttrRegparmN(2);
|
4414 |
|
|
BX_SMF bx_address VMexit_CR4_Write(bxInstruction_c *i, bx_address) BX_CPP_AttrRegparmN(2);
|
4415 |
|
|
BX_SMF void VMexit_CR8_Read(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
4416 |
|
|
BX_SMF void VMexit_CR8_Write(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
|
4417 |
|
|
BX_SMF void VMexit_DR_Access(unsigned read, unsigned dr, unsigned reg);
|
4418 |
|
|
#if BX_SUPPORT_VMX >= 2
|
4419 |
|
|
BX_SMF void Virtualization_Exception(Bit64u qualification, Bit64u guest_physical, Bit64u guest_linear);
|
4420 |
|
|
BX_SMF void vmfunc_eptp_switching(void);
|
4421 |
|
|
#endif
|
4422 |
|
|
#endif
|
4423 |
|
|
|
4424 |
|
|
#if BX_SUPPORT_SVM
|
4425 |
|
|
BX_SMF void SvmEnterSaveHostState(SVM_HOST_STATE *host);
|
4426 |
|
|
BX_SMF bx_bool SvmEnterLoadCheckControls(SVM_CONTROLS *ctrls);
|
4427 |
|
|
BX_SMF bx_bool SvmEnterLoadCheckGuestState(void);
|
4428 |
|
|
BX_SMF bx_bool SvmInjectEvents(void);
|
4429 |
|
|
BX_SMF void Svm_Vmexit(int reason, Bit64u exitinfo1 = 0, Bit64u exitinfo2 = 0);
|
4430 |
|
|
BX_SMF void SvmExitSaveGuestState(void);
|
4431 |
|
|
BX_SMF void SvmExitLoadHostState(SVM_HOST_STATE *host);
|
4432 |
|
|
BX_SMF Bit8u vmcb_read8(unsigned offset);
|
4433 |
|
|
BX_SMF Bit16u vmcb_read16(unsigned offset);
|
4434 |
|
|
BX_SMF Bit32u vmcb_read32(unsigned offset);
|
4435 |
|
|
BX_SMF Bit64u vmcb_read64(unsigned offset);
|
4436 |
|
|
BX_SMF void vmcb_write8(unsigned offset, Bit8u val_8);
|
4437 |
|
|
BX_SMF void vmcb_write16(unsigned offset, Bit16u val_16);
|
4438 |
|
|
BX_SMF void vmcb_write32(unsigned offset, Bit32u val_32);
|
4439 |
|
|
BX_SMF void vmcb_write64(unsigned offset, Bit64u val_64);
|
4440 |
|
|
BX_SMF void svm_segment_read(bx_segment_reg_t *seg, unsigned offset);
|
4441 |
|
|
BX_SMF void svm_segment_write(bx_segment_reg_t *seg, unsigned offset);
|
4442 |
|
|
BX_SMF void SvmInterceptException(unsigned type, unsigned vector,
|
4443 |
|
|
Bit16u errcode, bx_bool errcode_valid, Bit64u qualification = 0);
|
4444 |
|
|
BX_SMF void SvmInterceptIO(bxInstruction_c *i, unsigned port, unsigned len);
|
4445 |
|
|
BX_SMF void SvmInterceptMSR(unsigned op, Bit32u msr);
|
4446 |
|
|
BX_SMF void SvmInterceptTaskSwitch(Bit16u tss_selector, unsigned source, bx_bool push_error, Bit32u error_code);
|
4447 |
|
|
BX_SMF void SvmInterceptPAUSE(void);
|
4448 |
|
|
BX_SMF void VirtualInterruptAcknowledge(void);
|
4449 |
|
|
BX_SMF void register_svm_state(bx_param_c *parent);
|
4450 |
|
|
#endif
|
4451 |
|
|
|
4452 |
|
|
#if BX_CONFIGURE_MSRS
|
4453 |
|
|
int load_MSRs(const char *file);
|
4454 |
|
|
#endif
|
4455 |
|
|
};
|
4456 |
|
|
|
4457 |
|
|
#if BX_CPU_LEVEL >= 5
|
4458 |
|
|
BX_CPP_INLINE void BX_CPU_C::prepareMMX(void)
|
4459 |
|
|
{
|
4460 |
|
|
if(BX_CPU_THIS_PTR cr0.get_EM())
|
4461 |
|
|
exception(BX_UD_EXCEPTION, 0);
|
4462 |
|
|
|
4463 |
|
|
if(BX_CPU_THIS_PTR cr0.get_TS())
|
4464 |
|
|
exception(BX_NM_EXCEPTION, 0);
|
4465 |
|
|
|
4466 |
|
|
/* check floating point status word for a pending FPU exceptions */
|
4467 |
|
|
FPU_check_pending_exceptions();
|
4468 |
|
|
}
|
4469 |
|
|
|
4470 |
|
|
BX_CPP_INLINE void BX_CPU_C::prepareFPU2MMX(void)
|
4471 |
|
|
{
|
4472 |
|
|
BX_CPU_THIS_PTR the_i387.twd = 0;
|
4473 |
|
|
BX_CPU_THIS_PTR the_i387.tos = 0; /* reset FPU Top-Of-Stack */
|
4474 |
|
|
}
|
4475 |
|
|
#endif
|
4476 |
|
|
|
4477 |
|
|
#if BX_CPU_LEVEL >= 6
|
4478 |
|
|
BX_CPP_INLINE void BX_CPU_C::prepareXSAVE(void)
|
4479 |
|
|
{
|
4480 |
|
|
if(! BX_CPU_THIS_PTR cr4.get_OSXSAVE())
|
4481 |
|
|
exception(BX_UD_EXCEPTION, 0);
|
4482 |
|
|
|
4483 |
|
|
if(BX_CPU_THIS_PTR cr0.get_TS())
|
4484 |
|
|
exception(BX_NM_EXCEPTION, 0);
|
4485 |
|
|
}
|
4486 |
|
|
#endif
|
4487 |
|
|
|
4488 |
|
|
// Can be used as LHS or RHS.
|
4489 |
|
|
#define RMAddr(i) (BX_CPU_THIS_PTR address_xlation.rm_addr)
|
4490 |
|
|
|
4491 |
|
|
#if defined(NEED_CPU_REG_SHORTCUTS)
|
4492 |
|
|
|
4493 |
|
|
#include "stack.h"
|
4494 |
|
|
|
4495 |
|
|
#define RSP_SPECULATIVE { \
|
4496 |
|
|
BX_CPU_THIS_PTR speculative_rsp = 1; \
|
4497 |
|
|
BX_CPU_THIS_PTR prev_rsp = RSP; \
|
4498 |
|
|
}
|
4499 |
|
|
|
4500 |
|
|
#define RSP_COMMIT { \
|
4501 |
|
|
BX_CPU_THIS_PTR speculative_rsp = 0; \
|
4502 |
|
|
}
|
4503 |
|
|
|
4504 |
|
|
#endif // defined(NEED_CPU_REG_SHORTCUTS)
|
4505 |
|
|
|
4506 |
|
|
//
|
4507 |
|
|
// bit 0 - CS.D_B
|
4508 |
|
|
// bit 1 - long64 mode (CS.L)
|
4509 |
|
|
// bit 2 - SSE_OK
|
4510 |
|
|
// bit 3 - AVX_OK
|
4511 |
|
|
//
|
4512 |
|
|
// updateFetchModeMask - has to be called everytime
|
4513 |
|
|
// CS.L / CS.D_B / CR0.PE, CR0.TS or CR0.EM / CR4.OSFXSR / CR4.OSXSAVE changes
|
4514 |
|
|
//
|
4515 |
|
|
BX_CPP_INLINE void BX_CPU_C::updateFetchModeMask(void)
|
4516 |
|
|
{
|
4517 |
|
|
BX_CPU_THIS_PTR fetchModeMask =
|
4518 |
|
|
#if BX_CPU_LEVEL >= 6
|
4519 |
|
|
#if BX_SUPPORT_AVX
|
4520 |
|
|
(BX_CPU_THIS_PTR avx_ok << 3) |
|
4521 |
|
|
#endif
|
4522 |
|
|
(BX_CPU_THIS_PTR sse_ok << 2) |
|
4523 |
|
|
#endif
|
4524 |
|
|
#if BX_SUPPORT_X86_64
|
4525 |
|
|
((BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)<<1) |
|
4526 |
|
|
#endif
|
4527 |
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b);
|
4528 |
|
|
|
4529 |
|
|
BX_CPU_THIS_PTR user_pl = // CPL == 3
|
4530 |
|
|
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl == 3);
|
4531 |
|
|
}
|
4532 |
|
|
|
4533 |
|
|
#if BX_X86_DEBUGGER
|
4534 |
|
|
#define BX_HWDebugInstruction 0x00
|
4535 |
|
|
#define BX_HWDebugMemW 0x01
|
4536 |
|
|
#define BX_HWDebugIO 0x02
|
4537 |
|
|
#define BX_HWDebugMemRW 0x03
|
4538 |
|
|
#endif
|
4539 |
|
|
|
4540 |
|
|
BX_CPP_INLINE bx_address BX_CPU_C::get_segment_base(unsigned seg)
|
4541 |
|
|
{
|
4542 |
|
|
#if BX_SUPPORT_X86_64
|
4543 |
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
4544 |
|
|
if (seg < BX_SEG_REG_FS) return 0;
|
4545 |
|
|
}
|
4546 |
|
|
#endif
|
4547 |
|
|
return BX_CPU_THIS_PTR sregs[seg].cache.u.segment.base;
|
4548 |
|
|
}
|
4549 |
|
|
|
4550 |
|
|
BX_CPP_INLINE Bit32u BX_CPU_C::get_laddr32(unsigned seg, Bit32u offset)
|
4551 |
|
|
{
|
4552 |
|
|
return (Bit32u) BX_CPU_THIS_PTR sregs[seg].cache.u.segment.base + offset;
|
4553 |
|
|
}
|
4554 |
|
|
|
4555 |
|
|
#if BX_SUPPORT_X86_64
|
4556 |
|
|
BX_CPP_INLINE Bit64u BX_CPU_C::get_laddr64(unsigned seg, Bit64u offset)
|
4557 |
|
|
{
|
4558 |
|
|
if (seg < BX_SEG_REG_FS)
|
4559 |
|
|
return offset;
|
4560 |
|
|
else
|
4561 |
|
|
return BX_CPU_THIS_PTR sregs[seg].cache.u.segment.base + offset;
|
4562 |
|
|
}
|
4563 |
|
|
#endif
|
4564 |
|
|
|
4565 |
|
|
BX_CPP_INLINE bx_address BX_CPU_C::get_laddr(unsigned seg, bx_address offset)
|
4566 |
|
|
{
|
4567 |
|
|
#if BX_SUPPORT_X86_64
|
4568 |
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
4569 |
|
|
return get_laddr64(seg, offset);
|
4570 |
|
|
}
|
4571 |
|
|
#endif
|
4572 |
|
|
return get_laddr32(seg, (Bit32u) offset);
|
4573 |
|
|
}
|
4574 |
|
|
|
4575 |
|
|
BX_CPP_INLINE Bit8u BX_CPU_C::get_reg8l(unsigned reg)
|
4576 |
|
|
{
|
4577 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4578 |
|
|
return (BX_CPU_THIS_PTR gen_reg[reg].word.byte.rl);
|
4579 |
|
|
}
|
4580 |
|
|
|
4581 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_reg8l(unsigned reg, Bit8u val)
|
4582 |
|
|
{
|
4583 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4584 |
|
|
BX_CPU_THIS_PTR gen_reg[reg].word.byte.rl = val;
|
4585 |
|
|
}
|
4586 |
|
|
|
4587 |
|
|
BX_CPP_INLINE Bit8u BX_CPU_C::get_reg8h(unsigned reg)
|
4588 |
|
|
{
|
4589 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4590 |
|
|
return (BX_CPU_THIS_PTR gen_reg[reg].word.byte.rh);
|
4591 |
|
|
}
|
4592 |
|
|
|
4593 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_reg8h(unsigned reg, Bit8u val)
|
4594 |
|
|
{
|
4595 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4596 |
|
|
BX_CPU_THIS_PTR gen_reg[reg].word.byte.rh = val;
|
4597 |
|
|
}
|
4598 |
|
|
|
4599 |
|
|
#if BX_SUPPORT_X86_64
|
4600 |
|
|
BX_CPP_INLINE bx_address BX_CPU_C::get_instruction_pointer(void)
|
4601 |
|
|
{
|
4602 |
|
|
return BX_CPU_THIS_PTR get_rip();
|
4603 |
|
|
}
|
4604 |
|
|
#else
|
4605 |
|
|
BX_CPP_INLINE bx_address BX_CPU_C::get_instruction_pointer(void)
|
4606 |
|
|
{
|
4607 |
|
|
return BX_CPU_THIS_PTR get_eip();
|
4608 |
|
|
}
|
4609 |
|
|
#endif
|
4610 |
|
|
|
4611 |
|
|
BX_CPP_INLINE Bit16u BX_CPU_C::get_reg16(unsigned reg)
|
4612 |
|
|
{
|
4613 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4614 |
|
|
return (BX_CPU_THIS_PTR gen_reg[reg].word.rx);
|
4615 |
|
|
}
|
4616 |
|
|
|
4617 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_reg16(unsigned reg, Bit16u val)
|
4618 |
|
|
{
|
4619 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4620 |
|
|
BX_CPU_THIS_PTR gen_reg[reg].word.rx = val;
|
4621 |
|
|
}
|
4622 |
|
|
|
4623 |
|
|
BX_CPP_INLINE Bit32u BX_CPU_C::get_reg32(unsigned reg)
|
4624 |
|
|
{
|
4625 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4626 |
|
|
return (BX_CPU_THIS_PTR gen_reg[reg].dword.erx);
|
4627 |
|
|
}
|
4628 |
|
|
|
4629 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_reg32(unsigned reg, Bit32u val)
|
4630 |
|
|
{
|
4631 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4632 |
|
|
BX_CPU_THIS_PTR gen_reg[reg].dword.erx = val;
|
4633 |
|
|
}
|
4634 |
|
|
|
4635 |
|
|
#if BX_SUPPORT_X86_64
|
4636 |
|
|
BX_CPP_INLINE Bit64u BX_CPU_C::get_reg64(unsigned reg)
|
4637 |
|
|
{
|
4638 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4639 |
|
|
return (BX_CPU_THIS_PTR gen_reg[reg].rrx);
|
4640 |
|
|
}
|
4641 |
|
|
|
4642 |
|
|
BX_CPP_INLINE void BX_CPU_C::set_reg64(unsigned reg, Bit64u val)
|
4643 |
|
|
{
|
4644 |
|
|
assert(reg < BX_GENERAL_REGISTERS);
|
4645 |
|
|
BX_CPU_THIS_PTR gen_reg[reg].rrx = val;
|
4646 |
|
|
}
|
4647 |
|
|
#endif
|
4648 |
|
|
|
4649 |
|
|
#if BX_CPU_LEVEL >= 6
|
4650 |
|
|
// CR8 is aliased to APIC->TASK PRIORITY register
|
4651 |
|
|
// APIC.TPR[7:4] = CR8[3:0]
|
4652 |
|
|
// APIC.TPR[3:0] = 0
|
4653 |
|
|
// Reads of CR8 return zero extended APIC.TPR[7:4]
|
4654 |
|
|
BX_CPP_INLINE unsigned BX_CPU_C::get_cr8(void)
|
4655 |
|
|
{
|
4656 |
|
|
return (BX_CPU_THIS_PTR lapic.get_tpr() >> 4) & 0xf;
|
4657 |
|
|
}
|
4658 |
|
|
#endif
|
4659 |
|
|
|
4660 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::real_mode(void)
|
4661 |
|
|
{
|
4662 |
|
|
return (BX_CPU_THIS_PTR cpu_mode == BX_MODE_IA32_REAL);
|
4663 |
|
|
}
|
4664 |
|
|
|
4665 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::smm_mode(void)
|
4666 |
|
|
{
|
4667 |
|
|
return (BX_CPU_THIS_PTR in_smm);
|
4668 |
|
|
}
|
4669 |
|
|
|
4670 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::v8086_mode(void)
|
4671 |
|
|
{
|
4672 |
|
|
return (BX_CPU_THIS_PTR cpu_mode == BX_MODE_IA32_V8086);
|
4673 |
|
|
}
|
4674 |
|
|
|
4675 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::protected_mode(void)
|
4676 |
|
|
{
|
4677 |
|
|
return (BX_CPU_THIS_PTR cpu_mode >= BX_MODE_IA32_PROTECTED);
|
4678 |
|
|
}
|
4679 |
|
|
|
4680 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::long_mode(void)
|
4681 |
|
|
{
|
4682 |
|
|
#if BX_SUPPORT_X86_64
|
4683 |
|
|
return BX_CPU_THIS_PTR efer.get_LMA();
|
4684 |
|
|
#else
|
4685 |
|
|
return 0;
|
4686 |
|
|
#endif
|
4687 |
|
|
}
|
4688 |
|
|
|
4689 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::long64_mode(void)
|
4690 |
|
|
{
|
4691 |
|
|
#if BX_SUPPORT_X86_64
|
4692 |
|
|
return (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
|
4693 |
|
|
#else
|
4694 |
|
|
return 0;
|
4695 |
|
|
#endif
|
4696 |
|
|
}
|
4697 |
|
|
|
4698 |
|
|
BX_CPP_INLINE unsigned BX_CPU_C::get_cpu_mode(void)
|
4699 |
|
|
{
|
4700 |
|
|
return (BX_CPU_THIS_PTR cpu_mode);
|
4701 |
|
|
}
|
4702 |
|
|
|
4703 |
|
|
#if BX_SUPPORT_ALIGNMENT_CHECK && BX_CPU_LEVEL >= 4
|
4704 |
|
|
BX_CPP_INLINE bx_bool BX_CPU_C::alignment_check(void)
|
4705 |
|
|
{
|
4706 |
|
|
return BX_CPU_THIS_PTR alignment_check_mask;
|
4707 |
|
|
}
|
4708 |
|
|
#endif
|
4709 |
|
|
|
4710 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_svm(void)
|
4711 |
|
|
{
|
4712 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_SVM) != 0;
|
4713 |
|
|
}
|
4714 |
|
|
|
4715 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_smx(void)
|
4716 |
|
|
{
|
4717 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_SMX) != 0;
|
4718 |
|
|
}
|
4719 |
|
|
|
4720 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_vmx(void)
|
4721 |
|
|
{
|
4722 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_VMX) != 0;
|
4723 |
|
|
}
|
4724 |
|
|
|
4725 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_xsave(void)
|
4726 |
|
|
{
|
4727 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_XSAVE) != 0;
|
4728 |
|
|
}
|
4729 |
|
|
|
4730 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_x2apic(void)
|
4731 |
|
|
{
|
4732 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_X2APIC) != 0;
|
4733 |
|
|
}
|
4734 |
|
|
|
4735 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pcid(void)
|
4736 |
|
|
{
|
4737 |
|
|
#if BX_SUPPORT_X86_64
|
4738 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PCID) != 0;
|
4739 |
|
|
#else
|
4740 |
|
|
return 0;
|
4741 |
|
|
#endif
|
4742 |
|
|
}
|
4743 |
|
|
|
4744 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_fsgsbase(void)
|
4745 |
|
|
{
|
4746 |
|
|
#if BX_SUPPORT_X86_64
|
4747 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_FSGSBASE) != 0;
|
4748 |
|
|
#else
|
4749 |
|
|
return 0;
|
4750 |
|
|
#endif
|
4751 |
|
|
}
|
4752 |
|
|
|
4753 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_smap(void)
|
4754 |
|
|
{
|
4755 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_SMAP) != 0;
|
4756 |
|
|
}
|
4757 |
|
|
|
4758 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_smep(void)
|
4759 |
|
|
{
|
4760 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_SMEP) != 0;
|
4761 |
|
|
}
|
4762 |
|
|
|
4763 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_vme(void)
|
4764 |
|
|
{
|
4765 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_VME) != 0;
|
4766 |
|
|
}
|
4767 |
|
|
|
4768 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_tsc(void)
|
4769 |
|
|
{
|
4770 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_PENTIUM) != 0;
|
4771 |
|
|
}
|
4772 |
|
|
|
4773 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_debug_extensions(void)
|
4774 |
|
|
{
|
4775 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_DEBUG_EXTENSIONS) != 0;
|
4776 |
|
|
}
|
4777 |
|
|
|
4778 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pse(void)
|
4779 |
|
|
{
|
4780 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PSE) != 0;
|
4781 |
|
|
}
|
4782 |
|
|
|
4783 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pat(void)
|
4784 |
|
|
{
|
4785 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PAT) != 0;
|
4786 |
|
|
}
|
4787 |
|
|
|
4788 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_mtrr(void)
|
4789 |
|
|
{
|
4790 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_MTRR) != 0;
|
4791 |
|
|
}
|
4792 |
|
|
|
4793 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pae(void)
|
4794 |
|
|
{
|
4795 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PAE) != 0;
|
4796 |
|
|
}
|
4797 |
|
|
|
4798 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pge(void)
|
4799 |
|
|
{
|
4800 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PGE) != 0;
|
4801 |
|
|
}
|
4802 |
|
|
|
4803 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_mmx(void)
|
4804 |
|
|
{
|
4805 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_MMX) != 0;
|
4806 |
|
|
}
|
4807 |
|
|
|
4808 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_sse(void)
|
4809 |
|
|
{
|
4810 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_SSE) != 0;
|
4811 |
|
|
}
|
4812 |
|
|
|
4813 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_sep(void)
|
4814 |
|
|
{
|
4815 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_SYSENTER_SYSEXIT) != 0;
|
4816 |
|
|
}
|
4817 |
|
|
|
4818 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_fxsave_fxrstor(void)
|
4819 |
|
|
{
|
4820 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_SSE) != 0;
|
4821 |
|
|
}
|
4822 |
|
|
|
4823 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_x86_64(void)
|
4824 |
|
|
{
|
4825 |
|
|
#if BX_SUPPORT_X86_64
|
4826 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_LONG_MODE) != 0;
|
4827 |
|
|
#else
|
4828 |
|
|
return 0;
|
4829 |
|
|
#endif
|
4830 |
|
|
}
|
4831 |
|
|
|
4832 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_1g_paging(void)
|
4833 |
|
|
{
|
4834 |
|
|
#if BX_SUPPORT_X86_64
|
4835 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_1G_PAGES) != 0;
|
4836 |
|
|
#else
|
4837 |
|
|
return 0;
|
4838 |
|
|
#endif
|
4839 |
|
|
}
|
4840 |
|
|
|
4841 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_rdtscp(void)
|
4842 |
|
|
{
|
4843 |
|
|
#if BX_SUPPORT_X86_64
|
4844 |
|
|
return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_ISA_RDTSCP) != 0;
|
4845 |
|
|
#else
|
4846 |
|
|
return 0;
|
4847 |
|
|
#endif
|
4848 |
|
|
}
|
4849 |
|
|
|
4850 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_tsc_deadline(void)
|
4851 |
|
|
{
|
4852 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_TSC_DEADLINE) != 0;
|
4853 |
|
|
}
|
4854 |
|
|
|
4855 |
|
|
BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_xapic_extensions(void)
|
4856 |
|
|
{
|
4857 |
|
|
return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_XAPIC_EXT) != 0;
|
4858 |
|
|
}
|
4859 |
|
|
|
4860 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (ID, 21)
|
4861 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (VIP, 20)
|
4862 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (VIF, 19)
|
4863 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (AC, 18)
|
4864 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (VM, 17)
|
4865 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (RF, 16)
|
4866 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (NT, 14)
|
4867 |
|
|
IMPLEMENT_EFLAG_ACCESSOR_IOPL( 12)
|
4868 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (DF, 10)
|
4869 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (IF, 9)
|
4870 |
|
|
IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
|
4871 |
|
|
|
4872 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR (ID, 21)
|
4873 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR (VIP, 20)
|
4874 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR (VIF, 19)
|
4875 |
|
|
#if BX_SUPPORT_ALIGNMENT_CHECK && BX_CPU_LEVEL >= 4
|
4876 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR_AC( 18)
|
4877 |
|
|
#else
|
4878 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR (AC, 18)
|
4879 |
|
|
#endif
|
4880 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR_VM( 17)
|
4881 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR_RF( 16)
|
4882 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR (NT, 14)
|
4883 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR (DF, 10)
|
4884 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR_IF( 9)
|
4885 |
|
|
IMPLEMENT_EFLAG_SET_ACCESSOR_TF( 8)
|
4886 |
|
|
|
4887 |
|
|
#define BX_TASK_FROM_CALL 0
|
4888 |
|
|
#define BX_TASK_FROM_IRET 1
|
4889 |
|
|
#define BX_TASK_FROM_JUMP 2
|
4890 |
|
|
#define BX_TASK_FROM_INT 3
|
4891 |
|
|
|
4892 |
|
|
// exception types for interrupt method
|
4893 |
|
|
enum {
|
4894 |
|
|
BX_EXTERNAL_INTERRUPT = 0,
|
4895 |
|
|
BX_NMI = 2,
|
4896 |
|
|
BX_HARDWARE_EXCEPTION = 3, // all exceptions except #BP and #OF
|
4897 |
|
|
BX_SOFTWARE_INTERRUPT = 4,
|
4898 |
|
|
BX_PRIVILEGED_SOFTWARE_INTERRUPT = 5,
|
4899 |
|
|
BX_SOFTWARE_EXCEPTION = 6
|
4900 |
|
|
};
|
4901 |
|
|
|
4902 |
|
|
#if BX_CPU_LEVEL >= 6
|
4903 |
|
|
enum {
|
4904 |
|
|
BX_INVPCID_INDIVIDUAL_ADDRESS_NON_GLOBAL_INVALIDATION,
|
4905 |
|
|
BX_INVPCID_SINGLE_CONTEXT_NON_GLOBAL_INVALIDATION,
|
4906 |
|
|
BX_INVPCID_ALL_CONTEXT_INVALIDATION,
|
4907 |
|
|
BX_INVPCID_ALL_CONTEXT_NON_GLOBAL_INVALIDATION
|
4908 |
|
|
};
|
4909 |
|
|
#endif
|
4910 |
|
|
|
4911 |
|
|
// <TAG-DEFINES-DECODE-START>
|
4912 |
|
|
|
4913 |
|
|
//
|
4914 |
|
|
// For decoding...
|
4915 |
|
|
//
|
4916 |
|
|
|
4917 |
|
|
// If the BxImmediate mask is set, the lowest 4 bits of the attribute
|
4918 |
|
|
// specify which kinds of immediate data required by instruction.
|
4919 |
|
|
|
4920 |
|
|
#define BxImmediate 0x000f // bits 3..0: any immediate
|
4921 |
|
|
#define BxImmediate_I1 0x0001 // imm8 = 1
|
4922 |
|
|
#define BxImmediate_Ib 0x0002 // 8 bit
|
4923 |
|
|
#define BxImmediate_Ib_SE 0x0003 // sign extend to OS size
|
4924 |
|
|
#define BxImmediate_Iw 0x0004 // 16 bit
|
4925 |
|
|
#define BxImmediate_Id 0x0005 // 32 bit
|
4926 |
|
|
#define BxImmediate_O 0x0006 // MOV_ALOd, mov_OdAL, mov_eAXOv, mov_OveAX
|
4927 |
|
|
#if BX_SUPPORT_X86_64
|
4928 |
|
|
#define BxImmediate_Iq 0x0007 // 64 bit override
|
4929 |
|
|
#endif
|
4930 |
|
|
#define BxImmediate_BrOff8 0x0008 // Relative branch offset byte
|
4931 |
|
|
|
4932 |
|
|
#define BxImmediate_Ib4 BxImmediate_Ib // Register encoded in Ib[7:4]
|
4933 |
|
|
#define BxImmediate_Ib5 BxImmediate_Ib
|
4934 |
|
|
|
4935 |
|
|
#define BxImmediate_BrOff16 BxImmediate_Iw // Relative branch offset word, not encodable in 64-bit mode
|
4936 |
|
|
#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
|
4937 |
|
|
|
4938 |
|
|
// Lookup for opcode and attributes in another opcode tables
|
4939 |
|
|
// Totally 15 opcode groups supported
|
4940 |
|
|
#define BxGroupX 0x00f0 // bits 7..4: opcode groups definition
|
4941 |
|
|
#define BxPrefixSSE66 0x0010 // Group encoding: 0001, SSE_PREFIX_66 only
|
4942 |
|
|
#define BxPrefixSSEF3 0x0020 // Group encoding: 0010, SSE_PREFIX_F3 only
|
4943 |
|
|
#define BxPrefixSSEF2 0x0030 // Group encoding: 0011, SSE_PREFIX_F2 only
|
4944 |
|
|
#define BxPrefixSSE 0x0040 // Group encoding: 0100
|
4945 |
|
|
#define BxPrefixSSEF2F3 0x0050 // Group encoding: 0101, ignore SSE_PREFIX_66
|
4946 |
|
|
#define BxGroupN 0x0060 // Group encoding: 0110
|
4947 |
|
|
#define BxSplitGroupN 0x0070 // Group encoding: 0111
|
4948 |
|
|
#define BxFPEscape 0x0080 // Group encoding: 1000
|
4949 |
|
|
#define Bx3ByteOp 0x0090 // Group encoding: 1001
|
4950 |
|
|
#define BxOSizeGrp 0x00A0 // Group encoding: 1010
|
4951 |
|
|
#define BxPrefixVEX 0x00B0 // Group encoding: 1011
|
4952 |
|
|
#define BxSplitVexW 0x00C0 // Group encoding: 1100
|
4953 |
|
|
#define BxSplitVexW64 0x00D0 // Group encoding: 1101 - VexW ignored in 32-bit mode
|
4954 |
|
|
#define BxSplitMod11B 0x00E0 // Group encoding: 1110
|
4955 |
|
|
|
4956 |
|
|
// The BxImmediate2 mask specifies kind of second immediate data
|
4957 |
|
|
// required by instruction.
|
4958 |
|
|
#define BxImmediate2 0x0300 // bits 8.9: any immediate
|
4959 |
|
|
#define BxImmediate_Ib2 0x0100
|
4960 |
|
|
#define BxImmediate_Iw2 0x0200
|
4961 |
|
|
#define BxImmediate_Id2 0x0300
|
4962 |
|
|
|
4963 |
|
|
#define BxLockable 0x0400 // bit 10
|
4964 |
|
|
#define BxRepeatable 0x0800 // bit 11
|
4965 |
|
|
#define BxVexW0 0x1000 // bit 12
|
4966 |
|
|
#define BxVexW1 0x2000 // bit 13
|
4967 |
|
|
|
4968 |
|
|
#define BxTraceEnd 0x8000 // bit 15
|
4969 |
|
|
|
4970 |
|
|
|
4971 |
|
|
#ifdef BX_TRACE_CACHE_NO_SPECULATIVE_TRACING
|
4972 |
|
|
#define BxTraceJCC BxTraceEnd
|
4973 |
|
|
#else
|
4974 |
|
|
#define BxTraceJCC 0
|
4975 |
|
|
#endif
|
4976 |
|
|
|
4977 |
|
|
#define BxGroup1 BxGroupN
|
4978 |
|
|
#define BxGroup1A BxGroupN
|
4979 |
|
|
#define BxGroup2 BxGroupN
|
4980 |
|
|
#define BxGroup3 BxGroupN
|
4981 |
|
|
#define BxGroup4 BxGroupN
|
4982 |
|
|
#define BxGroup5 BxGroupN
|
4983 |
|
|
#define BxGroup6 BxGroupN
|
4984 |
|
|
#define BxGroup7 BxFPEscape
|
4985 |
|
|
#define BxGroup8 BxGroupN
|
4986 |
|
|
#define BxGroup9 BxSplitGroupN
|
4987 |
|
|
|
4988 |
|
|
#define BxGroup11 BxGroupN
|
4989 |
|
|
#define BxGroup12 BxGroupN
|
4990 |
|
|
#define BxGroup13 BxGroupN
|
4991 |
|
|
#define BxGroup14 BxGroupN
|
4992 |
|
|
#define BxGroup15 BxSplitGroupN
|
4993 |
|
|
#define BxGroup16 BxGroupN
|
4994 |
|
|
#define BxGroup17 BxGroupN
|
4995 |
|
|
#define BxGroup17A BxGroupN
|
4996 |
|
|
|
4997 |
|
|
#define BxGroupFP BxSplitGroupN
|
4998 |
|
|
|
4999 |
|
|
// <TAG-DEFINES-DECODE-END>
|
5000 |
|
|
|
5001 |
|
|
#endif // #ifndef BX_CPU_H
|