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alfik |
To add an Ethernet real-time dump of io accesses make the following changes to the source code:
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soc.v ports:
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[
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//debug - ethernet
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output ENET0_GTX_CLK,
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output ENET0_RST_N,
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input ENET0_RX_CLK,
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input [3:0] ENET0_RX_DATA,
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input ENET0_RX_DV,
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output [3:0] ENET0_TX_DATA,
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output ENET0_TX_EN
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]
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soc.v u0 instantiation :
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[
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.ao486_conduit_dbg_tb_finish_instr (dbg_tb_finish_instr),
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.ao486_conduit_dbg_dbg_io_address (dbg_io_address),
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.ao486_conduit_dbg_dbg_io_byteenable (dbg_io_byteenable),
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.ao486_conduit_dbg_dbg_io_write (dbg_io_write),
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.ao486_conduit_dbg_dbg_io_read (dbg_io_read),
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.ao486_conduit_dbg_dbg_io_data (dbg_io_data),
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.ao486_conduit_dbg_dbg_int_vector (dbg_int_vector),
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.ao486_conduit_dbg_dbg_int (dbg_int),
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.ao486_conduit_dbg_dbg_exc_vector (dbg_exc_vector),
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.ao486_conduit_dbg_dbg_exc (dbg_exc),
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.ao486_conduit_dbg_dbg_mem_address (dbg_mem_address),
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.ao486_conduit_dbg_dbg_mem_byteenable(dbg_mem_byteenable),
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.ao486_conduit_dbg_dbg_mem_write (dbg_mem_write),
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.ao486_conduit_dbg_dbg_mem_read (dbg_mem_read),
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.ao486_conduit_dbg_dbg_mem_data (dbg_mem_data)
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]
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ao486.v ports:
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[
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//-------------------------------------------------------------------------- debug
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input [17:0] SW,
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output tb_finish_instr,
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output [15:0] dbg_io_address,
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output [3:0] dbg_io_byteenable,
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output dbg_io_write,
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output dbg_io_read,
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output [31:0] dbg_io_data,
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output [7:0] dbg_int_vector,
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output dbg_int,
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output [7:0] dbg_exc_vector,
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output dbg_exc,
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output [31:0] dbg_mem_address,
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output [3:0] dbg_mem_byteenable,
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output dbg_mem_write,
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output dbg_mem_read,
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output [31:0] dbg_mem_data
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]
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pipeline.v ports:
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[
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//debug
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input [17:0] SW,
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output tb_finish_instr
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]
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pipeline.v:
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[
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//---------------- debug
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wire dbg_hold = dec_cmd != 7'd0 && dec_cmd > SW[6:0];
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reg dbg_holding;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_holding <= 1'b0;
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else if(dbg_eip_cnt == 32'hFFFFFFFF && SW[17]) dbg_holding <= 1'b1; //dummy
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else if(dbg_hold) dbg_holding <= 1'b1;
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else if(dbg_holding && rd_cmd == 7'd0 && ~(exe_mutex[10]) && ~(wr_mutex[10])) dbg_holding <= 1'b0;
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end
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reg [31:0] dbg_eip_cnt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_eip_cnt <= 32'd0;
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else if(dbg_eip_cnt == 32'd0 && eip[31]) dbg_eip_cnt <= 32'd1;
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else if(dbg_eip_cnt != 32'd0) dbg_eip_cnt <= dbg_eip_cnt + 32'd1;
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end
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//---------------- debug
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]
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pipeline.v decode instantiation:
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[
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//TODO: delete: micro_busy || rd_cmd != 7'd0 || exe_mutex[10] || wr_mutex[10]
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.micro_busy (micro_busy || ((dbg_hold || dbg_holding) && (rd_cmd != 7'd0 || exe_mutex[10] || wr_mutex[10]))), //input
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]
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ao486.v:
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[
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//--------------------------------------------------------------------------
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assign dbg_io_address = (avalon_io_readdatavalid)? dbg_io_address_reg : avalon_io_address;
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assign dbg_io_byteenable = (avalon_io_readdatavalid)? dbg_io_byteenable_reg : avalon_io_byteenable;
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assign dbg_io_write = avalon_io_write && avalon_io_waitrequest == 1'b0;
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assign dbg_io_read = avalon_io_readdatavalid;
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assign dbg_io_data = (avalon_io_readdatavalid)? avalon_io_readdata : avalon_io_writedata;
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reg [15:0] dbg_io_address_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_io_address_reg <= 16'd0;
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else if(avalon_io_read) dbg_io_address_reg <= avalon_io_address;
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end
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reg [3:0] dbg_io_byteenable_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_io_byteenable_reg <= 4'd0;
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else if(avalon_io_read) dbg_io_byteenable_reg <= avalon_io_byteenable;
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end
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assign dbg_int_vector = interrupt_vector;
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assign dbg_int = interrupt_done;
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assign dbg_exc_vector = exc_vector;
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assign dbg_exc = exc_init && (wr_interrupt_possible == 1'b0 || interrupt_do == 1'b0) && interrupt_done == 1'b0;
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//-----
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reg [31:0] dbg_mem_address_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_mem_address_reg <= 32'd0;
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else if(avm_read && dbg_mem_vga && avm_waitrequest == 1'b0) dbg_mem_address_reg <= avm_address;
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else if(dbg_mem_is_read_reg && avm_readdatavalid) dbg_mem_address_reg <= dbg_mem_address_reg + 32'd4;
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else if(avm_write && dbg_mem_is_write_reg == 1'b0 && avm_waitrequest == 1'b0) dbg_mem_address_reg <= avm_address + 32'd4;
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else if(avm_write && dbg_mem_is_write_reg && avm_waitrequest == 1'b0) dbg_mem_address_reg <= dbg_mem_address_reg + 32'd4;
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end
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reg [3:0] dbg_mem_byteenable_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_mem_byteenable_reg <= 4'd0;
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else if(avm_read && dbg_mem_vga && avm_waitrequest == 1'b0) dbg_mem_byteenable_reg <= avm_byteenable;
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end
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reg [2:0] dbg_mem_burstcount_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_mem_burstcount_reg <= 3'd0;
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else if(avm_read && dbg_mem_vga && avm_waitrequest == 1'b0 && avm_burstcount > 3'd1) dbg_mem_burstcount_reg <= avm_burstcount - 3'd1;
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else if(dbg_mem_is_read_reg && avm_readdatavalid && dbg_mem_burstcount_reg > 3'd0) dbg_mem_burstcount_reg <= dbg_mem_burstcount_reg - 3'd1;
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else if(avm_write && dbg_mem_is_write_reg == 1'b0 && avm_waitrequest == 1'b0 && avm_burstcount > 3'd1) dbg_mem_burstcount_reg <= avm_burstcount - 3'd1;
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else if(avm_write && dbg_mem_is_write_reg && avm_waitrequest == 1'b0 && dbg_mem_burstcount_reg > 3'd0) dbg_mem_burstcount_reg <= dbg_mem_burstcount_reg - 3'd1;
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end
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wire dbg_mem_vga = avm_address >= 32'h000A0000 && avm_address < 32'h000C0000;
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reg dbg_mem_is_read_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_mem_is_read_reg <= 1'b0;
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else if(avm_read && dbg_mem_vga && avm_waitrequest == 1'b0) dbg_mem_is_read_reg <= 1'b1;
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else if(dbg_mem_is_read_reg && avm_readdatavalid && dbg_mem_burstcount_reg <= 3'd1) dbg_mem_is_read_reg <= 1'b0;
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end
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reg dbg_mem_is_write_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_mem_is_write_reg <= 1'b0;
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else if(avm_write && dbg_mem_is_write_reg == 1'b0 && avm_waitrequest == 1'b0 && avm_burstcount > 3'd1) dbg_mem_is_write_reg <= 1'b1;
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else if(avm_write && dbg_mem_is_write_reg && avm_waitrequest == 1'b0 && dbg_mem_burstcount_reg <= 3'd1) dbg_mem_is_write_reg <= 1'b0;
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end
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assign dbg_mem_address = (dbg_mem_is_read_reg || dbg_mem_is_write_reg)? dbg_mem_address_reg : avm_address;
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assign dbg_mem_byteenable = (dbg_mem_is_read_reg)? dbg_mem_byteenable_reg : avm_byteenable;
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assign dbg_mem_read = dbg_mem_is_read_reg && avm_readdatavalid;
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assign dbg_mem_write = avm_write && avm_waitrequest == 1'b0;
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assign dbg_mem_data = (dbg_mem_is_read_reg)? avm_readdata : avm_writedata;
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]
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ao486.v pipeline instantiation:
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[
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//debug
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.SW (SW), //input [17:0]
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.tb_finish_instr (tb_finish_instr) //output
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]
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soc.v:
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[
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//------------------------------------------------------------------------------
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wire dbg_tb_finish_instr;
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wire [15:0] dbg_io_address;
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wire [3:0] dbg_io_byteenable;
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wire dbg_io_write;
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wire dbg_io_read;
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wire [31:0] dbg_io_data;
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wire [7:0] dbg_int_vector;
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wire dbg_int;
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wire [7:0] dbg_exc_vector;
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wire dbg_exc;
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wire [31:0] dbg_mem_address;
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wire [3:0] dbg_mem_byteenable;
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wire dbg_mem_write;
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wire dbg_mem_read;
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wire [31:0] dbg_mem_data;
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//------------------------------------------------------------------------------ ethernet debug
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wire enet_rst_n;
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wire [5:0] enet_clk;
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altpll pll_eth_inst (
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.inclk ( {1'b0, CLOCK_50} ),
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.clk (enet_clk),
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.locked (enet_rst_n)
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);
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defparam
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pll_eth_inst.clk0_divide_by = 2,
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pll_eth_inst.clk0_duty_cycle = 50,
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pll_eth_inst.clk0_multiply_by = 5,
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pll_eth_inst.clk0_phase_shift = "0",
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pll_eth_inst.clk1_divide_by = 2,
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pll_eth_inst.clk1_duty_cycle = 50,
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pll_eth_inst.clk1_multiply_by = 5,
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pll_eth_inst.clk1_phase_shift = "2000",
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pll_eth_inst.compensate_clock = "CLK0",
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pll_eth_inst.inclk0_input_frequency = 20000,
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pll_eth_inst.operation_mode = "NO_COMPENSATION";
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wire enet_clk_data = enet_clk[0];
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wire enet_clk_clock = enet_clk[1];
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assign ENET0_RST_N = enet_rst_cnt == 20'hFFFFF;
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reg [19:0] enet_rst_cnt;
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always @(posedge enet_clk_data or negedge enet_rst_n) begin
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if(enet_rst_n == 1'b0) enet_rst_cnt <= 20'd0;
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else if(enet_rst_cnt < 20'hFFFFF) enet_rst_cnt <= enet_rst_cnt + 20'd1;
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end
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//------------------------------------------------------------------------------
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reg [39:0] dbg_tb_finish_instr_reg;
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always @(posedge clk_sys or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_tb_finish_instr_reg <= 40'd0;
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else if(dbg_tb_finish_instr) dbg_tb_finish_instr_reg <= dbg_tb_finish_instr_reg + 40'd1;
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end
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//------------------------------------------------------------------------------
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reg [7:0] dbg_int_vector_reg;
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reg dbg_int_reg;
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always @(posedge clk_sys or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_int_vector_reg <= 8'd0;
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else if(dbg_int_reg == 1'b0) dbg_int_vector_reg <= dbg_int_vector;
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end
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wire dbg_int_reg_lower = dbg_int_reg && dbg_mem_read_reg == 1'b0 && dbg_mem_write_reg == 1'b0 && dbg_io_read_reg == 1'b0 && dbg_io_write_reg == 1'b0;
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always @(posedge clk_sys or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_int_reg <= 1'd0;
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else if(dbg_int_reg == 1'b0) dbg_int_reg <= dbg_int;
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else if(dbg_int_reg_lower) dbg_int_reg <= 1'b0;
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end
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reg [7:0] dbg_exc_vector_reg;
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reg dbg_exc_reg;
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always @(posedge clk_sys or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_exc_vector_reg <= 8'd0;
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else if(dbg_exc_reg == 1'b0) dbg_exc_vector_reg <= dbg_exc_vector;
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end
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wire dbg_exc_reg_lower = dbg_exc_reg && dbg_mem_read_reg == 1'b0 && dbg_mem_write_reg == 1'b0 && dbg_io_read_reg == 1'b0 && dbg_io_write_reg == 1'b0 && dbg_int_reg == 1'b0;
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always @(posedge clk_sys or negedge rst_n) begin
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if(rst_n == 1'b0) dbg_exc_reg <= 1'd0;
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else if(dbg_exc_reg == 1'b0) dbg_exc_reg <= dbg_exc;
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else if(dbg_exc_reg_lower) dbg_exc_reg <= 1'b0;
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end
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reg [15:0] dbg_io_address_reg;
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reg [3:0] dbg_io_byteenable_reg;
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reg dbg_io_write_reg;
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reg dbg_io_read_reg;
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reg [31:0] dbg_io_data_reg;
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always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_io_address_reg <= 16'd0; else dbg_io_address_reg <= dbg_io_address; end
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|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_io_byteenable_reg <= 4'd0; else dbg_io_byteenable_reg <= dbg_io_byteenable; end
|
286 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_io_write_reg <= 1'd0; else dbg_io_write_reg <= dbg_io_write; end
|
287 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_io_read_reg <= 1'd0; else dbg_io_read_reg <= dbg_io_read; end
|
288 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_io_data_reg <= 32'd0; else dbg_io_data_reg <= dbg_io_data; end
|
289 |
|
|
|
290 |
|
|
reg [31:0] dbg_mem_address_reg;
|
291 |
|
|
reg [3:0] dbg_mem_byteenable_reg;
|
292 |
|
|
reg dbg_mem_write_reg;
|
293 |
|
|
reg dbg_mem_read_reg;
|
294 |
|
|
reg [31:0] dbg_mem_data_reg;
|
295 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_mem_address_reg <= 32'd0; else dbg_mem_address_reg <= dbg_mem_address; end
|
296 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_mem_byteenable_reg <= 4'd0; else dbg_mem_byteenable_reg <= dbg_mem_byteenable; end
|
297 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_mem_write_reg <= 1'd0; else dbg_mem_write_reg <= dbg_mem_write; end
|
298 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_mem_read_reg <= 1'd0; else dbg_mem_read_reg <= dbg_mem_read; end
|
299 |
|
|
always @(posedge clk_sys or negedge rst_n) begin if(rst_n == 1'b0) dbg_mem_data_reg <= 32'd0; else dbg_mem_data_reg <= dbg_mem_data; end
|
300 |
|
|
|
301 |
|
|
//------------------------------------------------------------------------------
|
302 |
|
|
|
303 |
|
|
wire [71:0] dbg_step1_q;
|
304 |
|
|
wire dbg_step1_empty;
|
305 |
|
|
wire [9:0] dbg_step1_usedw;
|
306 |
|
|
|
307 |
|
|
wire [71:0] dbg_a_next =
|
308 |
|
|
(dbg_mem_read_reg || dbg_mem_write_reg)? { 2'd1, dbg_mem_address_reg, dbg_mem_data_reg, dbg_mem_byteenable_reg, dbg_mem_write_reg, dbg_mem_read_reg } :
|
309 |
|
|
(dbg_io_read_reg || dbg_io_write_reg)? { 2'd2, 16'd0, dbg_io_address_reg, dbg_io_data_reg, dbg_io_byteenable_reg, dbg_io_write_reg, dbg_io_read_reg } :
|
310 |
|
|
(dbg_int_reg_lower)? { 2'd3, 22'd0, dbg_tb_finish_instr_reg, dbg_int_vector_reg } :
|
311 |
|
|
{ 2'd3, 1'd1, 21'd0, dbg_tb_finish_instr_reg, dbg_exc_vector_reg };
|
312 |
|
|
|
313 |
|
|
scfifo scfifo_a_inst(
|
314 |
|
|
.clock (clk_sys),
|
315 |
|
|
|
316 |
|
|
.wrreq (dbg_mem_read_reg || dbg_mem_write_reg || dbg_io_read_reg || dbg_io_write_reg || dbg_int_reg_lower || dbg_exc_reg_lower),
|
317 |
|
|
.data (dbg_a_next),
|
318 |
|
|
|
319 |
|
|
.rdreq (dbg_a_state_enable && dbg_a_state == 2'd2),
|
320 |
|
|
.q (dbg_step1_q),
|
321 |
|
|
.empty (dbg_step1_empty),
|
322 |
|
|
.usedw (dbg_step1_usedw)
|
323 |
|
|
);
|
324 |
|
|
defparam
|
325 |
|
|
scfifo_a_inst.lpm_width = 72,
|
326 |
|
|
scfifo_a_inst.lpm_widthu = 10,
|
327 |
|
|
scfifo_a_inst.lpm_numwords = 1024,
|
328 |
|
|
scfifo_a_inst.lpm_showahead = "ON";
|
329 |
|
|
|
330 |
|
|
wire dbg_a_state_start = dbg_step1_step >= 9'd12 && dbg_step1_step <= 9'd376 && dbg_a_state == 2'd0 && dbg_step1_empty == 1'b0;
|
331 |
|
|
wire dbg_a_state_enable= dbg_step1_step >= 9'd12 && dbg_step1_step <= 9'd376 && (dbg_a_state == 2'd1 || dbg_a_state == 2'd2);
|
332 |
|
|
|
333 |
|
|
reg [1:0] dbg_a_state;
|
334 |
|
|
always @(posedge clk_sys or negedge rst_n) begin
|
335 |
|
|
if(rst_n == 1'b0) dbg_a_state <= 2'd0;
|
336 |
|
|
else if(dbg_a_state_start) dbg_a_state <= 2'd1;
|
337 |
|
|
else if(dbg_a_state_enable && dbg_a_state == 2'd1) dbg_a_state <= 2'd2;
|
338 |
|
|
else if(dbg_a_state_enable && dbg_a_state == 2'd2) dbg_a_state <= 2'd0;
|
339 |
|
|
end
|
340 |
|
|
|
341 |
|
|
//------------------------------------------------------------------------------
|
342 |
|
|
|
343 |
|
|
// d4 3d 7e 00 e9 c4 - 00 11 22 33 44 55 - 08 00 -
|
344 |
|
|
// 45 00 05 d2 00 00 40 00 40 11 - 1e 51 - 0a 01 01 65 0a 01 01 64 //1490 = 365*4+ 20 + 8 + 2
|
345 |
|
|
// cc dd cc de 05 be 00 00
|
346 |
|
|
|
347 |
|
|
wire [31:0] dbg_step1_part =
|
348 |
|
|
(dbg_a_state == 2'd0)? dbg_step1_q[71:40] :
|
349 |
|
|
(dbg_a_state == 2'd1)? dbg_step1_q[39:8] :
|
350 |
|
|
{ dbg_step1_q[7:0], 24'd0 };
|
351 |
|
|
|
352 |
|
|
reg [19:0] dbg_step1_counter;
|
353 |
|
|
always @(posedge clk_sys or negedge rst_n) begin
|
354 |
|
|
if(rst_n == 1'b0) dbg_step1_counter <= 20'd0;
|
355 |
|
|
else if(dbg_step1_step_last) dbg_step1_counter <= 20'd0;
|
356 |
|
|
else if(dbg_step1_empty) dbg_step1_counter <= 20'd0;
|
357 |
|
|
else if(dbg_step1_step == 9'd0) dbg_step1_counter <= dbg_step1_counter + 20'd1;
|
358 |
|
|
end
|
359 |
|
|
|
360 |
|
|
wire dbg_step1_start =
|
361 |
|
|
dbg_step1_empty == 1'b0 && (dbg_step1_usedw == 10'd0 || dbg_step1_usedw > 10'd121 || dbg_step1_counter == 20'hFFFFF);
|
362 |
|
|
|
363 |
|
|
reg [8:0] dbg_step1_step;
|
364 |
|
|
always @(posedge clk_sys or negedge rst_n) begin
|
365 |
|
|
if(rst_n == 1'b0) dbg_step1_step <= 9'd0;
|
366 |
|
|
else if(dbg_step1_step == 9'd0 && dbg_step1_start) dbg_step1_step <= 9'd1;
|
367 |
|
|
else if(dbg_step1_step_last) dbg_step1_step <= 9'd0;
|
368 |
|
|
else if(dbg_step1_step > 9'd0) dbg_step1_step <= dbg_step1_step + 9'd1;
|
369 |
|
|
end
|
370 |
|
|
|
371 |
|
|
wire dbg_step1_step_last = dbg_step1_step == 9'd376;
|
372 |
|
|
|
373 |
|
|
reg [15:0] dbg_io_counter;
|
374 |
|
|
always @(posedge clk_sys or negedge rst_n) begin
|
375 |
|
|
if(rst_n == 1'b0) dbg_io_counter <= 16'd0;
|
376 |
|
|
else if(dbg_step1_step == 9'd11) dbg_io_counter <= dbg_io_counter + 16'd1;
|
377 |
|
|
end
|
378 |
|
|
|
379 |
|
|
wire [31:0] dbg_step1_next =
|
380 |
|
|
(dbg_step1_step == 9'd1)? 32'hD43D7E00 :
|
381 |
|
|
(dbg_step1_step == 9'd2)? 32'hE9C40011 :
|
382 |
|
|
(dbg_step1_step == 9'd3)? 32'h22334455 :
|
383 |
|
|
(dbg_step1_step == 9'd4)? 32'h08004500 :
|
384 |
|
|
(dbg_step1_step == 9'd5)? 32'h05D20000 :
|
385 |
|
|
(dbg_step1_step == 9'd6)? 32'h40004011 :
|
386 |
|
|
(dbg_step1_step == 9'd7)? 32'h1E510A01 :
|
387 |
|
|
(dbg_step1_step == 9'd8)? 32'h01650A01 :
|
388 |
|
|
(dbg_step1_step == 9'd9)? 32'h0164CCDD :
|
389 |
|
|
(dbg_step1_step == 9'd10)? 32'hCCDE05BE :
|
390 |
|
|
(dbg_step1_step == 9'd11)? { 16'h0000, dbg_io_counter } :
|
391 |
|
|
(dbg_step1_empty)? 32'h00000000 :
|
392 |
|
|
dbg_step1_part;
|
393 |
|
|
|
394 |
|
|
//------------------------------------------------------------------------------
|
395 |
|
|
|
396 |
|
|
wire [34:0] out_dc_q;
|
397 |
|
|
wire out_dc_empty;
|
398 |
|
|
wire [9:0] out_dc_rdusedw;
|
399 |
|
|
|
400 |
|
|
dcfifo dcfifo_inst(
|
401 |
|
|
.wrclk (clk_sys),
|
402 |
|
|
.wrreq (dbg_step1_step != 9'd0),
|
403 |
|
|
.data ({ dbg_step1_step_last, 2'b0, dbg_step1_next }),
|
404 |
|
|
|
405 |
|
|
.rdclk (enet_clk_data),
|
406 |
|
|
.rdreq (out_dc_rdreq),
|
407 |
|
|
.q (out_dc_q),
|
408 |
|
|
.rdempty (out_dc_empty),
|
409 |
|
|
.rdusedw (out_dc_rdusedw)
|
410 |
|
|
);
|
411 |
|
|
defparam
|
412 |
|
|
dcfifo_inst.lpm_width = 35,
|
413 |
|
|
dcfifo_inst.lpm_widthu = 10,
|
414 |
|
|
dcfifo_inst.lpm_numwords = 1024;
|
415 |
|
|
|
416 |
|
|
wire out_dc_rdreq;
|
417 |
|
|
mac_output mac_output_inst(
|
418 |
|
|
.clk_data (enet_clk_data),
|
419 |
|
|
.clk_clock (enet_clk_clock),
|
420 |
|
|
.rst_n (enet_rst_n),
|
421 |
|
|
|
422 |
|
|
.fifo_empty (out_dc_empty || out_dc_rdusedw < 10'd375),
|
423 |
|
|
.fifo_rdreq (out_dc_rdreq),
|
424 |
|
|
// 34: end, 33,32: not valid
|
425 |
|
|
.fifo_q (out_dc_q),
|
426 |
|
|
|
427 |
|
|
.phy_txc (ENET0_GTX_CLK),
|
428 |
|
|
.phy_ddio_td (ENET0_TX_DATA),
|
429 |
|
|
.phy_ddio_tx_ctl(ENET0_TX_EN),
|
430 |
|
|
|
431 |
|
|
.slow (1'b0)
|
432 |
|
|
);
|
433 |
|
|
|
434 |
|
|
//------------------------------------------------------------------------------
|
435 |
|
|
|
436 |
|
|
endmodule
|
437 |
|
|
|
438 |
|
|
//------------------------------------------------------------------------------ ethernet output mac
|
439 |
|
|
|
440 |
|
|
module mac_output(
|
441 |
|
|
input clk_data,
|
442 |
|
|
input clk_clock,
|
443 |
|
|
input rst_n,
|
444 |
|
|
|
445 |
|
|
input fifo_empty,
|
446 |
|
|
output fifo_rdreq,
|
447 |
|
|
// 34: end, 33,32: not valid
|
448 |
|
|
input [34:0] fifo_q,
|
449 |
|
|
|
450 |
|
|
output phy_txc,
|
451 |
|
|
output [3:0] phy_ddio_td,
|
452 |
|
|
output phy_ddio_tx_ctl,
|
453 |
|
|
|
454 |
|
|
input slow
|
455 |
|
|
);
|
456 |
|
|
|
457 |
|
|
// *************************************************** TXC clock
|
458 |
|
|
|
459 |
|
|
altddio_out ddio_clk_inst(
|
460 |
|
|
.outclock (clk_clock),
|
461 |
|
|
|
462 |
|
|
.datain_h (1'b1),
|
463 |
|
|
.datain_l (1'b0),
|
464 |
|
|
|
465 |
|
|
.dataout (phy_txc)
|
466 |
|
|
);
|
467 |
|
|
defparam ddio_clk_inst.width = 1;
|
468 |
|
|
|
469 |
|
|
|
470 |
|
|
// *************************************************** DDIO
|
471 |
|
|
|
472 |
|
|
wire [7:0] phy_data_final;
|
473 |
|
|
reg phy_valid;
|
474 |
|
|
|
475 |
|
|
altddio_out ddio_td_inst(
|
476 |
|
|
.outclock (clk_data),
|
477 |
|
|
|
478 |
|
|
.datain_h (phy_data_final[3:0]),
|
479 |
|
|
.datain_l (phy_data_final[7:4]),
|
480 |
|
|
|
481 |
|
|
.dataout (phy_ddio_td)
|
482 |
|
|
);
|
483 |
|
|
defparam ddio_td_inst.width = 4;
|
484 |
|
|
|
485 |
|
|
altddio_out ddio_tx_ctl_inst(
|
486 |
|
|
.outclock (clk_data),
|
487 |
|
|
|
488 |
|
|
.datain_h (phy_valid),
|
489 |
|
|
.datain_l (phy_valid),
|
490 |
|
|
|
491 |
|
|
.dataout (phy_ddio_tx_ctl)
|
492 |
|
|
);
|
493 |
|
|
defparam ddio_tx_ctl_inst.width = 1;
|
494 |
|
|
|
495 |
|
|
wire idle;
|
496 |
|
|
|
497 |
|
|
// *************************************************** speed
|
498 |
|
|
reg slow_reg_1;
|
499 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
500 |
|
|
if(rst_n == 1'b0) slow_reg_1 <= 1'b0;
|
501 |
|
|
else slow_reg_1 <= slow;
|
502 |
|
|
end
|
503 |
|
|
|
504 |
|
|
reg slow_reg_2;
|
505 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
506 |
|
|
if(rst_n == 1'b0) slow_reg_2 <= 1'b0;
|
507 |
|
|
else slow_reg_2 <= slow_reg_1;
|
508 |
|
|
end
|
509 |
|
|
|
510 |
|
|
reg slow_reg;
|
511 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
512 |
|
|
if(rst_n == 1'b0) slow_reg <= 1'b0;
|
513 |
|
|
else if(slow_reg_1 == slow_reg_2 && idle) slow_reg <= slow_reg_2;
|
514 |
|
|
end
|
515 |
|
|
|
516 |
|
|
reg toggle;
|
517 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
518 |
|
|
if(rst_n == 1'b0) toggle <= 1'b0;
|
519 |
|
|
else if(slow_reg) toggle <= ~toggle;
|
520 |
|
|
else toggle <= 1'b0;
|
521 |
|
|
end
|
522 |
|
|
|
523 |
|
|
wire enabled = slow_reg == 1'b0 || toggle;
|
524 |
|
|
|
525 |
|
|
// *************************************************** data path
|
526 |
|
|
|
527 |
|
|
wire [31:0] crc_output;
|
528 |
|
|
wire crc_load;
|
529 |
|
|
|
530 |
|
|
wire start_preamble;
|
531 |
|
|
reg [2:0] preamble_cnt;
|
532 |
|
|
wire phy_valid_value;
|
533 |
|
|
|
534 |
|
|
|
535 |
|
|
reg fifo_rdreq_reg;
|
536 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
537 |
|
|
if(rst_n == 1'b0) fifo_rdreq_reg <= 1'b0;
|
538 |
|
|
else fifo_rdreq_reg <= fifo_rdreq;
|
539 |
|
|
end
|
540 |
|
|
|
541 |
|
|
reg [7:0] phy_data_1;
|
542 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
543 |
|
|
if(rst_n == 1'b0) phy_data_1 <= 8'd0;
|
544 |
|
|
else if(enabled) begin
|
545 |
|
|
if(fifo_rdreq_reg) phy_data_1 <= fifo_q[7:0];
|
546 |
|
|
end
|
547 |
|
|
end
|
548 |
|
|
|
549 |
|
|
reg [7:0] phy_data_2;
|
550 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
551 |
|
|
if(rst_n == 1'b0) phy_data_2 <= 8'd0;
|
552 |
|
|
else if(enabled) begin
|
553 |
|
|
if(crc_load) phy_data_2 <= crc_output[7:0];
|
554 |
|
|
else if(fifo_rdreq_reg) phy_data_2 <= fifo_q[15:8];
|
555 |
|
|
else phy_data_2 <= phy_data_1;
|
556 |
|
|
end
|
557 |
|
|
end
|
558 |
|
|
|
559 |
|
|
reg [7:0] phy_data_3;
|
560 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
561 |
|
|
if(rst_n == 1'b0) phy_data_3 <= 8'd0;
|
562 |
|
|
else if(enabled) begin
|
563 |
|
|
if(crc_load) phy_data_3 <= crc_output[15:8];
|
564 |
|
|
else if(fifo_rdreq_reg) phy_data_3 <= fifo_q[23:16];
|
565 |
|
|
else phy_data_3 <= phy_data_2;
|
566 |
|
|
end
|
567 |
|
|
end
|
568 |
|
|
|
569 |
|
|
reg [7:0] phy_data_4;
|
570 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
571 |
|
|
if(rst_n == 1'b0) phy_data_4 <= 8'd0;
|
572 |
|
|
else if(enabled) begin
|
573 |
|
|
if(crc_load) phy_data_4 <= crc_output[23:16];
|
574 |
|
|
else if(fifo_rdreq_reg) phy_data_4 <= fifo_q[31:24];
|
575 |
|
|
else phy_data_4 <= phy_data_3;
|
576 |
|
|
end
|
577 |
|
|
end
|
578 |
|
|
|
579 |
|
|
reg [7:0] phy_data_5;
|
580 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
581 |
|
|
if(rst_n == 1'b0) phy_data_5 <= 8'd0;
|
582 |
|
|
else if(enabled) begin
|
583 |
|
|
if(crc_load) phy_data_5 <= crc_output[31:24];
|
584 |
|
|
else if(preamble_cnt == 3'd7) phy_data_5 <= 8'hD5;
|
585 |
|
|
else if(start_preamble || preamble_cnt != 3'd0) phy_data_5 <= 8'h55;
|
586 |
|
|
else if(phy_valid_value == 1'b0) phy_data_5 <= 8'h00;
|
587 |
|
|
else phy_data_5 <= phy_data_4;
|
588 |
|
|
end
|
589 |
|
|
end
|
590 |
|
|
|
591 |
|
|
//-
|
592 |
|
|
assign phy_data_final = (slow == 1'b0)? phy_data_5 : (enabled)? { phy_data_5[7:4], phy_data_5[7:4] } : { phy_data_5[3:0], phy_data_5[3:0] };
|
593 |
|
|
|
594 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
595 |
|
|
if(rst_n == 1'b0) phy_valid <= 1'b0;
|
596 |
|
|
else if(enabled) begin
|
597 |
|
|
phy_valid <= phy_valid_value;
|
598 |
|
|
end
|
599 |
|
|
end
|
600 |
|
|
|
601 |
|
|
// *************************************************** counters
|
602 |
|
|
|
603 |
|
|
reg [2:0] left_cnt;
|
604 |
|
|
reg [4:0] gap_cnt;
|
605 |
|
|
reg [31:0] crc;
|
606 |
|
|
|
607 |
|
|
assign idle = preamble_cnt == 4'd0 && left_cnt == 3'd0 && gap_cnt == 5'd0;
|
608 |
|
|
assign start_preamble = idle && fifo_empty == 1'b0;
|
609 |
|
|
|
610 |
|
|
assign phy_valid_value = start_preamble || preamble_cnt != 4'd0 || left_cnt != 3'd0 || gap_cnt >= 5'd13;
|
611 |
|
|
wire crc_count = left_cnt != 3'd0 || gap_cnt >= 5'd17;
|
612 |
|
|
assign crc_load = gap_cnt == 5'd16;
|
613 |
|
|
|
614 |
|
|
assign fifo_rdreq = (slow_reg == 1'b0 && (preamble_cnt == 4'd6 || left_cnt == 3'd2)) || (slow_reg && enabled == 1'b0 && (preamble_cnt == 4'd7 || left_cnt == 3'd1));
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
618 |
|
|
if(rst_n == 1'b0) preamble_cnt <= 3'd0;
|
619 |
|
|
else if(enabled) begin
|
620 |
|
|
if(start_preamble || preamble_cnt != 3'd0) preamble_cnt <= preamble_cnt + 3'd1;
|
621 |
|
|
end
|
622 |
|
|
end
|
623 |
|
|
|
624 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
625 |
|
|
if(rst_n == 1'b0) left_cnt <= 3'd0;
|
626 |
|
|
else if(enabled) begin
|
627 |
|
|
if(fifo_rdreq_reg && fifo_q[34] == 1'b0) left_cnt <= 3'd4;
|
628 |
|
|
else if(fifo_rdreq_reg) left_cnt <= 3'd0;
|
629 |
|
|
else if(left_cnt > 3'd0) left_cnt <= left_cnt - 3'd1;
|
630 |
|
|
end
|
631 |
|
|
end
|
632 |
|
|
|
633 |
|
|
|
634 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
635 |
|
|
if(rst_n == 1'b0) gap_cnt <= 5'd0;
|
636 |
|
|
else if(enabled) begin
|
637 |
|
|
if(fifo_rdreq_reg && fifo_q[34] == 1'b1) gap_cnt <= 5'd20 - { 3'b0, fifo_q[33:32] };
|
638 |
|
|
else if(gap_cnt > 5'd0) gap_cnt <= gap_cnt - 5'd1;
|
639 |
|
|
end
|
640 |
|
|
end
|
641 |
|
|
|
642 |
|
|
|
643 |
|
|
// *************************************************** crc
|
644 |
|
|
|
645 |
|
|
wire [31:0] crc_rev = {
|
646 |
|
|
crc[24],crc[25],crc[26],crc[27],crc[28],crc[29],crc[30],crc[31],
|
647 |
|
|
crc[16],crc[17],crc[18],crc[19],crc[20],crc[21],crc[22],crc[23],
|
648 |
|
|
crc[8], crc[9], crc[10],crc[11],crc[12],crc[13],crc[14],crc[15],
|
649 |
|
|
crc[0], crc[1], crc[2], crc[3], crc[4], crc[5], crc[6], crc[7]
|
650 |
|
|
};
|
651 |
|
|
|
652 |
|
|
assign crc_output = ~crc_rev;
|
653 |
|
|
|
654 |
|
|
wire [31:0] crc_next = {
|
655 |
|
|
phy_data_4[2] ^ crc[23] ^ crc[29],
|
656 |
|
|
phy_data_4[0] ^ phy_data_4[3] ^ crc[22] ^ crc[28] ^ crc[31],
|
657 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[4] ^ crc[21] ^ crc[27] ^ crc[30] ^ crc[31],
|
658 |
|
|
phy_data_4[1] ^ phy_data_4[2] ^ phy_data_4[5] ^ crc[20] ^ crc[26] ^ crc[29] ^ crc[30],
|
659 |
|
|
phy_data_4[0] ^ phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[6] ^ crc[19] ^ crc[25] ^ crc[28] ^ crc[29] ^ crc[31],
|
660 |
|
|
phy_data_4[1] ^ phy_data_4[3] ^ phy_data_4[4] ^ phy_data_4[7] ^ crc[18] ^ crc[24] ^ crc[27] ^ crc[28] ^ crc[30],
|
661 |
|
|
phy_data_4[4] ^ phy_data_4[5] ^ crc[17] ^ crc[26] ^ crc[27],
|
662 |
|
|
phy_data_4[0] ^ phy_data_4[5] ^ phy_data_4[6] ^ crc[16] ^ crc[25] ^ crc[26] ^ crc[31],
|
663 |
|
|
phy_data_4[1] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[15] ^ crc[24] ^ crc[25] ^ crc[30],
|
664 |
|
|
phy_data_4[7] ^ crc[14] ^ crc[24],
|
665 |
|
|
phy_data_4[2] ^ crc[13] ^ crc[29],
|
666 |
|
|
phy_data_4[3] ^ crc[12] ^ crc[28],
|
667 |
|
|
phy_data_4[0] ^ phy_data_4[4] ^ crc[11] ^ crc[27] ^ crc[31],
|
668 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[5] ^ crc[10] ^ crc[26] ^ crc[30] ^ crc[31],
|
669 |
|
|
phy_data_4[1] ^ phy_data_4[2] ^ phy_data_4[6] ^ crc[9] ^ crc[25] ^ crc[29] ^ crc[30],
|
670 |
|
|
phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[7] ^ crc[8] ^ crc[24] ^ crc[28] ^ crc[29],
|
671 |
|
|
phy_data_4[0] ^ phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[4] ^ crc[7] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[31],
|
672 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[3] ^ phy_data_4[4] ^ phy_data_4[5] ^ crc[6] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30] ^ crc[31],
|
673 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[2] ^ phy_data_4[4] ^ phy_data_4[5] ^ phy_data_4[6] ^ crc[5] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[30] ^ crc[31],
|
674 |
|
|
phy_data_4[1] ^ phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[5] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[4] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30],
|
675 |
|
|
phy_data_4[3] ^ phy_data_4[4] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[3] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28],
|
676 |
|
|
phy_data_4[2] ^ phy_data_4[4] ^ phy_data_4[5] ^ phy_data_4[7] ^ crc[2] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29],
|
677 |
|
|
phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[5] ^ phy_data_4[6] ^ crc[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29],
|
678 |
|
|
phy_data_4[3] ^ phy_data_4[4] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28],
|
679 |
|
|
phy_data_4[0] ^ phy_data_4[2] ^ phy_data_4[4] ^ phy_data_4[5] ^ phy_data_4[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[31],
|
680 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[5] ^ phy_data_4[6] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31],
|
681 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[2] ^ phy_data_4[3] ^ phy_data_4[4] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31],
|
682 |
|
|
phy_data_4[1] ^ phy_data_4[3] ^ phy_data_4[4] ^ phy_data_4[5] ^ phy_data_4[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30],
|
683 |
|
|
phy_data_4[0] ^ phy_data_4[4] ^ phy_data_4[5] ^ phy_data_4[6] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[31],
|
684 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[5] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[30] ^ crc[31],
|
685 |
|
|
phy_data_4[0] ^ phy_data_4[1] ^ phy_data_4[6] ^ phy_data_4[7] ^ crc[24] ^ crc[25] ^ crc[30] ^ crc[31],
|
686 |
|
|
phy_data_4[1] ^ phy_data_4[7] ^ crc[24] ^ crc[30]
|
687 |
|
|
};
|
688 |
|
|
|
689 |
|
|
always @(posedge clk_data or negedge rst_n) begin
|
690 |
|
|
if(rst_n == 1'b0) crc <= 32'hFFFFFFFF;
|
691 |
|
|
else if(enabled) begin
|
692 |
|
|
if(crc_count) crc <= crc_next;
|
693 |
|
|
else if(crc_load) crc <= 32'hFFFFFFFF;
|
694 |
|
|
end
|
695 |
|
|
end
|
696 |
|
|
|
697 |
|
|
endmodule
|
698 |
|
|
]
|
699 |
|
|
|
700 |
|
|
--------------------------------------------------------------------------------
|
701 |
|
|
--------------------------------------------------------------------------------
|
702 |
|
|
--------------------------------------------------------------------------------
|
703 |
|
|
For disabling the pipeline (serial insruction execution):
|
704 |
|
|
|
705 |
|
|
pipeline.v write instantiation:
|
706 |
|
|
[
|
707 |
|
|
.tb_finish_instr (tb_finish_instr)
|
708 |
|
|
]
|
709 |
|
|
|
710 |
|
|
write.v ports:
|
711 |
|
|
[
|
712 |
|
|
//debug
|
713 |
|
|
output tb_finish_instr
|
714 |
|
|
]
|
715 |
|
|
|
716 |
|
|
write.v:
|
717 |
|
|
[
|
718 |
|
|
assign tb_finish_instr = wr_finished || (wr_ready && wr_hlt_in_progress);
|
719 |
|
|
]
|
720 |
|
|
|
721 |
|
|
soc.v ports:
|
722 |
|
|
[
|
723 |
|
|
//debug
|
724 |
|
|
input [17:0] SW,
|
725 |
|
|
]
|
726 |
|
|
|
727 |
|
|
soc.v u0 instantiation:
|
728 |
|
|
[
|
729 |
|
|
//debug
|
730 |
|
|
.ao486_debug_sw_export (SW),
|
731 |
|
|
]
|
732 |
|
|
|
733 |
|
|
--------------------------------------------------------------------------------
|
734 |
|
|
--------------------------------------------------------------------------------
|
735 |
|
|
--------------------------------------------------------------------------------
|
736 |
|
|
|
737 |
|
|
pit.v:
|
738 |
|
|
[
|
739 |
|
|
/*
|
740 |
|
|
reg counter_1_out_last;
|
741 |
|
|
always @(posedge clk or negedge rst_n) begin
|
742 |
|
|
if(rst_n == 1'b0) counter_1_out_last <= 1'b0;
|
743 |
|
|
else counter_1_out_last <= counter_1_out;
|
744 |
|
|
end
|
745 |
|
|
|
746 |
|
|
reg counter_1_toggle;
|
747 |
|
|
always @(posedge clk or negedge rst_n) begin
|
748 |
|
|
if(rst_n == 1'b0) counter_1_toggle <= 1'b0;
|
749 |
|
|
else if(counter_1_out_last == 1'b0 && counter_1_out == 1'b1) counter_1_toggle <= ~(counter_1_toggle);
|
750 |
|
|
end
|
751 |
|
|
*/
|
752 |
|
|
]
|
753 |
|
|
|
754 |
|
|
--------------------------------------------------------------------------------
|
755 |
|
|
--------------------------------------------------------------------------------
|
756 |
|
|
--------------------------------------------------------------------------------
|
757 |
|
|
|
758 |
|
|
TODO list:
|
759 |
|
|
|
760 |
|
|
floppy.v:
|
761 |
|
|
[
|
762 |
|
|
//TODO: in execute_ndma -- send irq after every byte
|
763 |
|
|
]
|
764 |
|
|
|
765 |
|
|
ao486:
|
766 |
|
|
[
|
767 |
|
|
//TODO: if repeat and interrupt --> eip = eip_prev;
|
768 |
|
|
//TODO: IN,INS, OUT,OUTS --> wait for prev. instr. -- exception possible
|
769 |
|
|
|
770 |
|
|
//TODO: task switch --> disable inhibits and debug traps
|
771 |
|
|
//TODO: interrupt --> disable inhibits and debug traps
|
772 |
|
|
//TODO: task switch --> IRET -- test with PG active
|
773 |
|
|
|
774 |
|
|
//TODO: read io only once in rd (if pipeline blocked, many reads can start)
|
775 |
|
|
|
776 |
|
|
//TODO: tlbflushall in memory
|
777 |
|
|
|
778 |
|
|
//TODO: wait in mult/div with busy=0 (wr can be busy)
|
779 |
|
|
|
780 |
|
|
//TODO: tflag_to_reg -- check if wr stage does not block
|
781 |
|
|
|
782 |
|
|
//TODO: JCXZ,LOOP .... reset pr,micro,dec; exe,wr can reset again
|
783 |
|
|
|
784 |
|
|
//TODO: tlb 2.6.2: if(pg disabled) access bits not set
|
785 |
|
|
|
786 |
|
|
//TODO: 2.6.2: EXT, change in table (?)
|
787 |
|
|
|
788 |
|
|
//TODO: 2.6.2: single-step after task switch
|
789 |
|
|
|
790 |
|
|
//TODO: interrupt_do -- in write checked and in exception -- must keep stable unit one cycle after interrupt_done -- changed:
|
791 |
|
|
// cycle 1: interrupt_do active
|
792 |
|
|
// cycle 2: interrupt_do don't care
|
793 |
|
|
// cycle 3: interrupt_done active for one cycle; interrupt_vector is sampled
|
794 |
|
|
|
795 |
|
|
//TODO: error code push test in exception
|
796 |
|
|
|
797 |
|
|
//TODO: soc: dma transfer and caching
|
798 |
|
|
|
799 |
|
|
//TODO: write to code already prefetched
|
800 |
|
|
//assign wr_req_reset_write_over_prefetch = wr_finished && write_for_wr_ready && write_over_prefetch && ~(wr_eip_has_next_eip);
|
801 |
|
|
//assign wr_eip_from_wr_eip = wr_exe_eip_from_wr_eip || wr_req_reset_write_over_prefetch;
|
802 |
|
|
|
803 |
|
|
/*
|
804 |
|
|
-T in TSS
|
805 |
|
|
-TF (inhibit; with RF in string instructions)
|
806 |
|
|
-instruction breakpoint
|
807 |
|
|
-data breakpoint
|
808 |
|
|
-debug registers (MOV; updates; exceptions)
|
809 |
|
|
AC flag
|
810 |
|
|
INVD,WBINVD,INVLPG
|
811 |
|
|
MOV Dx
|
812 |
|
|
|
813 |
|
|
-debug
|
814 |
|
|
-paging
|
815 |
|
|
*/
|
816 |
|
|
|
817 |
|
|
// From bochs arith32.cc version 2.4
|
818 |
|
|
// Some info on the opcodes at {0F,A6} and {0F,A7}
|
819 |
|
|
// On 386 steps A0-B0:
|
820 |
|
|
// {OF,A6} = XBTS
|
821 |
|
|
// {OF,A7} = IBTS
|
822 |
|
|
// On 486 steps A0-B0:
|
823 |
|
|
// {OF,A6} = CMPXCHG 8
|
824 |
|
|
// {OF,A7} = CMPXCHG 16|32
|
825 |
|
|
//
|
826 |
|
|
// On 486 >= B steps, and further processors, the
|
827 |
|
|
// CMPXCHG instructions were moved to opcodes:
|
828 |
|
|
// {OF,B0} = CMPXCHG 8
|
829 |
|
|
// {OF,B1} = CMPXCHG 16|32
|
830 |
|
|
]
|
831 |
|
|
|
832 |
|
|
defines.v mutex:
|
833 |
|
|
[
|
834 |
|
|
//`include "startup_from_sim.v"
|
835 |
|
|
//TODO: check that exe_waiting is active, if e*x is used in exe and busy_full[] is used
|
836 |
|
|
]
|