1 |
2 |
alfik |
//======================================================== conditions
|
2 |
|
|
wire cond_0 = state == STATE_IDLE;
|
3 |
|
|
wire cond_1 = invdcode_do;
|
4 |
|
|
wire cond_2 = ~(dcachetoicache_accept_empty);
|
5 |
|
|
wire cond_3 = ~(pr_reset) && icacheread_do && icacheread_length > 5'd0;
|
6 |
|
|
wire cond_4 = icacheread_do && icacheread_cache_disable;
|
7 |
|
|
wire cond_5 = icacheread_do && ~(icacheread_cache_disable);
|
8 |
|
|
wire cond_6 = state == STATE_INVALIDATE_WRITE;
|
9 |
|
|
wire cond_7 = state == STATE_CHECK;
|
10 |
|
|
wire cond_8 = matched;
|
11 |
|
|
wire cond_9 = pr_reset == `FALSE && reset_waiting == `FALSE;
|
12 |
|
|
wire cond_10 = ~(cache_disable);
|
13 |
|
|
wire cond_11 = state == STATE_READ;
|
14 |
|
|
wire cond_12 = readcode_partial_done || readcode_done;
|
15 |
|
|
wire cond_13 = partial_length[2:0] > 3'd0 && length > 5'd0;
|
16 |
|
|
wire cond_14 = readcode_done && ~(cache_disable);
|
17 |
|
|
wire cond_15 = plru_index[1:0] == 2'd0;
|
18 |
|
|
wire cond_16 = plru_index[1:0] == 2'd1;
|
19 |
|
|
wire cond_17 = plru_index[1:0] == 2'd2;
|
20 |
|
|
wire cond_18 = plru_index[1:0] == 2'd3;
|
21 |
|
|
wire cond_19 = readcode_done;
|
22 |
|
|
//======================================================== saves
|
23 |
|
|
wire [31:0] address_to_reg =
|
24 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( dcachetoicache_accept_address) :
|
25 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( icacheread_address) :
|
26 |
|
|
address;
|
27 |
|
|
wire [1:0] state_to_reg =
|
28 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( STATE_INVALIDATE_WRITE) :
|
29 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3 && cond_4)? ( STATE_CHECK) :
|
30 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3 && cond_5)? ( STATE_CHECK) :
|
31 |
|
|
(cond_6)? ( STATE_IDLE) :
|
32 |
|
|
(cond_7 && cond_8)? ( STATE_IDLE) :
|
33 |
|
|
(cond_7 && ~cond_8 && cond_10)? ( STATE_READ) :
|
34 |
|
|
(cond_7 && ~cond_8 && ~cond_10)? ( STATE_READ) :
|
35 |
|
|
(cond_11 && cond_19)? ( STATE_IDLE) :
|
36 |
|
|
state;
|
37 |
|
|
wire [4:0] length_to_reg =
|
38 |
|
|
(cond_0)? ( icacheread_length) :
|
39 |
|
|
(cond_11 && cond_9 && cond_12 && cond_13)? ( length - partial_length_current) :
|
40 |
|
|
length;
|
41 |
|
|
wire cache_disable_to_reg =
|
42 |
|
|
(cond_0)? ( icacheread_cache_disable) :
|
43 |
|
|
cache_disable;
|
44 |
|
|
wire [11:0] partial_length_to_reg =
|
45 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3 && cond_4)? ( length_burst) :
|
46 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3 && cond_5)? ( length_line) :
|
47 |
|
|
(cond_11 && cond_9 && cond_12)? ( { 3'd0, partial_length[11:3] }) :
|
48 |
|
|
partial_length;
|
49 |
|
|
//======================================================== always
|
50 |
|
|
always @(posedge clk or negedge rst_n) begin
|
51 |
|
|
if(rst_n == 1'b0) address <= 32'd0;
|
52 |
|
|
else address <= address_to_reg;
|
53 |
|
|
end
|
54 |
|
|
always @(posedge clk or negedge rst_n) begin
|
55 |
|
|
if(rst_n == 1'b0) state <= 2'd0;
|
56 |
|
|
else state <= state_to_reg;
|
57 |
|
|
end
|
58 |
|
|
always @(posedge clk or negedge rst_n) begin
|
59 |
|
|
if(rst_n == 1'b0) length <= 5'd0;
|
60 |
|
|
else length <= length_to_reg;
|
61 |
|
|
end
|
62 |
|
|
always @(posedge clk or negedge rst_n) begin
|
63 |
|
|
if(rst_n == 1'b0) cache_disable <= 1'd0;
|
64 |
|
|
else cache_disable <= cache_disable_to_reg;
|
65 |
|
|
end
|
66 |
|
|
always @(posedge clk or negedge rst_n) begin
|
67 |
|
|
if(rst_n == 1'b0) partial_length <= 12'd0;
|
68 |
|
|
else partial_length <= partial_length_to_reg;
|
69 |
|
|
end
|
70 |
|
|
//======================================================== sets
|
71 |
|
|
assign control_ram_read_do =
|
72 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
73 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? (`TRUE) :
|
74 |
|
|
1'd0;
|
75 |
|
|
assign data_ram3_write_do =
|
76 |
|
|
(cond_11 && cond_9 && cond_14 && cond_18)? (`TRUE) :
|
77 |
|
|
1'd0;
|
78 |
|
|
assign data_ram0_address =
|
79 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( dcachetoicache_accept_address) :
|
80 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( icacheread_address) :
|
81 |
|
|
(cond_11 && cond_9 && cond_14 && cond_15)? ( address) :
|
82 |
|
|
32'd0;
|
83 |
|
|
assign readcode_do =
|
84 |
|
|
(cond_7 && ~cond_8 && cond_10)? (`TRUE) :
|
85 |
|
|
(cond_7 && ~cond_8 && ~cond_10)? (`TRUE) :
|
86 |
|
|
1'd0;
|
87 |
|
|
assign data_ram0_data =
|
88 |
|
|
(cond_11 && cond_9 && cond_14 && cond_15)? ( readcode_line) :
|
89 |
|
|
128'd0;
|
90 |
|
|
assign data_ram1_write_do =
|
91 |
|
|
(cond_11 && cond_9 && cond_14 && cond_16)? (`TRUE) :
|
92 |
|
|
1'd0;
|
93 |
|
|
assign data_ram0_read_do =
|
94 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
95 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? (`TRUE) :
|
96 |
|
|
1'd0;
|
97 |
|
|
assign data_ram2_data =
|
98 |
|
|
(cond_11 && cond_9 && cond_14 && cond_17)? ( readcode_line) :
|
99 |
|
|
128'd0;
|
100 |
|
|
assign readcode_address =
|
101 |
|
|
(cond_7 && ~cond_8 && cond_10)? ( { address[31:4], 4'd0 }) :
|
102 |
|
|
(cond_7 && ~cond_8 && ~cond_10)? ( { address[31:2], 2'd0 }) :
|
103 |
|
|
32'd0;
|
104 |
|
|
assign dcachetoicache_accept_do =
|
105 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
106 |
|
|
1'd0;
|
107 |
|
|
assign prefetched_do =
|
108 |
|
|
(cond_7 && cond_8 && cond_9)? (`TRUE) :
|
109 |
|
|
(cond_11 && cond_9 && cond_12 && cond_13)? (`TRUE) :
|
110 |
|
|
1'd0;
|
111 |
|
|
assign prefetched_length =
|
112 |
|
|
(cond_7 && cond_8 && cond_9)? ( 5'd16 - { 1'b0, address[3:0] }) :
|
113 |
|
|
(cond_11 && cond_9 && cond_12 && cond_13)? ( partial_length_current) :
|
114 |
|
|
5'd0;
|
115 |
|
|
assign data_ram0_write_do =
|
116 |
|
|
(cond_11 && cond_9 && cond_14 && cond_15)? (`TRUE) :
|
117 |
|
|
1'd0;
|
118 |
|
|
assign data_ram1_read_do =
|
119 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
120 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? (`TRUE) :
|
121 |
|
|
1'd0;
|
122 |
|
|
assign data_ram2_write_do =
|
123 |
|
|
(cond_11 && cond_9 && cond_14 && cond_17)? (`TRUE) :
|
124 |
|
|
1'd0;
|
125 |
|
|
assign data_ram3_data =
|
126 |
|
|
(cond_11 && cond_9 && cond_14 && cond_18)? ( readcode_line) :
|
127 |
|
|
128'd0;
|
128 |
|
|
assign data_ram3_read_do =
|
129 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
130 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? (`TRUE) :
|
131 |
|
|
1'd0;
|
132 |
|
|
assign data_ram3_address =
|
133 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( dcachetoicache_accept_address) :
|
134 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( icacheread_address) :
|
135 |
|
|
(cond_11 && cond_9 && cond_14 && cond_18)? ( address) :
|
136 |
|
|
32'd0;
|
137 |
|
|
assign data_ram1_data =
|
138 |
|
|
(cond_11 && cond_9 && cond_14 && cond_16)? ( readcode_line) :
|
139 |
|
|
128'd0;
|
140 |
|
|
assign prefetchfifo_write_do =
|
141 |
|
|
(cond_7 && cond_8 && cond_9)? (`TRUE) :
|
142 |
|
|
(cond_11 && cond_9 && cond_12 && cond_13)? (`TRUE) :
|
143 |
|
|
1'd0;
|
144 |
|
|
assign control_ram_write_do =
|
145 |
|
|
(cond_6)? (`TRUE) :
|
146 |
|
|
(cond_7 && cond_8 && cond_9)? (`TRUE) :
|
147 |
|
|
(cond_11 && cond_9 && cond_14)? (`TRUE) :
|
148 |
|
|
1'd0;
|
149 |
|
|
assign control_ram_data =
|
150 |
|
|
(cond_6)? ( control_after_invalidate_write) :
|
151 |
|
|
(cond_7 && cond_8 && cond_9)? ( control_after_match) :
|
152 |
|
|
(cond_11 && cond_9 && cond_14)? ( control_after_line_read) :
|
153 |
|
|
7'd0;
|
154 |
|
|
assign data_ram2_address =
|
155 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( dcachetoicache_accept_address) :
|
156 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( icacheread_address) :
|
157 |
|
|
(cond_11 && cond_9 && cond_14 && cond_17)? ( address) :
|
158 |
|
|
32'd0;
|
159 |
|
|
assign data_ram1_address =
|
160 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( dcachetoicache_accept_address) :
|
161 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( icacheread_address) :
|
162 |
|
|
(cond_11 && cond_9 && cond_14 && cond_16)? ( address) :
|
163 |
|
|
32'd0;
|
164 |
|
|
assign data_ram2_read_do =
|
165 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
166 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? (`TRUE) :
|
167 |
|
|
1'd0;
|
168 |
|
|
assign prefetchfifo_write_data =
|
169 |
|
|
(cond_7 && cond_8 && cond_9)? ( prefetch_line) :
|
170 |
|
|
(cond_11 && cond_9 && cond_12 && cond_13)? ( prefetch_partial) :
|
171 |
|
|
136'd0;
|
172 |
|
|
assign control_ram_address =
|
173 |
|
|
(cond_0 && ~cond_1 && cond_2)? ( dcachetoicache_accept_address) :
|
174 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( icacheread_address) :
|
175 |
|
|
(cond_6)? ( address) :
|
176 |
|
|
(cond_7 && cond_8 && cond_9)? ( address) :
|
177 |
|
|
(cond_11 && cond_9 && cond_14)? ( address) :
|
178 |
|
|
32'd0;
|