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`define CMD_DIV         #AUTOGEN_NEXT_CMD

`define CMD_IDIV        #AUTOGEN_NEXT_CMD

dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd6

`CMD_DIV

IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();

SET(consume_modregrm_one);

dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd7

`CMD_IDIV

IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();

SET(consume_modregrm_one);

IF(rd_cmd == `CMD_IDIV || rd_cmd == `CMD_DIV);

    SET(rd_dst_is_edx_eax);

    SET(rd_req_edx_eax, rd_decoder[0]);

    SET(rd_req_eax);

    // dst: implicit, src: rm

    IF(rd_modregrm_mod == 2'b11);

        SET(rd_src_is_rm);

        IF(rd_mutex_busy_eax || (rd_decoder[0] && rd_mutex_busy_edx) || rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();

    ENDIF();

    // dst: implicit, src: memory

    IF(rd_modregrm_mod != 2'b11);

        IF(rd_mutex_busy_eax || (rd_decoder[0] && rd_mutex_busy_edx) || rd_mutex_busy_memory); SET(rd_waiting);

        ELSE();

            SET(rd_src_is_memory);

            SET(read_virtual);

            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();

        ENDIF();

    ENDIF();

ENDIF();

IF(exe_cmd == `CMD_IDIV || exe_cmd == `CMD_DIV);

    SET(exe_result, (exe_is_8bit)?          { 16'd0, div_result_remainder[7:0], div_result_quotient[7:0] } :

                    (exe_operand_16bit)?    { div_result_remainder[15:0], div_result_quotient[15:0] } :

                                            div_result_quotient);

    SET(exe_result2, div_result_remainder);

    IF(exe_div_exception || div_busy); SET(exe_waiting); ENDIF();

ENDIF();

IF(wr_cmd == `CMD_IDIV || wr_cmd == `CMD_DIV);

    SAVE(eax, (wr_is_8bit || wr_operand_16bit)? { eax[31:16], result[15:0] } : result);

    IF(~(wr_is_8bit));

        SAVE(edx, (wr_operand_16bit)? { edx[31:16], result[31:16] } : result2);

    ENDIF();

ENDIF();