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`define CMD_IMUL        #AUTOGEN_NEXT_CMD

`define CMDEX_IMUL_modregrm     4'd0

`define CMDEX_IMUL_modregrm_imm 4'd1

(dec_ready_modregrm_one && ({ decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd5)) || (dec_ready_2byte_modregrm && decoder[7:0] == 8'hAF)

`CMD_IMUL

SET(dec_cmdex, `CMDEX_IMUL_modregrm);

IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();

SET(consume_modregrm_one);

dec_ready_modregrm_imm && (decoder[7:0] == 8'h69 || decoder[7:0] == 8'h6B)

`CMD_IMUL

SET(dec_cmdex, `CMDEX_IMUL_modregrm_imm);

SET(consume_modregrm_imm);

IF(rd_cmd == `CMD_IMUL && rd_cmdex == `CMDEX_IMUL_modregrm_imm);

    SET(rd_dst_is_reg);

    SET(rd_req_eflags);

    SET(rd_req_reg);

    IF(rd_decoder[1:0] == 2'b11);   SET(rd_dst_is_modregrm_imm_se);

    ELSE();                         SET(rd_dst_is_modregrm_imm);

    ENDIF();

    // dst: reg(only write), src1: rm, src2: imm

    IF(rd_modregrm_mod == 2'b11);

        SET(rd_src_is_rm);

        //no need to wait for dst(modregrm_reg)

        IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();

    ENDIF();

    // dst: reg(only write), src1: memory, src2: imm

    IF(rd_modregrm_mod != 2'b11);

        SET(rd_src_is_memory);

        IF(rd_mutex_busy_memory); SET(rd_waiting);

        ELSE();

            SET(read_virtual);

            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();

        ENDIF();

    ENDIF();

ENDIF();

wire rd_imul_modregrm_mutex_busy;

assign rd_imul_modregrm_mutex_busy =

    (  rd_decoder[3]  && rd_mutex_busy_modregrm_reg) ||

    (~(rd_decoder[3]) && rd_mutex_busy_eax);

IF(rd_cmd == `CMD_IMUL && rd_cmdex == `CMDEX_IMUL_modregrm);

    SET(rd_dst_is_reg,          rd_decoder[3]);

    SET(rd_dst_is_edx_eax,    ~(rd_decoder[3]));

    SET(rd_req_eflags);

    SET(rd_req_reg,          rd_decoder[3]);

    SET(rd_req_edx_eax,      ~(rd_decoder[3]) && rd_decoder[0]);

    SET(rd_req_eax,          ~(rd_decoder[3]));

    // dst: reg/implicit, src: rm

    IF(rd_modregrm_mod == 2'b11);

        SET(rd_src_is_rm);

        IF(rd_imul_modregrm_mutex_busy || rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();

    ENDIF();

    // dst: reg/implicit, src: memory

    IF(rd_modregrm_mod != 2'b11);

        IF(rd_imul_modregrm_mutex_busy || rd_mutex_busy_memory); SET(rd_waiting);

        ELSE();

            SET(rd_src_is_memory);

            SET(read_virtual);

            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();

        ENDIF();

    ENDIF();

ENDIF();

IF(exe_cmd == `CMD_IMUL);

    SET(exe_result,  mult_result[31:0]);

    SET(exe_result2, mult_result[63:32]);

    IF(mult_busy); SET(exe_waiting); ENDIF();

ENDIF();

IF(wr_cmd == `CMD_IMUL);

    SET(write_regrm, wr_dst_is_reg);

    IF(wr_dst_is_edx_eax);

        SAVE(eax, (wr_is_8bit || wr_operand_16bit)? { eax[31:16], result[15:0] } : result);

        IF(~(wr_is_8bit));

            SAVE(edx, (wr_operand_16bit)? { edx[31:16], result[31:16] } : result2);

        ENDIF();

    ENDIF();

    SAVE(zflag, zflag_result);

    SAVE(sflag, sflag_result);

    SAVE(pflag, pflag_result);

    SAVE(aflag, 1'b0);

    SAVE(cflag, wr_mult_overflow);

    SAVE(oflag, wr_mult_overflow);

ENDIF();