OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_INVD.txt] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik
 
2
3
`define CMD_INVD        #AUTOGEN_NEXT_CMD
4
 
5
// check CPL
6
`define CMDEX_INVD_STEP_0     4'd0
7
// do invalidate
8
`define CMDEX_INVD_STEP_1     4'd1
9
// idle
10
`define CMDEX_INVD_STEP_2     4'd2
11
12
 
13
14
dec_ready_2byte_one && decoder[7:0] == 8'h08
15
`CMD_INVD
16
SET(dec_cmdex, `CMDEX_INVD_STEP_0);
17
SET(consume_one);
18
SET(dec_is_complex);
19
20
 
21
22
`CMDEX_INVD_STEP_0
23
`CMDEX_INVD_STEP_1
24
LOOP(`CMDEX_INVD_STEP_2);
25
26
 
27
28
IF(exe_cmd == `CMD_INVD && exe_cmdex == `CMDEX_INVD_STEP_0);
29
    IF(cpl > 2'd0);
30
        SET(exe_waiting);
31
        SET(exe_trigger_gp_fault); //exception GP(0)
32
    ENDIF();
33
ENDIF();
34
35
 
36
37
reg e_invd_code_done;
38
reg e_invd_data_done;
39
 
40
always @(posedge clk or negedge rst_n) begin
41
    if(rst_n == 1'b0)       e_invd_code_done <= `FALSE;
42
    else if(exe_reset)      e_invd_code_done <= `FALSE;
43
    else if(exe_ready)      e_invd_code_done <= `FALSE;
44
    else if(invdcode_done)  e_invd_code_done <= `TRUE;
45
end
46
 
47
always @(posedge clk or negedge rst_n) begin
48
    if(rst_n == 1'b0)       e_invd_data_done <= `FALSE;
49
    else if(exe_reset)      e_invd_data_done <= `FALSE;
50
    else if(exe_ready)      e_invd_data_done <= `FALSE;
51
    else if(invddata_done)  e_invd_data_done <= `TRUE;
52
end
53
54
 
55
56
IF(exe_cmd == `CMD_INVD && exe_cmdex == `CMDEX_INVD_STEP_1);
57
 
58
    SET(invdcode_do, ~(e_invd_code_done));
59
    SET(invddata_do, ~(e_invd_data_done));
60
 
61
    IF(~(e_invd_code_done && e_invd_data_done));
62
        SET(exe_waiting);
63
    ENDIF();
64
ENDIF();
65
66
 
67
68
IF(wr_cmd == `CMD_INVD && wr_cmdex == `CMDEX_INVD_STEP_0);
69
    SET(wr_not_finished);
70
ENDIF();
71
72
 
73
74
IF(wr_cmd == `CMD_INVD && wr_cmdex == `CMDEX_INVD_STEP_1);
75
 
76
    // reset part of pipeline
77
    SET(wr_req_reset_micro);
78
    SET(wr_req_reset_rd);
79
    SET(wr_req_reset_exe);
80
ENDIF();
81

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.