1 |
2 |
alfik |
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3 |
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`define CMD_IRET #AUTOGEN_NEXT_CMD
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4 |
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// mc_param_1 --> cs
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5 |
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// mc_param_2 --> eip
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6 |
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// mc_param_3 --> eflags
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7 |
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8 |
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`define CMDEX_IRET_real_v86_STEP_0 4'd0
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`define CMDEX_IRET_real_v86_STEP_1 4'd1
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`define CMDEX_IRET_real_v86_STEP_2 4'd2
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`define CMDEX_IRET_real_v86_STEP_3 4'd3
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`define CMDEX_IRET_protected_STEP_0 4'd4
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14 |
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`define CMDEX_IRET_task_switch_STEP_0 4'd5
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`define CMDEX_IRET_task_switch_STEP_1 4'd6
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`define CMDEX_IRET_protected_STEP_1 4'd7
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`define CMDEX_IRET_protected_STEP_2 4'd8
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`define CMDEX_IRET_protected_STEP_3 4'd9
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`define CMDEX_IRET_protected_to_v86_STEP_0 4'd10
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`define CMDEX_IRET_protected_to_v86_STEP_1 4'd11
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`define CMDEX_IRET_protected_to_v86_STEP_2 4'd12
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`define CMDEX_IRET_protected_to_v86_STEP_3 4'd13
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`define CMDEX_IRET_protected_to_v86_STEP_4 4'd14
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`define CMDEX_IRET_protected_to_v86_STEP_5 4'd15
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//------------------------------------------------------------------------------
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`define CMD_IRET_2 #AUTOGEN_NEXT_CMD
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`define CMDEX_IRET_2_idle 4'd0
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`define CMDEX_IRET_2_protected_same_STEP_0 4'd1
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`define CMDEX_IRET_2_protected_same_STEP_1 4'd2
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36 |
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`define CMDEX_IRET_2_protected_outer_STEP_0 4'd3
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// glob_param_1 --> ss
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// glob_param_2 --> eip
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// glob_descriptor --> ss desc
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// glob_param_3 --> saved cs
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// glob_descriptor_2 --> saved cs desc
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`define CMDEX_IRET_2_protected_outer_STEP_1 4'd4
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`define CMDEX_IRET_2_protected_outer_STEP_2 4'd5
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`define CMDEX_IRET_2_protected_outer_STEP_3 4'd6
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// glob_param_2 --> eip
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// glob_param_4 --> esp
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// glob_param_5 --> eflags
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// after step 3/exe:
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// glob_param_1 --> cs
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// glob_descriptor --> cs desc
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// glob_param_3 --> ss
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// glob_descriptor_2 --> ss desc
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// glob_param_2 --> eip
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// glob_param_4 --> esp
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// glob_param_5 --> eflags
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`define CMDEX_IRET_2_protected_outer_STEP_4 4'd7
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`define CMDEX_IRET_2_protected_outer_STEP_5 4'd8
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// after step 5/exe:
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// glob_param_1 --> ss
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// glob_descriptor --> ss desc
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// glob_param_3 --> cs
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// glob_descriptor_2 --> cs desc
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// glob_param_2 --> eip
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// glob_param_4 --> esp
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// glob_param_5 --> eflags
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`define CMDEX_IRET_2_protected_outer_STEP_6 4'd9
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`define CMDEX_IRET_2_protected_to_v86_STEP_6 4'd10
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dec_ready_one && decoder[7:0] == 8'hCF
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`CMD_IRET
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IF(~(protected_mode)); SET(dec_cmdex, `CMDEX_IRET_real_v86_STEP_0); ELSE(); SET(dec_cmdex, `CMDEX_IRET_protected_STEP_0); ENDIF();
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SET(consume_one);
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SET(dec_is_complex);
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IF(`CMDEX_IRET_real_v86_STEP_0);
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`CMDEX_IRET_real_v86_STEP_1
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`CMDEX_IRET_real_v86_STEP_2
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CALL(`CMDEX_load_seg_STEP_1);
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LOOP(`CMDEX_IRET_real_v86_STEP_3);
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ENDIF();
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IF(`CMDEX_IRET_protected_STEP_0 && ntflag);
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`CMDEX_IRET_task_switch_STEP_0
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`CMDEX_IRET_task_switch_STEP_1
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JMP(`CMDEX_task_switch_STEP_1);
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ENDIF();
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IF(`CMDEX_IRET_protected_STEP_0 && ~(ntflag));
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`CMDEX_IRET_protected_STEP_1
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`CMDEX_IRET_protected_STEP_2
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`CMDEX_IRET_protected_STEP_3
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101 |
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//iret to v86
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IF(`CMDEX_IRET_protected_STEP_3 && mc_operand_32bit && glob_param_3[`EFLAGS_BIT_VM] && cpl == 2'd0);
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`CMDEX_IRET_protected_to_v86_STEP_0
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IF(mc_cmd == `CMD_IRET && mc_cmdex_last >= `CMDEX_IRET_protected_to_v86_STEP_0 && mc_cmdex_last < `CMDEX_IRET_protected_to_v86_STEP_5);
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DIRECT(`CMD_IRET, mc_cmdex_last + 4'd1);
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ENDIF();
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IF(`CMDEX_IRET_protected_to_v86_STEP_5);
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`CMDEX_IRET_2_protected_to_v86_STEP_6
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LOOP(`CMDEX_IRET_2_idle);
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ENDIF();
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ENDIF();
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//iret same or outer
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IF(`CMDEX_IRET_protected_STEP_3 && ~(mc_operand_32bit && glob_param_3[`EFLAGS_BIT_VM] && cpl == 2'd0));
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CALL(`CMDEX_load_seg_STEP_1);
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DIRECT(`CMD_IRET_2, (glob_param_1[`SELECTOR_BITS_RPL] == cpl)? `CMDEX_IRET_2_protected_same_STEP_0 : `CMDEX_IRET_2_protected_outer_STEP_0);
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ENDIF();
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IF(`CMDEX_IRET_2_protected_same_STEP_0);
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`CMDEX_IRET_2_protected_same_STEP_1
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LOOP(`CMDEX_IRET_2_idle);
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ENDIF();
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IF(`CMDEX_IRET_2_protected_outer_STEP_0);
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CALL(`CMDEX_load_seg_STEP_1);
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`CMDEX_IRET_2_protected_outer_STEP_1
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IF(mc_cmd == `CMD_IRET_2 && mc_cmdex_last >= `CMDEX_IRET_2_protected_outer_STEP_1 && mc_cmdex_last < `CMDEX_IRET_2_protected_outer_STEP_6);
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DIRECT(`CMD_IRET_2, mc_cmdex_last + 4'd1);
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ENDIF();
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IF(`CMDEX_IRET_2_protected_outer_STEP_6);
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LOOP(`CMDEX_IRET_2_idle);
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ENDIF();
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ENDIF();
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ENDIF();
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IF(rd_cmd == `CMD_IRET && rd_cmdex <= `CMDEX_IRET_real_v86_STEP_2);
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SET(address_stack_pop);
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IF(rd_cmdex >`CMDEX_IRET_real_v86_STEP_0); SET(address_stack_pop_speedup); ENDIF();
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IF(rd_cmdex == `CMDEX_IRET_real_v86_STEP_0);
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SET(rd_glob_param_2_set);
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SET(rd_glob_param_2_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read eip
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ENDIF();
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IF(rd_cmdex == `CMDEX_IRET_real_v86_STEP_1);
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SET(rd_glob_param_1_set);
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SET(rd_glob_param_1_value, { 13'd0, `SEGMENT_CS, read_4[15:0] }); // read cs
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ENDIF();
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IF(rd_cmdex == `CMDEX_IRET_real_v86_STEP_2);
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SET(rd_glob_param_3_set);
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SET(rd_glob_param_3_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read eflags
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ENDIF();
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IF(rd_mutex_busy_memory || (rd_mutex_busy_eflags && v8086_mode)); SET(rd_waiting); // waiting for esp in 'address_waiting'
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ELSE();
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IF(~(v8086_mode) || iopl == 2'd3);
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SET(read_virtual);
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IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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ENDIF();
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ENDIF();
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ENDIF();
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IF(rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_protected_STEP_0);
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IF(rd_mutex_busy_memory || rd_mutex_busy_eflags); SET(rd_waiting); ENDIF(); // waiting for esp in 'address_waiting'
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ENDIF();
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180 |
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181 |
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IF(rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_task_switch_STEP_0);
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SET(rd_system_linear, tr_base);
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186 |
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SET(read_system_word);
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188 |
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SET(rd_glob_param_1_set);
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SET(rd_glob_param_1_value, { 14'd0, `TASK_SWITCH_FROM_IRET, read_4[15:0] });
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IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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ENDIF();
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194 |
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195 |
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IF(rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_task_switch_STEP_1);
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198 |
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SET(rd_glob_param_3_set);
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SET(rd_glob_param_3_value, { 10'd0, rd_consumed, 18'd0 });
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201 |
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IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- exception possible
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ELSE();
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IF(~(rd_descriptor_not_in_limits));
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206 |
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SET(rd_glob_descriptor_set);
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SET(rd_glob_descriptor_value, read_8);
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209 |
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SET(rd_glob_param_2_set);
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SET(rd_glob_param_2_value, 32'd0);
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212 |
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SET(read_system_descriptor);
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IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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216 |
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ELSE();
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SET(rd_glob_param_2_set);
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218 |
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SET(rd_glob_param_2_value, { 30'd0, rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 });
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ENDIF();
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ENDIF();
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ENDIF();
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223 |
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224 |
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225 |
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IF(rd_cmd == `CMD_IRET && rd_cmdex >= `CMDEX_IRET_protected_STEP_1 && rd_cmdex <= `CMDEX_IRET_protected_STEP_3);
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227 |
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SET(address_stack_pop_next);
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IF(rd_cmdex == `CMDEX_IRET_protected_STEP_1);
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SET(address_stack_save);
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SET(address_stack_for_iret_first);
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233 |
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SET(rd_glob_param_3_set);
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SET(rd_glob_param_3_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); //eflags
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ENDIF();
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IF(rd_cmdex == `CMDEX_IRET_protected_STEP_2);
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SET(rd_glob_param_1_set);
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SET(rd_glob_param_1_value, { `MC_PARAM_1_FLAG_NO_WRITE, `SEGMENT_CS, read_4[15:0] }); //cs
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ENDIF();
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IF(rd_cmdex == `CMDEX_IRET_protected_STEP_3);
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SET(rd_glob_param_2_set);
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SET(rd_glob_param_2_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); //eip
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ENDIF();
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247 |
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SET(read_virtual);
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IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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ENDIF();
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253 |
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254 |
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255 |
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IF(rd_cmd == `CMD_IRET && rd_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0);
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256 |
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SET(address_stack_pop_next);
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SET(address_stack_add_4_to_saved);
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259 |
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IF(rd_cmdex == `CMDEX_IRET_protected_to_v86_STEP_0);
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260 |
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SET(address_stack_save);
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261 |
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SET(address_stack_for_iret_to_v86);
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262 |
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ENDIF();
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263 |
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264 |
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SET(rd_src_is_memory);
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266 |
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SET(read_virtual);
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267 |
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268 |
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IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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ENDIF();
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270 |
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271 |
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272 |
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273 |
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IF(rd_cmd == `CMD_IRET_2 && rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_0);
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274 |
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275 |
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SET(address_stack_pop_next);
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276 |
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SET(address_stack_for_iret_second);
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277 |
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278 |
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SET(rd_glob_param_1_set, rd_ready);
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279 |
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SET(rd_glob_param_1_value, { `MC_PARAM_1_FLAG_NP_NOT_SS | `MC_PARAM_1_FLAG_CPL_FROM_PARAM_3, `SEGMENT_SS, read_4[15:0] }); // read ss
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280 |
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281 |
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SET(rd_glob_param_3_set);
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282 |
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SET(rd_glob_param_3_value, glob_param_1);
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283 |
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284 |
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SET(rd_glob_descriptor_2_set);
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285 |
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SET(rd_glob_descriptor_2_value, glob_descriptor);
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286 |
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287 |
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SET(read_length_word);
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288 |
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SET(read_virtual);
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289 |
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290 |
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IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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291 |
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ENDIF();
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292 |
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293 |
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294 |
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295 |
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IF(rd_cmd == `CMD_IRET_2 && rd_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_1 && rd_cmdex <= `CMDEX_IRET_2_protected_outer_STEP_3);
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296 |
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297 |
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SET(address_stack_pop_next);
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298 |
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299 |
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IF(rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_1);
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300 |
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SET(address_stack_save);
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301 |
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SET(address_stack_for_iret_third);
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302 |
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303 |
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SET(rd_glob_param_4_set);
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304 |
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SET(rd_glob_param_4_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read esp
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305 |
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ENDIF();
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306 |
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307 |
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IF(rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_2);
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308 |
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SET(rd_glob_param_5_set);
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309 |
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SET(rd_glob_param_5_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read eflags
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310 |
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ENDIF();
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311 |
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312 |
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IF(rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_3);
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313 |
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SET(address_stack_for_iret_last);
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314 |
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315 |
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SET(rd_glob_param_2_set);
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316 |
|
|
SET(rd_glob_param_2_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read eip
|
317 |
|
|
ENDIF();
|
318 |
|
|
|
319 |
|
|
SET(read_virtual);
|
320 |
|
|
|
321 |
|
|
IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
|
322 |
|
|
ENDIF();
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
IF(rd_cmd == `CMD_IRET_2 && rd_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_6);
|
327 |
|
|
IF(rd_mutex_busy_active); SET(rd_waiting); ENDIF(); // wait for previous step -- loading ss
|
328 |
|
|
ENDIF();
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_same_STEP_0);
|
333 |
|
|
|
334 |
|
|
SET(offset_iret);
|
335 |
|
|
|
336 |
|
|
IF(glob_param_2 > glob_desc_limit);
|
337 |
|
|
SET(exe_waiting);
|
338 |
|
|
SET(exe_trigger_gp_fault); //exception GP(0)
|
339 |
|
|
ENDIF();
|
340 |
|
|
|
341 |
|
|
ENDIF();
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_same_STEP_1);
|
346 |
|
|
SET(exe_eip_from_glob_param_2);
|
347 |
|
|
ENDIF();
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_3);
|
352 |
|
|
|
353 |
|
|
IF(glob_param_2 > glob_desc_2_limit);
|
354 |
|
|
|
355 |
|
|
SET(exe_waiting);
|
356 |
|
|
SET(exe_trigger_gp_fault); //exception GP(0)
|
357 |
|
|
ELSE();
|
358 |
|
|
SET(exe_glob_descriptor_set);
|
359 |
|
|
SET(exe_glob_descriptor_value, glob_descriptor_2);
|
360 |
|
|
|
361 |
|
|
SET(exe_glob_descriptor_2_set);
|
362 |
|
|
SET(exe_glob_descriptor_2_value, glob_descriptor);
|
363 |
|
|
|
364 |
|
|
SET(exe_glob_param_1_set);
|
365 |
|
|
SET(exe_glob_param_1_value, glob_param_3);
|
366 |
|
|
|
367 |
|
|
SET(exe_glob_param_3_set);
|
368 |
|
|
SET(exe_glob_param_3_value, glob_param_1);
|
369 |
|
|
ENDIF();
|
370 |
|
|
ENDIF();
|
371 |
|
|
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_5);
|
375 |
|
|
|
376 |
|
|
SET(exe_glob_descriptor_set);
|
377 |
|
|
SET(exe_glob_descriptor_value, glob_descriptor_2);
|
378 |
|
|
|
379 |
|
|
SET(exe_glob_descriptor_2_set);
|
380 |
|
|
SET(exe_glob_descriptor_2_value, glob_descriptor);
|
381 |
|
|
|
382 |
|
|
SET(exe_glob_param_1_set);
|
383 |
|
|
SET(exe_glob_param_1_value, glob_param_3);
|
384 |
|
|
|
385 |
|
|
SET(exe_glob_param_3_set);
|
386 |
|
|
SET(exe_glob_param_3_value, glob_param_1);
|
387 |
|
|
ENDIF();
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_6);
|
392 |
|
|
|
393 |
|
|
SET(offset_iret_glob_param_4);
|
394 |
|
|
SET(exe_eip_from_glob_param_2);
|
395 |
|
|
ENDIF();
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_0);
|
400 |
|
|
|
401 |
|
|
SET(offset_pop);
|
402 |
|
|
|
403 |
|
|
IF(v8086_mode && iopl < 2'd3);
|
404 |
|
|
SET(exe_waiting);
|
405 |
|
|
SET(exe_trigger_gp_fault); //exception GP(0)
|
406 |
|
|
ENDIF();
|
407 |
|
|
ENDIF();
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_1);
|
412 |
|
|
SET(offset_pop);
|
413 |
|
|
ENDIF();
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_2);
|
418 |
|
|
|
419 |
|
|
SET(offset_pop);
|
420 |
|
|
|
421 |
|
|
IF(~(v8086_mode) && glob_param_2 > cs_limit);
|
422 |
|
|
SET(exe_waiting);
|
423 |
|
|
SET(exe_trigger_gp_fault); //exception GP(0)
|
424 |
|
|
ENDIF();
|
425 |
|
|
ENDIF();
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
|
429 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_3);
|
430 |
|
|
SET(exe_eip_from_glob_param_2);
|
431 |
|
|
ENDIF();
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_task_switch_STEP_0);
|
436 |
|
|
IF(glob_param_1[`SELECTOR_BIT_TI]);
|
437 |
|
|
SET(exe_waiting);
|
438 |
|
|
|
439 |
|
|
SET(exe_trigger_ts_fault);
|
440 |
|
|
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
|
441 |
|
|
ENDIF();
|
442 |
|
|
ENDIF();
|
443 |
|
|
|
444 |
|
|
|
445 |
|
|
|
446 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_task_switch_STEP_1);
|
447 |
|
|
|
448 |
|
|
IF(glob_param_2[1] || exe_descriptor[`DESC_BIT_SEG] || (exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_286));
|
449 |
|
|
SET(exe_waiting);
|
450 |
|
|
|
451 |
|
|
SET(exe_trigger_ts_fault);
|
452 |
|
|
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
|
453 |
|
|
ENDIF();
|
454 |
|
|
|
455 |
|
|
IF(glob_param_2[1] == 1'b0 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]));
|
456 |
|
|
SET(exe_waiting);
|
457 |
|
|
|
458 |
|
|
SET(exe_trigger_np_fault);
|
459 |
|
|
SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
|
460 |
|
|
ENDIF();
|
461 |
|
|
ENDIF();
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
IF(exe_cmd == `CMD_IRET && exe_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0);
|
466 |
|
|
IF(exe_ready);
|
467 |
|
|
SAVE(exe_buffer, src);
|
468 |
|
|
SET(exe_buffer_shift);
|
469 |
|
|
ENDIF();
|
470 |
|
|
ENDIF();
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_to_v86_STEP_6);
|
475 |
|
|
SET(exe_eip_from_glob_param_2_16bit);
|
476 |
|
|
ENDIF();
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
// special case: check if (cs.rpl != ss.rpl) before LOAD_SEG
|
481 |
|
|
IF(exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_0);
|
482 |
|
|
|
483 |
|
|
IF(glob_param_1[`SELECTOR_BITS_RPL] != glob_param_3[`SELECTOR_BITS_RPL]); // new_ss.rpl != new_cs.rpl
|
484 |
|
|
|
485 |
|
|
SET(exe_waiting);
|
486 |
|
|
SET(exe_trigger_gp_fault); //exception GP(val)
|
487 |
|
|
SET(exe_error_code, { glob_param_1[15:2], 2'd0 });
|
488 |
|
|
ENDIF();
|
489 |
|
|
ENDIF();
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
IF(wr_cmd == `CMD_IRET && wr_cmdex <= `CMDEX_IRET_real_v86_STEP_2);
|
494 |
|
|
SET(wr_not_finished);
|
495 |
|
|
|
496 |
|
|
SAVE(esp, wr_stack_esp);
|
497 |
|
|
IF(wr_cmdex == `CMDEX_IRET_real_v86_STEP_0); SET(wr_make_esp_speculative); ENDIF(); //NOTE: esp update can not be every cycle; must be at least every second cycle
|
498 |
|
|
ENDIF();
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
|
502 |
|
|
IF(wr_cmd == `CMD_IRET && wr_cmdex == `CMDEX_IRET_real_v86_STEP_3);
|
503 |
|
|
|
504 |
|
|
SET(wr_make_esp_commit);
|
505 |
|
|
|
506 |
|
|
SAVE(cflag, glob_param_3[0]);
|
507 |
|
|
SAVE(pflag, glob_param_3[2]);
|
508 |
|
|
SAVE(aflag, glob_param_3[4]);
|
509 |
|
|
SAVE(zflag, glob_param_3[6]);
|
510 |
|
|
SAVE(sflag, glob_param_3[7]);
|
511 |
|
|
SAVE(tflag, glob_param_3[8]);
|
512 |
|
|
SAVE(iflag, glob_param_3[9]);
|
513 |
|
|
SAVE(dflag, glob_param_3[10]);
|
514 |
|
|
SAVE(oflag, glob_param_3[11]);
|
515 |
|
|
SAVE(ntflag, glob_param_3[14]);
|
516 |
|
|
|
517 |
|
|
IF(real_mode);
|
518 |
|
|
SAVE(iopl, glob_param_3[13:12]);
|
519 |
|
|
ENDIF();
|
520 |
|
|
|
521 |
|
|
IF(wr_operand_32bit);
|
522 |
|
|
SAVE(rflag, glob_param_3[16]);
|
523 |
|
|
SAVE(acflag, glob_param_3[18]);
|
524 |
|
|
SAVE(idflag, glob_param_3[21]);
|
525 |
|
|
ENDIF();
|
526 |
|
|
|
527 |
|
|
// clear pipeline
|
528 |
|
|
SET(wr_req_reset_pr);
|
529 |
|
|
SET(wr_req_reset_dec);
|
530 |
|
|
SET(wr_req_reset_micro);
|
531 |
|
|
SET(wr_req_reset_rd);
|
532 |
|
|
SET(wr_req_reset_exe);
|
533 |
|
|
ENDIF();
|
534 |
|
|
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
IF(wr_cmd == `CMD_IRET && (wr_cmdex == `CMDEX_IRET_protected_STEP_0 || wr_cmdex == `CMDEX_IRET_task_switch_STEP_0 || wr_cmdex == `CMDEX_IRET_task_switch_STEP_1));
|
538 |
|
|
SET(wr_not_finished);
|
539 |
|
|
ENDIF();
|
540 |
|
|
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
IF(wr_cmd == `CMD_IRET && wr_cmdex >= `CMDEX_IRET_protected_STEP_1 && wr_cmdex <= `CMDEX_IRET_protected_STEP_3);
|
544 |
|
|
SET(wr_not_finished);
|
545 |
|
|
ENDIF();
|
546 |
|
|
|
547 |
|
|
|
548 |
|
|
|
549 |
|
|
IF(wr_cmd == `CMD_IRET && wr_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0 && wr_cmdex <= `CMDEX_IRET_protected_to_v86_STEP_4);
|
550 |
|
|
SET(wr_not_finished);
|
551 |
|
|
ENDIF();
|
552 |
|
|
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
wire [15:0] wr_IRET_to_v86_es;
|
556 |
|
|
wire [15:0] wr_IRET_to_v86_cs;
|
557 |
|
|
wire [15:0] wr_IRET_to_v86_ss;
|
558 |
|
|
wire [15:0] wr_IRET_to_v86_ds;
|
559 |
|
|
wire [15:0] wr_IRET_to_v86_fs;
|
560 |
|
|
wire [15:0] wr_IRET_to_v86_gs;
|
561 |
|
|
|
562 |
|
|
assign wr_IRET_to_v86_es = exe_buffer_shifted[79:64];
|
563 |
|
|
assign wr_IRET_to_v86_cs = glob_param_1[15:0];
|
564 |
|
|
assign wr_IRET_to_v86_ss = exe_buffer_shifted[111:96];
|
565 |
|
|
assign wr_IRET_to_v86_ds = exe_buffer_shifted[47:32];
|
566 |
|
|
assign wr_IRET_to_v86_fs = exe_buffer_shifted[15:0];
|
567 |
|
|
assign wr_IRET_to_v86_gs = exe_buffer[15:0];
|
568 |
|
|
|
569 |
|
|
|
570 |
|
|
|
571 |
|
|
IF(wr_cmd == `CMD_IRET && wr_cmdex == `CMDEX_IRET_protected_to_v86_STEP_5);
|
572 |
|
|
|
573 |
|
|
SET(wr_not_finished);
|
574 |
|
|
|
575 |
|
|
SAVE(cflag, glob_param_3[0]);
|
576 |
|
|
SAVE(pflag, glob_param_3[2]);
|
577 |
|
|
SAVE(aflag, glob_param_3[4]);
|
578 |
|
|
SAVE(zflag, glob_param_3[6]);
|
579 |
|
|
SAVE(sflag, glob_param_3[7]);
|
580 |
|
|
SAVE(tflag, glob_param_3[8]);
|
581 |
|
|
SAVE(iflag, glob_param_3[9]);
|
582 |
|
|
SAVE(dflag, glob_param_3[10]);
|
583 |
|
|
SAVE(oflag, glob_param_3[11]);
|
584 |
|
|
SAVE(iopl, glob_param_3[13:12]);
|
585 |
|
|
SAVE(ntflag, glob_param_3[14]);
|
586 |
|
|
SAVE(rflag, glob_param_3[16]);
|
587 |
|
|
SAVE(vmflag, glob_param_3[`EFLAGS_BIT_VM]);
|
588 |
|
|
SAVE(acflag, glob_param_3[18]);
|
589 |
|
|
SAVE(idflag, glob_param_3[21]);
|
590 |
|
|
|
591 |
|
|
SAVE(esp, exe_buffer_shifted[159:128]);
|
592 |
|
|
|
593 |
|
|
//seg
|
594 |
|
|
SAVE(es, wr_IRET_to_v86_es);
|
595 |
|
|
SAVE(cs, wr_IRET_to_v86_cs);
|
596 |
|
|
SAVE(ss, wr_IRET_to_v86_ss);
|
597 |
|
|
SAVE(ds, wr_IRET_to_v86_ds);
|
598 |
|
|
SAVE(fs, wr_IRET_to_v86_fs);
|
599 |
|
|
SAVE(gs, wr_IRET_to_v86_gs);
|
600 |
|
|
|
601 |
|
|
SAVE(es_rpl, 2'd3);
|
602 |
|
|
SAVE(cs_rpl, 2'd3);
|
603 |
|
|
SAVE(ss_rpl, 2'd3);
|
604 |
|
|
SAVE(ds_rpl, 2'd3);
|
605 |
|
|
SAVE(fs_rpl, 2'd3);
|
606 |
|
|
SAVE(gs_rpl, 2'd3);
|
607 |
|
|
|
608 |
|
|
SAVE(es_cache_valid, `TRUE);
|
609 |
|
|
SAVE(cs_cache_valid, `TRUE);
|
610 |
|
|
SAVE(ss_cache_valid, `TRUE);
|
611 |
|
|
SAVE(ds_cache_valid, `TRUE);
|
612 |
|
|
SAVE(fs_cache_valid, `TRUE);
|
613 |
|
|
SAVE(gs_cache_valid, `TRUE);
|
614 |
|
|
|
615 |
|
|
SAVE(es_cache, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_es[15:12], wr_IRET_to_v86_es[11:0],4'd0, 16'hFFFF });
|
616 |
|
|
SAVE(cs_cache, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_cs[15:12], wr_IRET_to_v86_cs[11:0],4'd0, 16'hFFFF });
|
617 |
|
|
SAVE(ss_cache, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_ss[15:12], wr_IRET_to_v86_ss[11:0],4'd0, 16'hFFFF });
|
618 |
|
|
SAVE(ds_cache, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_ds[15:12], wr_IRET_to_v86_ds[11:0],4'd0, 16'hFFFF });
|
619 |
|
|
SAVE(fs_cache, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_fs[15:12], wr_IRET_to_v86_fs[11:0],4'd0, 16'hFFFF });
|
620 |
|
|
SAVE(gs_cache, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_gs[15:12], wr_IRET_to_v86_gs[11:0],4'd0, 16'hFFFF });
|
621 |
|
|
ENDIF();
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
|
625 |
|
|
IF(wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_to_v86_STEP_6);
|
626 |
|
|
|
627 |
|
|
// clear pipeline
|
628 |
|
|
SET(wr_req_reset_pr);
|
629 |
|
|
SET(wr_req_reset_dec);
|
630 |
|
|
SET(wr_req_reset_micro);
|
631 |
|
|
SET(wr_req_reset_rd);
|
632 |
|
|
SET(wr_req_reset_exe);
|
633 |
|
|
ENDIF();
|
634 |
|
|
|
635 |
|
|
|
636 |
|
|
|
637 |
|
|
IF(wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_same_STEP_1);
|
638 |
|
|
|
639 |
|
|
// save eflags
|
640 |
|
|
SAVE(cflag, glob_param_3[0]);
|
641 |
|
|
SAVE(pflag, glob_param_3[2]);
|
642 |
|
|
SAVE(aflag, glob_param_3[4]);
|
643 |
|
|
SAVE(zflag, glob_param_3[6]);
|
644 |
|
|
SAVE(sflag, glob_param_3[7]);
|
645 |
|
|
SAVE(tflag, glob_param_3[8]);
|
646 |
|
|
SAVE(dflag, glob_param_3[10]);
|
647 |
|
|
SAVE(oflag, glob_param_3[11]);
|
648 |
|
|
SAVE(ntflag, glob_param_3[14]);
|
649 |
|
|
|
650 |
|
|
IF(cpl <= iopl);
|
651 |
|
|
SAVE(iflag, glob_param_3[9]);
|
652 |
|
|
ENDIF();
|
653 |
|
|
|
654 |
|
|
IF(cpl == 2'd0);
|
655 |
|
|
SAVE(iopl, glob_param_3[13:12]);
|
656 |
|
|
ENDIF();
|
657 |
|
|
|
658 |
|
|
IF(wr_operand_32bit);
|
659 |
|
|
SAVE(rflag, glob_param_3[16]);
|
660 |
|
|
SAVE(acflag, glob_param_3[18]);
|
661 |
|
|
SAVE(idflag, glob_param_3[21]);
|
662 |
|
|
ENDIF();
|
663 |
|
|
|
664 |
|
|
// clear pipeline
|
665 |
|
|
SET(wr_req_reset_pr);
|
666 |
|
|
SET(wr_req_reset_dec);
|
667 |
|
|
SET(wr_req_reset_micro);
|
668 |
|
|
SET(wr_req_reset_rd);
|
669 |
|
|
SET(wr_req_reset_exe);
|
670 |
|
|
ENDIF();
|
671 |
|
|
|
672 |
|
|
|
673 |
|
|
|
674 |
|
|
IF(wr_cmd == `CMD_IRET_2 && wr_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_0 && wr_cmdex <= `CMDEX_IRET_2_protected_outer_STEP_2);
|
675 |
|
|
SET(wr_not_finished);
|
676 |
|
|
ENDIF();
|
677 |
|
|
|
678 |
|
|
|
679 |
|
|
|
680 |
|
|
IF(wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_outer_STEP_4);
|
681 |
|
|
SET(wr_not_finished);
|
682 |
|
|
|
683 |
|
|
// save eflags
|
684 |
|
|
|
685 |
|
|
SAVE(cflag, glob_param_5[0]);
|
686 |
|
|
SAVE(pflag, glob_param_5[2]);
|
687 |
|
|
SAVE(aflag, glob_param_5[4]);
|
688 |
|
|
SAVE(zflag, glob_param_5[6]);
|
689 |
|
|
SAVE(sflag, glob_param_5[7]);
|
690 |
|
|
SAVE(tflag, glob_param_5[8]);
|
691 |
|
|
SAVE(dflag, glob_param_5[10]);
|
692 |
|
|
SAVE(oflag, glob_param_5[11]);
|
693 |
|
|
SAVE(ntflag, glob_param_5[14]);
|
694 |
|
|
|
695 |
|
|
IF(wr_task_rpl <= iopl);
|
696 |
|
|
SAVE(iflag, glob_param_5[9]);
|
697 |
|
|
ENDIF();
|
698 |
|
|
|
699 |
|
|
IF(wr_task_rpl == 2'd0);
|
700 |
|
|
SAVE(iopl, glob_param_5[13:12]);
|
701 |
|
|
ENDIF();
|
702 |
|
|
|
703 |
|
|
IF(wr_operand_32bit);
|
704 |
|
|
SAVE(rflag, glob_param_5[16]);
|
705 |
|
|
SAVE(acflag, glob_param_5[18]);
|
706 |
|
|
SAVE(idflag, glob_param_5[21]);
|
707 |
|
|
ENDIF();
|
708 |
|
|
ENDIF();
|
709 |
|
|
|