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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_SHxD.txt] - Blame information for rev 2

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`define CMD_SHxD        #AUTOGEN_NEXT_CMD_MOD2
`define CMD_SHLD        #AUTOGEN_NEXT_CMD_LIKE_PREV
`define CMD_SHRD        #AUTOGEN_NEXT_CMD
 
`define CMDEX_SHxD_implicit     4'd0
`define CMDEX_SHxD_modregrm_imm 4'd1

 

(dec_ready_2byte_modregrm && decoder[7:0] == 8'hA5) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hA4)
`CMD_SHLD
IF(decoder[0]); SET(dec_cmdex, `CMDEX_SHxD_implicit); ELSE(); SET(dec_cmdex, `CMDEX_SHxD_modregrm_imm); ENDIF();
IF(decoder[0] == 1'b0); SET(consume_modregrm_imm); ELSE(); SET(consume_modregrm_one); ENDIF();

 

(dec_ready_2byte_modregrm && decoder[7:0] == 8'hAD) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hAC)
`CMD_SHRD
IF(decoder[0]); SET(dec_cmdex, `CMDEX_SHxD_implicit); ELSE(); SET(dec_cmdex, `CMDEX_SHxD_modregrm_imm); ENDIF();
IF(decoder[0] == 1'b0); SET(consume_modregrm_imm); ELSE(); SET(consume_modregrm_one); ENDIF();

 

IF({ rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex != `CMDEX_SHxD_implicit);
 
    SET(rd_src_is_reg);
 
    SET(rd_req_eflags);
 
    // dst: reg, src: imm
    IF(rd_modregrm_mod == 2'b11);
 
        SET(rd_dst_is_rm);
 
        SET(rd_req_rm);
 
        IF(rd_mutex_busy_modregrm_rm || rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
    ENDIF();
 
    // dst: memory, src: imm or 1
    IF(rd_modregrm_mod != 2'b11);
 
        SET(rd_dst_is_memory);
 
        SET(rd_req_memory);
 
        IF(rd_mutex_busy_memory || rd_mutex_busy_modregrm_reg); SET(rd_waiting);
        ELSE();
            SET(read_rmw_virtual);
 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF({ rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex == `CMDEX_SHxD_implicit);
 
    SET(rd_src_is_reg);
 
    SET(rd_req_eflags);
 
    // dst: reg, src: CL
    IF(rd_modregrm_mod == 2'b11);
 
        SET(rd_dst_is_rm);
 
        SET(rd_req_rm);
 
        IF(rd_mutex_busy_modregrm_rm || rd_mutex_busy_ecx || rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
    ENDIF();
 
    // dst: memory, src: imm or 1
    IF(rd_modregrm_mod != 2'b11);
 
        SET(rd_dst_is_memory);
 
        SET(rd_req_memory);
 
        IF(rd_mutex_busy_memory || rd_mutex_busy_ecx || rd_mutex_busy_modregrm_reg); SET(rd_waiting);
        ELSE();
            SET(read_rmw_virtual);
 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF({ exe_cmd[6:1], 1'd0 } == `CMD_SHxD);
 
    SET(exe_result, e_shift_result);
    SET(exe_result_signals, { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag });
 
ENDIF();

 

IF({ wr_cmd[6:1], 1'd0 } == `CMD_SHxD);
 
    // result_signals
    // { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag }
 
    IF(~(result_signals[4])); //e_shift_no_write
        IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
 
        SET(write_regrm,         wr_dst_is_rm);
        SET(write_rmw_virtual,   wr_dst_is_memory);
    ENDIF();
 
    IF(result_signals[3]); //e_shift_oszapc_update
        SAVE(zflag, zflag_result);
        SAVE(sflag, sflag_result);
        SAVE(pflag, pflag_result);
        SAVE(aflag, aflag_arith);
    ENDIF();
 
    IF(result_signals[2]); //e_shift_cf_of_update
        SAVE(cflag, result_signals[0]);
        SAVE(oflag, result_signals[1]);
    ENDIF();
ENDIF();


Line No.	Rev	Author	Line
1	2	alfik
2
3			`define CMD_SHxD #AUTOGEN_NEXT_CMD_MOD2
4			`define CMD_SHLD #AUTOGEN_NEXT_CMD_LIKE_PREV
5			`define CMD_SHRD #AUTOGEN_NEXT_CMD
6
7			`define CMDEX_SHxD_implicit 4'd0
8			`define CMDEX_SHxD_modregrm_imm 4'd1
9
10
11
12			`(dec_ready_2byte_modregrm && decoder[7:0] == 8'hA5) \|\| (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hA4)`
13			`CMD_SHLD
14			IF(decoder[0]); SET(dec_cmdex, `CMDEX_SHxD_implicit); ELSE(); SET(dec_cmdex, `CMDEX_SHxD_modregrm_imm); ENDIF();
15			`IF(decoder[0] == 1'b0); SET(consume_modregrm_imm); ELSE(); SET(consume_modregrm_one); ENDIF();`
16
17
18
19			`(dec_ready_2byte_modregrm && decoder[7:0] == 8'hAD) \|\| (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hAC)`
20			`CMD_SHRD
21			IF(decoder[0]); SET(dec_cmdex, `CMDEX_SHxD_implicit); ELSE(); SET(dec_cmdex, `CMDEX_SHxD_modregrm_imm); ENDIF();
22			`IF(decoder[0] == 1'b0); SET(consume_modregrm_imm); ELSE(); SET(consume_modregrm_one); ENDIF();`
23
24
25
26			IF({ rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex != `CMDEX_SHxD_implicit);
27
28			`SET(rd_src_is_reg);`
29
30			`SET(rd_req_eflags);`
31
32			`// dst: reg, src: imm`
33			`IF(rd_modregrm_mod == 2'b11);`
34
35			`SET(rd_dst_is_rm);`
36
37			`SET(rd_req_rm);`
38
39			`IF(rd_mutex_busy_modregrm_rm \|\| rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();`
40			`ENDIF();`
41
42			`// dst: memory, src: imm or 1`
43			`IF(rd_modregrm_mod != 2'b11);`
44
45			`SET(rd_dst_is_memory);`
46
47			`SET(rd_req_memory);`
48
49			`IF(rd_mutex_busy_memory \|\| rd_mutex_busy_modregrm_reg); SET(rd_waiting);`
50			`ELSE();`
51			`SET(read_rmw_virtual);`
52
53			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
54			`ENDIF();`
55			`ENDIF();`
56			`ENDIF();`
57
58
59
60			IF({ rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex == `CMDEX_SHxD_implicit);
61
62			`SET(rd_src_is_reg);`
63
64			`SET(rd_req_eflags);`
65
66			`// dst: reg, src: CL`
67			`IF(rd_modregrm_mod == 2'b11);`
68
69			`SET(rd_dst_is_rm);`
70
71			`SET(rd_req_rm);`
72
73			`IF(rd_mutex_busy_modregrm_rm \|\| rd_mutex_busy_ecx \|\| rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();`
74			`ENDIF();`
75
76			`// dst: memory, src: imm or 1`
77			`IF(rd_modregrm_mod != 2'b11);`
78
79			`SET(rd_dst_is_memory);`
80
81			`SET(rd_req_memory);`
82
83			`IF(rd_mutex_busy_memory \|\| rd_mutex_busy_ecx \|\| rd_mutex_busy_modregrm_reg); SET(rd_waiting);`
84			`ELSE();`
85			`SET(read_rmw_virtual);`
86
87			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
88			`ENDIF();`
89			`ENDIF();`
90			`ENDIF();`
91
92
93
94			IF({ exe_cmd[6:1], 1'd0 } == `CMD_SHxD);
95
96			`SET(exe_result, e_shift_result);`
97			`SET(exe_result_signals, { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag });`
98
99			`ENDIF();`
100
101
102
103			IF({ wr_cmd[6:1], 1'd0 } == `CMD_SHxD);
104
105			`// result_signals`
106			`// { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag }`
107
108			`IF(~(result_signals[4])); //e_shift_no_write`
109			`IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();`
110
111			`SET(write_regrm, wr_dst_is_rm);`
112			`SET(write_rmw_virtual, wr_dst_is_memory);`
113			`ENDIF();`
114
115			`IF(result_signals[3]); //e_shift_oszapc_update`
116			`SAVE(zflag, zflag_result);`
117			`SAVE(sflag, sflag_result);`
118			`SAVE(pflag, pflag_result);`
119			`SAVE(aflag, aflag_arith);`
120			`ENDIF();`
121
122			`IF(result_signals[2]); //e_shift_cf_of_update`
123			`SAVE(cflag, result_signals[0]);`
124			`SAVE(oflag, result_signals[1]);`
125			`ENDIF();`
126			`ENDIF();`
127

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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_SHxD.txt] - Blame information for rev 2