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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_control_reg.txt] - Blame information for rev 2

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`define CMD_control_reg         #AUTOGEN_NEXT_CMD
 
`define CMDEX_control_reg_SMSW_STEP_0       4'd0
 
`define CMDEX_control_reg_LMSW_STEP_0       4'd1
`define CMDEX_control_reg_LMSW_STEP_1       4'd2
 
`define CMDEX_control_reg_MOV_store_STEP_0  4'd3
 
`define CMDEX_control_reg_MOV_load_STEP_0   4'd4
`define CMDEX_control_reg_MOV_load_STEP_1   4'd5

 

dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd4
`CMD_control_reg
SET(dec_cmdex, `CMDEX_control_reg_SMSW_STEP_0);
SET(consume_modregrm_one);

 

dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd6
`CMD_control_reg
SET(dec_cmdex, `CMDEX_control_reg_LMSW_STEP_0);
SET(consume_modregrm_one);
SET(dec_is_complex);

 

dec_ready_2byte_modregrm && { decoder[7:2], 1'b0, decoder[0] } == 8'h20
prefix_group_1_lock || (decoder[13:11] != 3'd0 && decoder[13:11] != 3'd2 && decoder[13:11] != 3'd3)
`CMD_control_reg
IF(decoder[1]); SET(dec_cmdex, `CMDEX_control_reg_MOV_load_STEP_0); ELSE(); SET(dec_cmdex, `CMDEX_control_reg_MOV_store_STEP_0); ENDIF();
SET(consume_modregrm_one);
IF(decoder[1]); SET(dec_is_complex); ENDIF();

 

IF(`CMDEX_control_reg_LMSW_STEP_0);
    LOOP(`CMDEX_control_reg_LMSW_STEP_1);
ENDIF();
 
IF(`CMDEX_control_reg_MOV_load_STEP_0);
    LOOP(`CMDEX_control_reg_MOV_load_STEP_1);
ENDIF();

 

IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_SMSW_STEP_0);
 
    IF(rd_modregrm_mod == 2'b11);
 
        SET(rd_dst_is_rm);
 
        SET(rd_req_rm);
    ENDIF();
 
    IF(rd_modregrm_mod != 2'b11);
 
        SET(rd_dst_is_memory);
 
        SET(rd_req_memory);
 
        SET(write_virtual_check);
 
        IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_LMSW_STEP_0);
 
    IF(cpl == 2'd0);
        // dst: reg, src: reg
        IF(rd_modregrm_mod == 2'b11);
 
            SET(rd_src_is_rm);
 
            // no req required
            IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();
        ENDIF();
 
        IF(rd_modregrm_mod != 2'b11);
 
            SET(rd_src_is_memory);
 
            IF(rd_mutex_busy_memory); SET(rd_waiting);
            ELSE();
                SET(read_length_word);
                SET(read_virtual);
 
                // no req required
                IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
            ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_load_STEP_0);
 
    SET(rd_src_is_rm);
 
    // no req required
    IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_store_STEP_0);
 
    SET(rd_dst_is_rm);
 
    SET(rd_req_rm);
ENDIF();

 

IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_LMSW_STEP_0);
 
    SET(exe_result2, src);
 
    IF(cpl > 2'd0);
        SET(exe_waiting);
        SET(exe_trigger_gp_fault); //exception GP(0)
    ENDIF();
ENDIF();

 

wire [31:0] e_cr0_reg;
 
assign e_cr0_reg = { cr0_pg, cr0_cd, cr0_nw, 10'b0, cr0_am, 1'b0, cr0_wp, 10'b0, cr0_ne, 1'b1, cr0_ts, cr0_em, cr0_mp, cr0_pe };

 

IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_MOV_store_STEP_0);
 
    IF(exe_modregrm_reg == 3'd0);
        SET(exe_result, e_cr0_reg);
    ENDIF();
 
    IF(exe_modregrm_reg == 3'd2);
        SET(exe_result, cr2);
    ENDIF();
 
    IF(exe_modregrm_reg == 3'd3);
        SET(exe_result, cr3);
    ENDIF();
 
    IF(cpl > 2'd0);
        SET(exe_waiting);
        SET(exe_trigger_gp_fault); //exception GP(0)
    ENDIF();
ENDIF();

 

IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_MOV_load_STEP_0);
 
    SET(exe_result2, src);
 
    IF(cpl > 2'd0 || (exe_modregrm_reg == 3'd0 && ((src[31] && ~(src[0])) || (src[29] && ~(src[30]))))); // CR0: (PG && ~PE) || (NW && ~CD)
        SET(exe_waiting);
        SET(exe_trigger_gp_fault); //exception GP(0)
    ENDIF();
ENDIF();

 

IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_SMSW_STEP_0);
    SET(exe_result, e_cr0_reg);
ENDIF();

 

IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_SMSW_STEP_0);
 
    SET(write_length_word);
 
    IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
 
    SET(write_regrm,     wr_dst_is_rm);
    SET(write_virtual,   wr_dst_is_memory);
ENDIF();

 

IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_LMSW_STEP_0);
 
    SAVE(cr0_pe, cr0_pe | result2[0]);
    SAVE(cr0_mp, result2[1]);
    SAVE(cr0_em, result2[2]);
    SAVE(cr0_ts, result2[3]);
 
    IF(cr0_pe ^ result2[0]);
        SET(tlbflushall_do); //can not enable paging this way, so no need to wait for flush
    ENDIF();
 
    // reset all pipeline
    SET(wr_req_reset_pr);
    SET(wr_req_reset_dec);
    SET(wr_req_reset_micro);
    SET(wr_req_reset_rd);
    SET(wr_req_reset_exe);
ENDIF();

 

IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_MOV_store_STEP_0);
    SET(wr_regrm_dword);
    SET(write_regrm);
ENDIF();

 

IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_MOV_load_STEP_0);
 
    IF(wr_decoder[13:11] == 3'd0);
        SAVE(cr0_pe, result2[0]);
        SAVE(cr0_mp, result2[1]);
        SAVE(cr0_em, result2[2]);
        SAVE(cr0_ts, result2[3]);
        SAVE(cr0_ne, result2[5]);
        SAVE(cr0_wp, result2[16]);
        SAVE(cr0_am, result2[18]);
        SAVE(cr0_nw, result2[29]);
        SAVE(cr0_cd, result2[30]);
        SAVE(cr0_pg, result2[31]);
 
        IF((cr0_pe ^ result2[0]) || (cr0_wp ^ result2[16]) || (cr0_pg ^ result[31]));
            SET(tlbflushall_do);
        ENDIF();
 
        //entering real mode
        IF(cr0_pe && result2[0] == 1'b0);
            SAVE(cs_cache, { cs_cache[63:48], 1'b1, cs_cache[46:45], 1'b1, 4'b0011, cs_cache[39:0] }); //present, segment=1, data r/w/a
        ENDIF();
    ENDIF();
 
    IF(wr_decoder[13:11] == 3'd2);
        SAVE(cr2, result2);
    ENDIF();
 
    IF(wr_decoder[13:11] == 3'd3);
        SET(tlbflushall_do);
 
        SAVE(cr3, result2);
    ENDIF();
 
    // clear pipeline -- paging may be enabled
    SET(wr_req_reset_pr);
    SET(wr_req_reset_dec);
    SET(wr_req_reset_micro);
    SET(wr_req_reset_rd);
    SET(wr_req_reset_exe);
ENDIF();

 

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Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_control_reg.txt] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik
2
3			`define CMD_control_reg #AUTOGEN_NEXT_CMD
4
5			`define CMDEX_control_reg_SMSW_STEP_0 4'd0
6
7			`define CMDEX_control_reg_LMSW_STEP_0 4'd1
8			`define CMDEX_control_reg_LMSW_STEP_1 4'd2
9
10			`define CMDEX_control_reg_MOV_store_STEP_0 4'd3
11
12			`define CMDEX_control_reg_MOV_load_STEP_0 4'd4
13			`define CMDEX_control_reg_MOV_load_STEP_1 4'd5
14
15
16
17			`dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd4`
18			`CMD_control_reg
19			SET(dec_cmdex, `CMDEX_control_reg_SMSW_STEP_0);
20			`SET(consume_modregrm_one);`
21
22
23
24			`dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd6`
25			`CMD_control_reg
26			SET(dec_cmdex, `CMDEX_control_reg_LMSW_STEP_0);
27			`SET(consume_modregrm_one);`
28			`SET(dec_is_complex);`
29
30
31
32			`dec_ready_2byte_modregrm && { decoder[7:2], 1'b0, decoder[0] } == 8'h20`
33			`prefix_group_1_lock \|\| (decoder[13:11] != 3'd0 && decoder[13:11] != 3'd2 && decoder[13:11] != 3'd3)`
34			`CMD_control_reg
35			IF(decoder[1]); SET(dec_cmdex, `CMDEX_control_reg_MOV_load_STEP_0); ELSE(); SET(dec_cmdex, `CMDEX_control_reg_MOV_store_STEP_0); ENDIF();
36			`SET(consume_modregrm_one);`
37			`IF(decoder[1]); SET(dec_is_complex); ENDIF();`
38
39
40
41			IF(`CMDEX_control_reg_LMSW_STEP_0);
42			LOOP(`CMDEX_control_reg_LMSW_STEP_1);
43			`ENDIF();`
44
45			IF(`CMDEX_control_reg_MOV_load_STEP_0);
46			LOOP(`CMDEX_control_reg_MOV_load_STEP_1);
47			`ENDIF();`
48
49
50
51			IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_SMSW_STEP_0);
52
53			`IF(rd_modregrm_mod == 2'b11);`
54
55			`SET(rd_dst_is_rm);`
56
57			`SET(rd_req_rm);`
58			`ENDIF();`
59
60			`IF(rd_modregrm_mod != 2'b11);`
61
62			`SET(rd_dst_is_memory);`
63
64			`SET(rd_req_memory);`
65
66			`SET(write_virtual_check);`
67
68			`IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();`
69			`ENDIF();`
70			`ENDIF();`
71
72
73
74			IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_LMSW_STEP_0);
75
76			`IF(cpl == 2'd0);`
77			`// dst: reg, src: reg`
78			`IF(rd_modregrm_mod == 2'b11);`
79
80			`SET(rd_src_is_rm);`
81
82			`// no req required`
83			`IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();`
84			`ENDIF();`
85
86			`IF(rd_modregrm_mod != 2'b11);`
87
88			`SET(rd_src_is_memory);`
89
90			`IF(rd_mutex_busy_memory); SET(rd_waiting);`
91			`ELSE();`
92			`SET(read_length_word);`
93			`SET(read_virtual);`
94
95			`// no req required`
96			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
97			`ENDIF();`
98			`ENDIF();`
99			`ENDIF();`
100			`ENDIF();`
101
102
103
104			IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_load_STEP_0);
105
106			`SET(rd_src_is_rm);`
107
108			`// no req required`
109			`IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();`
110			`ENDIF();`
111
112
113
114			IF(rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_store_STEP_0);
115
116			`SET(rd_dst_is_rm);`
117
118			`SET(rd_req_rm);`
119			`ENDIF();`
120
121
122
123			IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_LMSW_STEP_0);
124
125			`SET(exe_result2, src);`
126
127			`IF(cpl > 2'd0);`
128			`SET(exe_waiting);`
129			`SET(exe_trigger_gp_fault); //exception GP(0)`
130			`ENDIF();`
131			`ENDIF();`
132
133
134
135			`wire [31:0] e_cr0_reg;`
136
137			`assign e_cr0_reg = { cr0_pg, cr0_cd, cr0_nw, 10'b0, cr0_am, 1'b0, cr0_wp, 10'b0, cr0_ne, 1'b1, cr0_ts, cr0_em, cr0_mp, cr0_pe };`
138
139
140
141			IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_MOV_store_STEP_0);
142
143			`IF(exe_modregrm_reg == 3'd0);`
144			`SET(exe_result, e_cr0_reg);`
145			`ENDIF();`
146
147			`IF(exe_modregrm_reg == 3'd2);`
148			`SET(exe_result, cr2);`
149			`ENDIF();`
150
151			`IF(exe_modregrm_reg == 3'd3);`
152			`SET(exe_result, cr3);`
153			`ENDIF();`
154
155			`IF(cpl > 2'd0);`
156			`SET(exe_waiting);`
157			`SET(exe_trigger_gp_fault); //exception GP(0)`
158			`ENDIF();`
159			`ENDIF();`
160
161
162
163			IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_MOV_load_STEP_0);
164
165			`SET(exe_result2, src);`
166
167			`IF(cpl > 2'd0 \|\| (exe_modregrm_reg == 3'd0 && ((src[31] && ~(src[0])) \|\| (src[29] && ~(src[30]))))); // CR0: (PG && ~PE) \|\| (NW && ~CD)`
168			`SET(exe_waiting);`
169			`SET(exe_trigger_gp_fault); //exception GP(0)`
170			`ENDIF();`
171			`ENDIF();`
172
173
174
175			IF(exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_SMSW_STEP_0);
176			`SET(exe_result, e_cr0_reg);`
177			`ENDIF();`
178
179
180
181			IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_SMSW_STEP_0);
182
183			`SET(write_length_word);`
184
185			`IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();`
186
187			`SET(write_regrm, wr_dst_is_rm);`
188			`SET(write_virtual, wr_dst_is_memory);`
189			`ENDIF();`
190
191
192
193			IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_LMSW_STEP_0);
194
195			`SAVE(cr0_pe, cr0_pe \| result2[0]);`
196			`SAVE(cr0_mp, result2[1]);`
197			`SAVE(cr0_em, result2[2]);`
198			`SAVE(cr0_ts, result2[3]);`
199
200			`IF(cr0_pe ^ result2[0]);`
201			`SET(tlbflushall_do); //can not enable paging this way, so no need to wait for flush`
202			`ENDIF();`
203
204			`// reset all pipeline`
205			`SET(wr_req_reset_pr);`
206			`SET(wr_req_reset_dec);`
207			`SET(wr_req_reset_micro);`
208			`SET(wr_req_reset_rd);`
209			`SET(wr_req_reset_exe);`
210			`ENDIF();`
211
212
213
214			IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_MOV_store_STEP_0);
215			`SET(wr_regrm_dword);`
216			`SET(write_regrm);`
217			`ENDIF();`
218
219
220
221			IF(wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_MOV_load_STEP_0);
222
223			`IF(wr_decoder[13:11] == 3'd0);`
224			`SAVE(cr0_pe, result2[0]);`
225			`SAVE(cr0_mp, result2[1]);`
226			`SAVE(cr0_em, result2[2]);`
227			`SAVE(cr0_ts, result2[3]);`
228			`SAVE(cr0_ne, result2[5]);`
229			`SAVE(cr0_wp, result2[16]);`
230			`SAVE(cr0_am, result2[18]);`
231			`SAVE(cr0_nw, result2[29]);`
232			`SAVE(cr0_cd, result2[30]);`
233			`SAVE(cr0_pg, result2[31]);`
234
235			`IF((cr0_pe ^ result2[0]) \|\| (cr0_wp ^ result2[16]) \|\| (cr0_pg ^ result[31]));`
236			`SET(tlbflushall_do);`
237			`ENDIF();`
238
239			`//entering real mode`
240			`IF(cr0_pe && result2[0] == 1'b0);`
241			`SAVE(cs_cache, { cs_cache[63:48], 1'b1, cs_cache[46:45], 1'b1, 4'b0011, cs_cache[39:0] }); //present, segment=1, data r/w/a`
242			`ENDIF();`
243			`ENDIF();`
244
245			`IF(wr_decoder[13:11] == 3'd2);`
246			`SAVE(cr2, result2);`
247			`ENDIF();`
248
249			`IF(wr_decoder[13:11] == 3'd3);`
250			`SET(tlbflushall_do);`
251
252			`SAVE(cr3, result2);`
253			`ENDIF();`
254
255			`// clear pipeline -- paging may be enabled`
256			`SET(wr_req_reset_pr);`
257			`SET(wr_req_reset_dec);`
258			`SET(wr_req_reset_micro);`
259			`SET(wr_req_reset_rd);`
260			`SET(wr_req_reset_exe);`
261			`ENDIF();`
262
263