OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_task_switch.txt] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik 
 
2
3 
`define TASK_SWITCH_FROM_IRET   2'd0
4 
`define TASK_SWITCH_FROM_INT    2'd1
5 
`define TASK_SWITCH_FROM_CALL   2'd2
6 
`define TASK_SWITCH_FROM_JUMP   2'd3
7 
 
8 
`define TASK_SWITCH_SOURCE_BITS 17:16
9 
 
10 
//------------------------------------------------------------------------------
11 
 
12 
`define CMD_task_switch     #AUTOGEN_NEXT_CMD
13 
// glob_param_1[15:0]  --> new_tr
14 
// glob_param_1[17:16] --> source
15 
// glob_param_2        --> [used internal]
16 
// glob_param_3[15:0]  --> error_code
17 
// glob_param_3[16]    --> push code flag
18 
// glob_param_3[17]    --> [internal] is push 32 bit (TSS386)
19 
// glob_param_3[21:18] --> cmd_len
20 
// glob_descriptor     --> new_tr_cache
21 
 
22 
`define CMDEX_task_switch_STEP_1     4'd1
23 
// check limits
24 
 
25 
`define CMDEX_task_switch_STEP_2     4'd2
26 
`define CMDEX_task_switch_STEP_3     4'd3
27 
`define CMDEX_task_switch_STEP_4     4'd4
28 
`define CMDEX_task_switch_STEP_5     4'd5
29 
// check translation for new tss
30 
 
31 
`define CMDEX_task_switch_STEP_6    4'd6
32 
// turn off busy descriptor type
33 
 
34 
`define CMDEX_task_switch_STEP_7    4'd7
35 
`define CMDEX_task_switch_STEP_8    4'd8
36 
// check translation for old tss
37 
 
38 
`define CMDEX_task_switch_STEP_9    4'd9
39 
`define CMDEX_task_switch_STEP_10   4'd10
40 
// write old eip,eflags
41 
`define CMDEX_task_switch_STEP_11   4'd11
42 
// write link
43 
`define CMDEX_task_switch_STEP_12   4'd12
44 
`define CMDEX_task_switch_STEP_13   4'd13
45 
`define CMDEX_task_switch_STEP_14   4'd14
46 
// read cr3,eip,eflags
47 
 
48 
//------------------------------------------------------------------------------
49 
 
50 
`define CMD_task_switch_2   #AUTOGEN_NEXT_CMD
51 
 
52 
`define CMDEX_task_switch_2_STEP_0  4'd0
53 
`define CMDEX_task_switch_2_STEP_7  4'd7
54 
`define CMDEX_task_switch_2_STEP_11 4'd11
55 
`define CMDEX_task_switch_2_STEP_13 4'd13
56 
 
57 
//------------------------------------------------------------------------------
58 
 
59 
`define CMD_task_switch_3   #AUTOGEN_NEXT_CMD
60 
 
61 
`define CMDEX_task_switch_3_STEP_0  4'd0
62 
`define CMDEX_task_switch_3_STEP_7  4'd7
63 
`define CMDEX_task_switch_3_STEP_8  4'd8
64 
`define CMDEX_task_switch_3_STEP_12 4'd12
65 
`define CMDEX_task_switch_3_STEP_15 4'd15
66 
 
67 
//------------------------------------------------------------------------------
68 
 
69 
`define CMD_task_switch_4   #AUTOGEN_NEXT_CMD
70 
 
71 
`define CMDEX_task_switch_4_STEP_0  4'd0
72 
`define CMDEX_task_switch_4_STEP_1  4'd1
73 
`define CMDEX_task_switch_4_STEP_2  4'd2
74 
`define CMDEX_task_switch_4_STEP_3  4'd3
75 
`define CMDEX_task_switch_4_STEP_4  4'd4
76 
`define CMDEX_task_switch_4_STEP_5  4'd5
77 
`define CMDEX_task_switch_4_STEP_6  4'd6
78 
`define CMDEX_task_switch_4_STEP_7  4'd7
79 
`define CMDEX_task_switch_4_STEP_8  4'd8
80 
`define CMDEX_task_switch_4_STEP_9  4'd9
81 
`define CMDEX_task_switch_4_STEP_10 4'd10
82
83 
 
84
85 
IF(`CMDEX_task_switch_STEP_1 && cr0_pg);
86 
    `CMDEX_task_switch_STEP_2
87 
    `CMDEX_task_switch_STEP_3
88 
 
89 
    IF(`CMDEX_task_switch_STEP_3 && (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT));
90 
        `CMDEX_task_switch_STEP_4
91 
        `CMDEX_task_switch_STEP_5
92 
        `CMDEX_task_switch_STEP_6
93 
    ENDIF();
94 
 
95 
    IF(`CMDEX_task_switch_STEP_3 && ~(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT));
96 
        `CMDEX_task_switch_STEP_6
97 
    ENDIF();
98 
 
99 
ENDIF();
100 
 
101 
IF(`CMDEX_task_switch_STEP_1 && ~(cr0_pg));
102 
    `CMDEX_task_switch_STEP_6
103 
ENDIF();
104 
 
105 
IF(`CMDEX_task_switch_STEP_6 && cr0_pg);
106 
    `CMDEX_task_switch_STEP_7
107 
    `CMDEX_task_switch_STEP_8
108 
    `CMDEX_task_switch_STEP_9
109 
ENDIF();
110 
 
111 
IF(`CMDEX_task_switch_STEP_6 && ~(cr0_pg));
112 
    `CMDEX_task_switch_STEP_9
113 
ENDIF();
114 
 
115 
IF(`CMDEX_task_switch_STEP_9);
116 
    `CMDEX_task_switch_STEP_10
117 
    `CMDEX_task_switch_2_STEP_0
118 
 
119 
    IF(mc_cmd == `CMD_task_switch_2 && mc_cmdex_last < `CMDEX_task_switch_2_STEP_13);
120 
        DIRECT(mc_cmd, mc_cmdex_last + 4'd1);
121 
    ENDIF();
122 
 
123 
    IF(`CMDEX_task_switch_2_STEP_13);
124 
        `CMDEX_task_switch_STEP_11
125 
        `CMDEX_task_switch_STEP_12
126 
        `CMDEX_task_switch_STEP_13
127 
        `CMDEX_task_switch_STEP_14
128 
        `CMDEX_task_switch_3_STEP_0
129 
    ENDIF();
130 
ENDIF();
131 
 
132 
IF(mc_cmd == `CMD_task_switch_3);
133 
    DIRECT(mc_cmd, mc_cmdex_last + 4'd1);
134 
ENDIF();
135 
 
136 
IF(`CMDEX_task_switch_3_STEP_15);
137 
    `CMDEX_task_switch_4_STEP_0
138 
ENDIF();
139 
 
140 
IF(mc_cmd == `CMD_task_switch_4 && mc_cmdex_last < `CMDEX_task_switch_4_STEP_10);
141 
    DIRECT(mc_cmd, mc_cmdex_last + 4'd1);
142 
ENDIF();
143 
 
144 
IF(`CMDEX_task_switch_4_STEP_10)
145 
    LOOP(`CMDEX_task_switch_4_STEP_10);
146 
ENDIF();
147
148 
 
149
150 
wire [31:0] rd_task_switch_linear_next;
151 
 
152 
reg [31:0] rd_task_switch_linear_reg;
153 
 
154 
assign rd_task_switch_linear_next =
155 
    (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? rd_task_switch_linear_reg + 32'd2 :
156 
                                                rd_task_switch_linear_reg + 32'd4;
157 
 
158 
always @(posedge clk or negedge rst_n) begin
159 
    if(rst_n == 1'b0)                                                               rd_task_switch_linear_reg <= 32'd0;
160 
    else if(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_12)   rd_task_switch_linear_reg <= rd_system_linear;
161 
    else if(rd_ready)                                                               rd_task_switch_linear_reg <= rd_task_switch_linear_next;
162 
end
163
164 
 
165
166 
IF(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_6);
167 
 
168 
    SET(rd_system_linear, gdtr_base + { 16'd0, tr[15:3], 3'd0 } + 32'd4);
169 
 
170 
    IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- exception possible
171 
    ELSE();
172 
        IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET);
173 
 
174 
            SET(rd_req_memory);
175 
 
176 
            SET(rd_glob_param_2_set);
177 
            SET(rd_glob_param_2_value, read_4);
178 
 
179 
            IF(rd_mutex_busy_memory); SET(rd_waiting);
180 
            ELSE();
181 
                SET(read_rmw_system_dword);
182 
 
183 
                IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
184 
            ENDIF();
185 
        ENDIF();
186 
    ENDIF();
187 
ENDIF();
188
189 
 
190
191 
IF(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_9);
192 
    IF(rd_mutex_busy_memory); SET(rd_waiting); ENDIF();
193 
ENDIF();
194
195 
 
196
197 
IF(rd_cmd == `CMD_task_switch_2 && rd_cmdex <= `CMDEX_task_switch_2_STEP_7);
198 
    SET(rd_src_is_cmdex);
199 
ENDIF();
200
201 
 
202
203 
IF(rd_cmd == `CMD_task_switch_2 && rd_cmdex == `CMDEX_task_switch_2_STEP_13);
204 
    SET(rd_req_memory);
205 
ENDIF();
206
207 
 
208
209 
IF(rd_cmd == `CMD_task_switch && rd_cmdex >= `CMDEX_task_switch_STEP_12 && rd_cmdex <= `CMDEX_task_switch_STEP_14);
210 
 
211 
    IF(rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3); SET(rd_system_linear, glob_desc_base + 32'd12); ENDIF();
212 
    IF(rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] >  4'd3); SET(rd_system_linear, glob_desc_base + 32'h1C); ENDIF();
213 
    IF(rd_cmdex == `CMDEX_task_switch_STEP_13 || rd_cmdex == `CMDEX_task_switch_STEP_14);   SET(rd_system_linear, rd_task_switch_linear_next); ENDIF();
214 
 
215 
    IF(rd_cmdex != `CMDEX_task_switch_STEP_12 || (glob_descriptor[`DESC_BITS_TYPE] > 4'd3 && cr0_pg));
216 
 
217 
        IF(rd_mutex_busy_memory); SET(rd_waiting);
218 
        ELSE();
219 
            SET(read_system_dword, glob_descriptor[`DESC_BITS_TYPE] >  4'd3);
220 
            SET(read_system_word,  glob_descriptor[`DESC_BITS_TYPE] <= 4'd3);
221 
 
222 
            SET(rd_src_is_memory);
223 
 
224 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
225 
        ENDIF();
226 
    ENDIF();
227 
ENDIF();
228
229 
 
230
231 
IF(rd_cmd == `CMD_task_switch_3);
232 
 
233 
    SET(rd_system_linear, rd_task_switch_linear_next);
234 
 
235 
    IF(rd_cmdex <= `CMDEX_task_switch_3_STEP_12 || glob_descriptor[`DESC_BITS_TYPE] > 4'd3);
236 
 
237 
        SET(read_system_dword, glob_descriptor[`DESC_BITS_TYPE] >  4'd3 && rd_cmdex <= `CMDEX_task_switch_3_STEP_7);
238 
        SET(read_system_word,  glob_descriptor[`DESC_BITS_TYPE] <= 4'd3 || rd_cmdex > `CMDEX_task_switch_3_STEP_7);
239 
 
240 
        SET(rd_src_is_memory);
241 
 
242 
        IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
243 
    ENDIF();
244 
ENDIF();
245
246 
 
247 
 
248
249 
IF(rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_0);
250 
 
251 
    SET(rd_system_linear, gdtr_base + { 16'd0, glob_param_1[15:3], 3'd0 } + 32'd4);
252 
 
253 
    IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- wait for read complete
254 
    ELSE();
255 
 
256 
        IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET);
257 
 
258 
            SET(read_rmw_system_dword);
259 
 
260 
            SET(rd_src_is_memory);
261 
 
262 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
263 
        ENDIF();
264 
    ENDIF();
265 
ENDIF();
266
267 
 
268
269 
// load ldt
270 
 
271 
IF(rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_2);
272 
 
273 
    IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- wait for write complete; needed for TLB flush
274 
    ELSE();
275 
 
276 
        IF(glob_param_1[`SELECTOR_BIT_TI] == 1'b0 && glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits)); // load null; not in limits
277 
 
278 
            SET(rd_glob_descriptor_set);
279 
            SET(rd_glob_descriptor_value, read_8);
280 
 
281 
            SET(rd_glob_param_2_set);
282 
            SET(rd_glob_param_2_value, 32'd0);
283 
 
284 
            SET(read_system_descriptor);
285 
 
286 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
287 
 
288 
        ELSE();
289 
            SET(rd_glob_param_2_set);
290 
            SET(rd_glob_param_2_value, { 29'd0, glob_param_1[`SELECTOR_BIT_TI], rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 });
291 
        ENDIF();
292 
    ENDIF();
293 
ENDIF();
294
295 
 
296 
 
297 
//param_4 used: fs, gs
298 
//param_2 used: control bits
299 
 
300
301 
// load ss,ds,es,fs,gs,cs
302 
 
303 
IF(rd_cmd == `CMD_task_switch_4 && rd_cmdex >= `CMDEX_task_switch_4_STEP_3 && rd_cmdex <= `CMDEX_task_switch_4_STEP_8);
304 
 
305 
    IF(rd_mutex_busy_active); SET(rd_waiting); // wait for previous step -- wait for write complete for glob_param_1; glob_param_2; write ldt
306 
    ELSE();
307 
 
308 
        IF(v8086_mode);
309 
            SET(rd_glob_descriptor_set);
310 
            SET(rd_glob_descriptor_value, `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,glob_param_1[15:12], glob_param_1[11:0],4'd0, 16'hFFFF });
311 
 
312 
            SET(rd_glob_param_2_set);
313 
            SET(rd_glob_param_2_value, 32'd0);
314 
        ELSE();
315 
 
316 
            IF(glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits)); // load null; not in limits
317 
 
318 
                SET(rd_glob_descriptor_set);
319 
                SET(rd_glob_descriptor_value, read_8);
320 
 
321 
                SET(rd_glob_param_2_set);
322 
                SET(rd_glob_param_2_value, 32'd0);
323 
 
324 
                SET(read_system_descriptor);
325 
 
326 
                IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
327 
            ELSE();
328 
                SET(rd_glob_param_2_set);
329 
                SET(rd_glob_param_2_value, { 30'd0, rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 });
330 
            ENDIF();
331 
 
332 
        ENDIF();
333 
    ENDIF();
334 
ENDIF();
335
336 
 
337
338 
wire [31:0] exe_new_tss_max;
339 
 
340 
assign exe_new_tss_max = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 32'h2B : 32'h67;
341 
 
342
343 
 
344
345 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_1);
346 
 
347 
    IF(glob_desc_limit < exe_new_tss_max);
348 
        SET(exe_waiting);
349 
        SET(exe_trigger_ts_fault); //exception TS(val)
350 
        SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
351 
    ENDIF();
352 
 
353 
    IF(tr_limit < ((tr_cache[`DESC_BITS_TYPE] <= 4'd3)? 32'h29 : 32'h5F));
354 
        SET(exe_waiting);
355 
        SET(exe_trigger_ts_fault); //exception TS(val)
356 
        SET(exe_error_code, `SELECTOR_FOR_CODE(tr));
357 
    ENDIF();
358 
ENDIF();
359
360 
 
361
362 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_2);
363 
 
364 
    SET(tlbcheck_do);
365 
    SET(tlbcheck_rw,       `FALSE);
366 
    SET(tlbcheck_address,   glob_desc_base);
367 
 
368 
    IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
369 
 
370 
    IF(tlbcheck_page_fault);
371 
        SET(exe_waiting);
372 
 
373 
        SET(exe_trigger_pf_fault); //exception PF(val)
374 
    ENDIF();
375 
ENDIF();
376
377 
 
378
379 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_3);
380 
 
381 
    SET(tlbcheck_do);
382 
    SET(tlbcheck_rw,       `FALSE);
383 
    SET(tlbcheck_address,   glob_desc_base + exe_new_tss_max);
384 
 
385 
    IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
386 
 
387 
    IF(tlbcheck_page_fault);
388 
        SET(exe_waiting);
389 
 
390 
        SET(exe_trigger_pf_fault); //exception PF(val)
391 
    ENDIF();
392 
ENDIF();
393
394 
 
395
396 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_4);
397 
 
398 
    SET(tlbcheck_do);
399 
    SET(tlbcheck_rw,       `TRUE);
400 
    SET(tlbcheck_address,   glob_desc_base);
401 
 
402 
    IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
403 
 
404 
    IF(tlbcheck_page_fault);
405 
        SET(exe_waiting);
406 
 
407 
        SET(exe_trigger_pf_fault); //exception PF(val)
408 
    ENDIF();
409 
ENDIF();
410
411 
 
412
413 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_5);
414 
 
415 
    SET(tlbcheck_do);
416 
    SET(tlbcheck_rw,       `TRUE);
417 
    SET(tlbcheck_address,   glob_desc_base + 32'd1);
418 
 
419 
    IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
420 
 
421 
    IF(tlbcheck_page_fault);
422 
        SET(exe_waiting);
423 
 
424 
        SET(exe_trigger_pf_fault); //exception PF(val)
425 
    ENDIF();
426 
ENDIF();
427
428 
 
429
430 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_7);
431 
 
432 
    SET(tlbcheck_do);
433 
    SET(tlbcheck_rw,       `TRUE);
434 
    SET(tlbcheck_address,   (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd14 : tr_base + 32'h20);
435 
 
436 
    IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
437 
 
438 
    IF(tlbcheck_page_fault);
439 
        SET(exe_waiting);
440 
 
441 
        SET(exe_trigger_pf_fault); //exception PF(val)
442 
    ENDIF();
443 
ENDIF();
444
445 
 
446
447 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_8);
448 
 
449 
    SET(tlbcheck_do);
450 
    SET(tlbcheck_rw,       `TRUE);
451 
    SET(tlbcheck_address,   (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd41 : tr_base + 32'h5D);
452 
 
453 
 
454 
    IF(~(tlbcheck_done) && ~(tlbcheck_page_fault)); SET(exe_waiting); ENDIF();
455 
 
456 
    IF(tlbcheck_page_fault);
457 
        SET(exe_waiting);
458 
 
459 
        SET(exe_trigger_pf_fault); //exception PF(val)
460 
    ENDIF();
461 
ENDIF();
462
463 
 
464
465 
IF(exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_10);
466 
    SET(exe_result_push, exe_push_eflags);
467 
ENDIF();
468
469 
 
470
471 
IF(exe_cmd == `CMD_task_switch && exe_cmdex >= `CMDEX_task_switch_STEP_12 && exe_cmdex <= `CMDEX_task_switch_STEP_14);
472 
 
473 
    IF(exe_ready);
474 
        SAVE(exe_buffer, src);
475 
        SET(exe_buffer_shift);
476 
    ENDIF();
477 
ENDIF();
478
479 
 
480
481 
IF(exe_cmd == `CMD_task_switch_2);
482 
 
483 
    IF(exe_cmdex <= `CMDEX_task_switch_2_STEP_7);
484 
        SET(exe_result2, src);
485 
    ENDIF();
486 
 
487 
    IF(exe_cmdex > `CMDEX_task_switch_2_STEP_7);
488 
        SET(exe_result2, { 16'd0, e_seg_by_cmdex });
489 
    ENDIF();
490 
ENDIF();
491
492 
 
493
494 
IF(exe_cmd == `CMD_task_switch_3);
495 
 
496 
    IF(exe_ready);
497 
        SAVE(exe_buffer, (exe_cmdex == `CMDEX_task_switch_3_STEP_15 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 32'd0 : src);
498 
 
499 
        SET(exe_buffer_shift,       exe_cmdex <= `CMDEX_task_switch_3_STEP_8);
500 
        SET(exe_buffer_shift_word,  exe_cmdex >  `CMDEX_task_switch_3_STEP_8);
501 
    ENDIF();
502 
ENDIF();
503
504 
 
505
506 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_0);
507 
    SET(exe_result2, src);
508 
ENDIF();
509
510 
 
511
512 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_2);
513 
 
514 
    IF(glob_param_2[2] || glob_param_2[2:0] == 3'b010 || (
515 
        glob_param_2[2:0] == 3'b000 && (
516 
            exe_descriptor[`DESC_BIT_SEG] ||
517 
            exe_descriptor[`DESC_BITS_TYPE] != `DESC_LDT ||
518 
            exe_descriptor[`DESC_BIT_P] == `FALSE
519 
        )
520 
    ));
521 
 
522 
        SET(exe_waiting);
523 
 
524 
        SET(exe_trigger_ts_fault);
525 
        SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
526 
    ENDIF();
527 
ENDIF();
528
529 
 
530
531 
// load ss
532 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_3);
533 
 
534 
    IF(~(v8086_mode));
535 
 
536 
        IF(glob_param_2[1:0] != 2'b00 || (
537 
            exe_descriptor[`DESC_BIT_SEG] == 1'b0 ||
538 
            `DESC_IS_CODE(exe_descriptor) ||
539 
            `DESC_IS_DATA_RO(exe_descriptor) ||
540 
            (exe_descriptor[`DESC_BIT_P] && (
541 
                exe_descriptor[`DESC_BITS_DPL] != wr_task_rpl ||
542 
                exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL]
543 
                )
544 
            )
545 
        ));
546 
 
547 
            SET(exe_waiting);
548 
 
549 
            SET(exe_trigger_ts_fault);
550 
            SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
551 
        ENDIF();
552 
 
553 
        IF(glob_param_2[1:0] == 2'b00 && exe_descriptor[`DESC_BIT_SEG] && `DESC_IS_DATA_RW(exe_descriptor) && ~(exe_descriptor[`DESC_BIT_P]));
554 
            SET(exe_waiting);
555 
 
556 
            SET(exe_trigger_ss_fault);
557 
            SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
558 
        ENDIF();
559 
    ENDIF();
560 
ENDIF();
561
562 
 
563
564 
// load ds,es,fs,gs
565 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex >= `CMDEX_task_switch_4_STEP_4 && exe_cmdex <= `CMDEX_task_switch_4_STEP_7);
566 
 
567 
    IF(~(v8086_mode));
568 
 
569 
        IF(glob_param_2[1:0] == 2'b10 || (glob_param_2[1:0] == 2'b00 && (
570 
            exe_descriptor[`DESC_BIT_SEG] == 1'b0 ||
571 
            `DESC_IS_CODE_EO(exe_descriptor) ||
572 
            ((`DESC_IS_DATA(exe_descriptor) || `DESC_IS_CODE_NON_CONFORMING(exe_descriptor)) && exe_privilege_not_accepted)
573 
        )));
574 
 
575 
            SET(exe_waiting);
576 
 
577 
            SET(exe_trigger_ts_fault);
578 
            SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
579 
        ENDIF();
580 
 
581 
        IF(glob_param_2[1:0] == 2'b00 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]));
582 
            SET(exe_waiting);
583 
 
584 
            SET(exe_trigger_np_fault);
585 
            SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
586 
        ENDIF();
587 
    ENDIF();
588 
ENDIF();
589
590 
 
591
592 
// load cs
593 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_8);
594 
 
595 
    IF(~(v8086_mode));
596 
 
597 
        IF(glob_param_2[1:0] != 2'b00 || (
598 
            exe_descriptor[`DESC_BIT_SEG] == 1'b0 ||
599 
            `DESC_IS_DATA(exe_descriptor) ||
600 
            (`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL]) ||
601 
            (`DESC_IS_CODE_CONFORMING(exe_descriptor)     && exe_descriptor[`DESC_BITS_DPL] >  exe_selector[`SELECTOR_BITS_RPL])
602 
        ));
603 
 
604 
            SET(exe_waiting);
605 
 
606 
            SET(exe_trigger_ts_fault);
607 
            SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
608 
        ENDIF();
609 
 
610 
        IF(glob_param_2[1:0] == 2'b00 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]));
611 
            SET(exe_waiting);
612 
 
613 
            SET(exe_trigger_np_fault);
614 
            SET(exe_error_code, `SELECTOR_FOR_CODE(glob_param_1));
615 
        ENDIF();
616 
    ENDIF();
617 
ENDIF();
618
619 
 
620
621 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_9);
622 
    SET(offset_task);
623 
    SET(exe_result_push, { 16'd0, glob_param_3[15:0] });
624 
ENDIF();
625
626 
 
627
628 
// check eip
629 
IF(exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_10);
630 
 
631 
    SET(exe_glob_param_2_set);
632 
    SET(exe_glob_param_2_value, exe_eip);
633 
 
634 
    SET(exe_eip_from_glob_param_2);
635 
 
636 
    SET(exe_task_switch_finished);
637 
 
638 
    IF(exe_eip > cs_limit);
639 
        SET(exe_waiting);
640 
        SET(exe_trigger_gp_fault); //exception GP(0)
641 
    ENDIF();
642 
ENDIF();
643
644 
 
645
646 
wire [31:0] wr_task_switch_linear;
647 
wire [31:0] wr_task_switch_linear_next;
648 
 
649 
reg  [31:0] wr_task_switch_linear_reg;
650 
 
651 
 
652 
assign wr_task_switch_linear =
653 
    (wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9 && tr_cache[`DESC_BITS_TYPE] <= 4'd3)?     tr_base + 32'd14 :
654 
    (wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9 && tr_cache[`DESC_BITS_TYPE] > 4'd3)?      tr_base + 32'h20 :
655 
                                                                                                                    wr_task_switch_linear_next;
656 
assign wr_task_switch_linear_next =
657 
    (tr_cache[`DESC_BITS_TYPE] <= 4'd3)?    wr_task_switch_linear_reg + 32'd2 :
658 
                                            wr_task_switch_linear_reg + 32'd4;
659 
 
660 
always @(posedge clk or negedge rst_n) begin
661 
    if(rst_n == 1'b0)                                                               wr_task_switch_linear_reg <= 32'd0;
662 
    else if(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9)    wr_task_switch_linear_reg <= wr_task_switch_linear;
663 
    else if(wr_ready)                                                               wr_task_switch_linear_reg <= wr_task_switch_linear_next;
664 
end
665
666 
 
667
668 
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_1);
669 
    SET(wr_debug_trap_clear);
670 
 
671 
    SET(wr_not_finished);
672 
ENDIF();
673
674 
 
675
676 
IF(wr_cmd == `CMD_task_switch && (wr_cmdex == `CMDEX_task_switch_STEP_2 || wr_cmdex == `CMDEX_task_switch_STEP_3 || wr_cmdex == `CMDEX_task_switch_STEP_4 || wr_cmdex == `CMDEX_task_switch_STEP_5));
677 
    SET(wr_not_finished);
678 
ENDIF();
679
680 
 
681
682 
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_6);
683 
 
684 
    SET(wr_not_finished);
685 
 
686 
    IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET);
687 
        SET(wr_system_dword, glob_param_2 & 32'hFFFFFDFF);
688 
 
689 
        SET(write_rmw_system_dword);
690 
 
691 
        IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
692 
 
693 
    ENDIF();
694 
ENDIF();
695
696 
 
697
698 
IF(wr_cmd == `CMD_task_switch && (wr_cmdex == `CMDEX_task_switch_STEP_7 || wr_cmdex == `CMDEX_task_switch_STEP_8));
699 
    SET(wr_not_finished);
700 
ENDIF();
701
702 
 
703
704 
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9);
705 
    SET(wr_not_finished);
706 
 
707 
    SET(wr_system_dword,  (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT)? exc_eip : eip);
708 
    SET(wr_system_linear, wr_task_switch_linear);
709 
 
710 
    SET(write_system_word,  tr_cache[`DESC_BITS_TYPE] <= 4'd3);
711 
    SET(write_system_dword, tr_cache[`DESC_BITS_TYPE] > 4'd3);
712 
 
713 
    IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
714 
ENDIF();
715
716 
 
717
718 
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_10);
719 
    SET(wr_not_finished);
720 
 
721 
    SET(wr_system_dword,  result_push &
722 
            ((glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_286 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_386)? 32'hFFFFBFFF : 32'hFFFFFFFF));
723 
    SET(wr_system_linear, wr_task_switch_linear);
724 
 
725 
    SET(write_system_word,  tr_cache[`DESC_BITS_TYPE] <= 4'd3);
726 
    SET(write_system_dword, tr_cache[`DESC_BITS_TYPE] > 4'd3);
727 
 
728 
    IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
729 
ENDIF();
730
731 
 
732
733 
IF(wr_cmd == `CMD_task_switch_2 && wr_cmdex <= `CMDEX_task_switch_2_STEP_13);
734 
    SET(wr_not_finished);
735 
 
736 
    IF(tr_cache[`DESC_BITS_TYPE] > 4'd3 || wr_cmdex <= `CMDEX_task_switch_2_STEP_11);
737 
        SET(wr_system_dword,  result2);
738 
        SET(wr_system_linear, wr_task_switch_linear);
739 
 
740 
        SET(write_system_word,  tr_cache[`DESC_BITS_TYPE] <= 4'd3 || wr_cmdex > `CMDEX_task_switch_2_STEP_7);
741 
        SET(write_system_dword, tr_cache[`DESC_BITS_TYPE] > 4'd3  && wr_cmdex <= `CMDEX_task_switch_2_STEP_7);
742 
 
743 
        IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
744 
    ENDIF();
745 
ENDIF();
746
747 
 
748
749 
IF(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_11);
750 
    SET(wr_not_finished);
751 
 
752 
    IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT);
753 
 
754 
        SET(wr_system_dword,  { 16'd0, tr });
755 
        SET(wr_system_linear, glob_desc_base);
756 
 
757 
        SET(write_system_word);
758 
 
759 
        IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
760 
    ENDIF();
761 
ENDIF();
762
763 
 
764
765 
IF(wr_cmd == `CMD_task_switch && wr_cmdex >= `CMDEX_task_switch_STEP_12 && wr_cmdex <= `CMDEX_task_switch_STEP_14);
766 
    SET(wr_not_finished);
767 
ENDIF();
768
769 
 
770
771 
IF(wr_cmd == `CMD_task_switch_3);
772 
    SET(wr_not_finished);
773 
ENDIF();
774
775 
 
776
777 
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_0);
778 
 
779 
    SET(wr_not_finished);
780 
 
781 
    IF(glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET);
782 
        SET(wr_system_dword, result2 | 32'h00000200);
783 
 
784 
        SET(write_rmw_system_dword);
785 
 
786 
        IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
787 
    ENDIF();
788 
ENDIF();
789
790 
 
791
792 
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_1);
793 
 
794 
    SET(wr_not_finished);
795 
 
796 
    SET(wr_make_esp_commit);
797 
 
798 
    SET(wr_glob_param_1_set);
799 
    SET(wr_glob_param_1_value, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 13'd0, `SEGMENT_LDT, exe_buffer_shifted[47:32] } : { 13'd0, `SEGMENT_LDT, exe_buffer_shifted[15:0] });
800 
 
801 
    SET(wr_glob_param_3_set);
802 
    SET(wr_glob_param_3_value, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? glob_param_3 : glob_param_3 | 32'h00020000); //bit 17: [internal] is push 32 bit (TSS386)
803 
 
804 
    SET(wr_glob_param_4_set);
805 
    SET(wr_glob_param_4_value, { task_fs, task_gs });
806 
 
807 
    SAVE(eax, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[351:336] } : exe_buffer_shifted[367:336]);
808 
    SAVE(ecx, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[319:304] } : exe_buffer_shifted[335:304]);
809 
    SAVE(edx, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[287:272] } : exe_buffer_shifted[303:272]);
810 
    SAVE(ebx, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[255:240] } : exe_buffer_shifted[271:240]);
811 
    SAVE(esp, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[223:208] } : exe_buffer_shifted[239:208]);
812 
    SAVE(ebp, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[191:176] } : exe_buffer_shifted[207:176]);
813 
    SAVE(esi, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[159:144] } : exe_buffer_shifted[175:144]);
814 
    SAVE(edi, (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[127:112] } : exe_buffer_shifted[143:112]);
815 
 
816 
    SAVE(cflag,  task_eflags[0]);
817 
    SAVE(pflag,  task_eflags[2]);
818 
    SAVE(aflag,  task_eflags[4]);
819 
    SAVE(zflag,  task_eflags[6]);
820 
    SAVE(sflag,  task_eflags[7]);
821 
    SAVE(tflag,  task_eflags[8]);
822 
    SAVE(iflag,  task_eflags[9]);
823 
    SAVE(dflag,  task_eflags[10]);
824 
    SAVE(oflag,  task_eflags[11]);
825 
    SAVE(iopl,   task_eflags[13:12]);
826 
    SAVE(ntflag, task_eflags[14] |  +
827 
            (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT));
828 
    SAVE(rflag,  task_eflags[16]);
829 
    SAVE(vmflag, task_eflags[17]);
830 
    SAVE(acflag, task_eflags[18]);
831 
    SAVE(idflag, task_eflags[21]);
832 
 
833 
    SAVE(dr7, dr7 & 32'hFFFFFEAA);
834 
 
835 
    SAVE(cr0_ts, `TRUE);
836 
 
837 
    //set tr, tr_cache, tr_cache.type |= 2 -- set busy
838 
    SAVE(tr,         glob_param_1[15:0]);
839 
    SAVE(tr_rpl,     glob_param_1[1:0]);
840 
    SAVE(tr_cache,   glob_descriptor | 64'h0000020000000000);
841 
 
842 
    //set selectors, cache valid: 6+ldt
843 
    SAVE(cs,             task_cs);
844 
    SAVE(cs_cache_valid, `FALSE);
845 
    SAVE(cs_rpl,         2'd3);
846 
 
847 
    SAVE(wr_task_rpl, task_cs[1:0]);
848 
 
849 
    SAVE(ds,                task_ds);
850 
    SAVE(ds_cache_valid,    `FALSE);
851 
    SAVE(ds_rpl,            task_ds[1:0]);
852 
 
853 
    SAVE(es,                task_es);
854 
    SAVE(es_cache_valid,    `FALSE);
855 
    SAVE(es_rpl,            task_es[1:0]);
856 
 
857 
    SAVE(fs,                task_fs);
858 
    SAVE(fs_cache_valid,    `FALSE);
859 
    SAVE(fs_rpl,            task_fs[1:0]);
860 
 
861 
    SAVE(gs,                task_gs);
862 
    SAVE(gs_cache_valid,    `FALSE);
863 
    SAVE(gs_rpl,            task_gs[1:0]);
864 
 
865 
    SAVE(ss,                task_ss);
866 
    SAVE(ss_cache_valid,    `FALSE);
867 
    SAVE(ss_rpl,            task_ss[1:0]);
868 
 
869 
    SAVE(ldtr,              task_ldtr);
870 
    SAVE(ldtr_cache_valid,  `FALSE);
871 
    SAVE(ldtr_rpl,          task_ldtr[1:0]);
872 
 
873 
    IF(glob_descriptor[`DESC_BITS_TYPE] >= 4'd9 && cr0_pg && cr3 != exe_buffer_shifted[463:432]);
874 
        SAVE(cr3, exe_buffer_shifted[463:432]);
875 
 
876 
        SET(tlbflushall_do);
877 
    ENDIF();
878 
ENDIF();
879
880 
 
881
882 
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_2);
883 
 
884 
    SET(wr_not_finished);
885 
 
886 
    SET(wr_glob_param_1_set);
887 
    SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_SS, task_ss });
888 
 
889 
    IF(glob_param_2[2:0] == 3'b000);
890 
        SAVE(ldtr_cache,         glob_descriptor);
891 
        SAVE(ldtr_cache_valid,   `TRUE);
892 
    ENDIF();
893 
ENDIF();
894
895 
 
896
897 
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex >= `CMDEX_task_switch_4_STEP_3 && wr_cmdex <= `CMDEX_task_switch_4_STEP_8);
898 
 
899 
    SET(wr_not_finished);
900 
 
901 
    IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3); SAVE(cs_rpl, wr_task_rpl); ENDIF();
902 
 
903 
    IF(glob_param_2[1:0] == 2'b00 && ~(v8086_mode) && `DESC_IS_NOT_ACCESSED(glob_descriptor));
904 
 
905 
        SET(write_system_touch);
906 
 
907 
        IF(~(write_for_wr_ready)); SET(wr_waiting);
908 
        ELSE();
909 
            IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3);
910 
                SET(wr_glob_param_1_set);
911 
                SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_DS, task_ds });
912 
            ENDIF();
913 
            IF(wr_cmdex == `CMDEX_task_switch_4_STEP_4);
914 
                SET(wr_glob_param_1_set);
915 
                SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_ES, task_es });
916 
            ENDIF();
917 
            IF(wr_cmdex == `CMDEX_task_switch_4_STEP_5);
918 
                SET(wr_glob_param_1_set);
919 
                SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_FS, glob_param_4[31:16] });
920 
            ENDIF();
921 
            IF(wr_cmdex == `CMDEX_task_switch_4_STEP_6);
922 
                SET(wr_glob_param_1_set);
923 
                SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_GS, glob_param_4[15:0] });
924 
            ENDIF();
925 
            IF(wr_cmdex == `CMDEX_task_switch_4_STEP_7);
926 
                SET(wr_glob_param_1_set);
927 
                SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_CS, task_cs });
928 
            ENDIF();
929 
 
930 
            SET(wr_seg_cache_valid,  `TRUE);
931 
            SET(write_seg_cache_valid);
932 
 
933 
            SET(write_seg_cache);
934 
        ENDIF();
935 
    ENDIF();
936 
 
937 
    IF(glob_param_2[1:0] == 2'b00 && `DESC_IS_ACCESSED(glob_descriptor));
938 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3);
939 
            SET(wr_glob_param_1_set);
940 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_DS, task_ds });
941 
        ENDIF();
942 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_4);
943 
            SET(wr_glob_param_1_set);
944 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_ES, task_es });
945 
        ENDIF();
946 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_5);
947 
            SET(wr_glob_param_1_set);
948 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_FS, glob_param_4[31:16] });
949 
        ENDIF();
950 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_6);
951 
            SET(wr_glob_param_1_set);
952 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_GS, glob_param_4[15:0] });
953 
        ENDIF();
954 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_7);
955 
            SET(wr_glob_param_1_set);
956 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_CS, task_cs });
957 
        ENDIF();
958 
 
959 
        SET(wr_seg_sel, glob_param_1[15:0]);
960 
 
961 
        SET(wr_seg_cache_valid,  `TRUE);
962 
        SET(write_seg_cache_valid);
963 
 
964 
        SET(write_seg_cache);
965 
 
966 
        IF(v8086_mode);
967 
            SET(wr_seg_rpl,      2'd3);
968 
            SET(write_seg_rpl);
969 
        ENDIF();
970 
    ENDIF();
971 
 
972 
    IF(glob_param_2[1:0] != 2'b00);
973 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_3);
974 
            SET(wr_glob_param_1_set);
975 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_DS, task_ds });
976 
        ENDIF();
977 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_4);
978 
            SET(wr_glob_param_1_set);
979 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_ES, task_es });
980 
        ENDIF();
981 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_5);
982 
            SET(wr_glob_param_1_set);
983 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_FS, glob_param_4[31:16] });
984 
        ENDIF();
985 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_6);
986 
            SET(wr_glob_param_1_set);
987 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_GS, glob_param_4[15:0] });
988 
        ENDIF();
989 
        IF(wr_cmdex == `CMDEX_task_switch_4_STEP_7);
990 
            SET(wr_glob_param_1_set);
991 
            SET(wr_glob_param_1_value, { 13'd0, `SEGMENT_CS, task_cs });
992 
        ENDIF();
993 
    ENDIF();
994 
ENDIF();
995
996 
 
997
998 
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_9);
999 
 
1000 
    SET(wr_not_finished);
1001 
 
1002 
    SET(wr_push_length_word,  ~(glob_param_3[17]));
1003 
    SET(wr_push_length_dword, glob_param_3[17]);
1004 
 
1005 
    IF(glob_param_3[16]); // push error code
1006 
 
1007 
        SET(wr_push_ss_fault_check);
1008 
        SET(wr_one_cycle_wait);
1009 
 
1010 
        SET(wr_make_esp_speculative);
1011 
 
1012 
        IF(~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
1013 
 
1014 
        IF(~(wr_push_ss_fault));
1015 
            SAVE(esp, wr_stack_esp);
1016 
 
1017 
            SET(write_stack_virtual);
1018 
        ENDIF();
1019 
    ENDIF();
1020 
ENDIF();
1021
1022 
 
1023
1024 
IF(wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_10);
1025 
    SET(wr_make_esp_commit);
1026 
 
1027 
    // finish exception/interrupt
1028 
    SET(wr_exception_finished);
1029 
 
1030 
    IF(glob_param_3[17] && task_trap[0]); SET(wr_debug_task_trigger); ENDIF();
1031 
 
1032 
    // clear pipeline
1033 
    SET(wr_req_reset_pr);
1034 
    SET(wr_req_reset_dec);
1035 
    SET(wr_req_reset_micro);
1036 
    SET(wr_req_reset_rd);
1037 
    SET(wr_req_reset_exe);
1038 
ENDIF();
1039

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.