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/*
 * Copyright (c) 2014, Aleksander Osman
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
`include "defines.v"
 
//PARSED_COMMENTS: this file contains parsed script comments
 
module dcache(
    // global
    input               clk,
    input               rst_n,
 
    //RESP:
    input               dcacheread_do,
    output              dcacheread_done,
 
    input   [3:0]       dcacheread_length,
    input               dcacheread_cache_disable,
    input   [31:0]      dcacheread_address,
    output  [63:0]      dcacheread_data,
    //END
 
    //RESP:
    input               dcachewrite_do,
    output              dcachewrite_done,
 
    input   [2:0]       dcachewrite_length,
    input               dcachewrite_cache_disable,
    input   [31:0]      dcachewrite_address,
    input               dcachewrite_write_through,
    input   [31:0]      dcachewrite_data,
    //END
 
    //REQ:
    output              readline_do,
    input               readline_done,
 
    output  [31:0]      readline_address,
    input   [127:0]     readline_line,
    //END
 
    //REQ:
    output              readburst_do,
    input               readburst_done,
 
    output  [31:0]      readburst_address,
    output  [1:0]       readburst_dword_length,
    output  [3:0]       readburst_byte_length,
    input   [95:0]      readburst_data,
    //END
 
    //REQ: write line
    output              writeline_do,
    input               writeline_done,
 
    output      [31:0]  writeline_address,
    output      [127:0] writeline_line,
    //END
 
    //REQ:
    output              writeburst_do,
    input               writeburst_done,
 
    output      [31:0]  writeburst_address,
    output      [1:0]   writeburst_dword_length,
    output      [3:0]   writeburst_byteenable_0,
    output      [3:0]   writeburst_byteenable_1,
    output      [55:0]  writeburst_data,
    //END
 
    output              dcachetoicache_write_do,
    output      [31:0]  dcachetoicache_write_address,
 
    //RESP:
    input               invddata_do,
    output              invddata_done,
    //END
 
    //RESP:
    input               wbinvddata_do,
    output              wbinvddata_done,
    //END
 
    output              dcache_busy
);
 
//------------------------------------------------------------------------------
 
reg [31:0]  address;
reg         cache_disable;
reg [3:0]   length;
 
reg         write_through;
reg [31:0]  write_data;
 
reg         is_write;
reg [2:0]   state;
 
//------------------------------------------------------------------------------
 
localparam [2:0] STATE_IDLE          = 3'd0;
localparam [2:0] STATE_READ_CHECK    = 3'd1;
localparam [2:0] STATE_READ_BURST    = 3'd2;
localparam [2:0] STATE_WRITE_BACK    = 3'd3;
localparam [2:0] STATE_READ_LINE     = 3'd4;
localparam [2:0] STATE_WRITE_CHECK   = 3'd5;
localparam [2:0] STATE_WRITE_THROUGH = 3'd6;
 
//------------------------------------------------------------------------------
 
wire        wbinvdread_do;
wire [7:0]  wbinvdread_address;
 
wire            dcache_writeline_do;
wire [31:0]     dcache_writeline_address;
wire [127:0]    dcache_writeline_line;
 
//------------------------------------------------------------------------------
 
assign writeline_do         = dcache_writeline_do || control_ram_writeline_do;
assign writeline_address    = (dcache_writeline_do)? dcache_writeline_address : control_ram_writeline_address;
assign writeline_line       = (dcache_writeline_do)? dcache_writeline_line    : control_ram_writeline_line;
 
assign dcache_busy = state != STATE_IDLE;
 
//------------------------------------------------------------------------------
 
wire [31:0] control_ram_address;
wire        control_ram_read_do;
wire        control_ram_write_do;
wire [10:0] control_ram_data;
wire [10:0] control_ram_q;
 
wire            control_ram_writeline_do;
wire [31:0]     control_ram_writeline_address;
wire [127:0]    control_ram_writeline_line;
 
//------------------------------------------------------------------------------
 
wire         matched;
wire [1:0]   matched_index;
wire [127:0] matched_data_line;
 
wire [1:0]   plru_index;
wire [147:0] plru_data_line;
 
wire [10:0]  control_after_match;
wire [10:0]  control_after_line_read;
wire [10:0]  control_after_write_to_existing;
wire [10:0]  control_after_write_to_new;
 
wire         writeback_needed;
 
//------------------------------------------------------------------------------
 
wire [63:0] read_from_line;
wire [1:0]  read_burst_dword_length;
wire [3:0]  read_burst_byte_length;
wire [63:0] read_from_burst;
 
//------------------------------------------------------------------------------
 
wire [127:0] line_merged;
wire [1:0]   write_burst_dword_length;
wire [3:0]   write_burst_byteenable_0;
wire [3:0]   write_burst_byteenable_1;
wire [55:0]  write_burst_data;
 
//------------------------------------------------------------------------------
 
wire            data_ram0_read_do;
wire [31:0]     data_ram0_address;
wire            data_ram0_write_do;
wire [127:0]    data_ram0_data;
wire [147:0]    data_ram0_q;
 
wire            data_ram1_read_do;
wire [31:0]     data_ram1_address;
wire            data_ram1_write_do;
wire [127:0]    data_ram1_data;
wire [147:0]    data_ram1_q;
 
wire            data_ram2_read_do;
wire [31:0]     data_ram2_address;
wire            data_ram2_write_do;
wire [127:0]    data_ram2_data;
wire [147:0]    data_ram2_q;
 
wire            data_ram3_read_do;
wire [31:0]     data_ram3_address;
wire            data_ram3_write_do;
wire [127:0]    data_ram3_data;
wire [147:0]    data_ram3_q;
 
//------------------------------------------------------------------------------
 
dcache_matched dcache_matched_inst(
    .address    (address),  //input [31:0]
 
    .control    (control_ram_q),    //input [10:0]
 
    .data_0     (data_ram0_q),      //input [147:0]
    .data_1     (data_ram1_q),      //input [147:0]
    .data_2     (data_ram2_q),      //input [147:0]
    .data_3     (data_ram3_q),      //input [147:0]
 
    .matched            (matched),              //output
    .matched_index      (matched_index),        //output [2:0]
    .matched_data_line  (matched_data_line),    //output [127:0]
 
    .plru_index         (plru_index),           //output [1:0]
    .plru_data_line     (plru_data_line),       //output [147:0]
 
    .control_after_match                (control_after_match),              //output [10:0]
    .control_after_line_read            (control_after_line_read),          //output [10:0]
    .control_after_write_to_existing    (control_after_write_to_existing),  //output [10:0]
    .control_after_write_to_new         (control_after_write_to_new),       //output [10:0]
 
    .writeback_needed                   (writeback_needed)                  //output
);
 
 
 
dcache_read dcache_read_inst(
 
    .line       ((state == STATE_READ_LINE)? readline_line : matched_data_line),    //input [127:0]
    .read_data  (readburst_data),                                                   //input [95:0]                         
 
    .address    (address),                                                          //input [31:0]
    .length     (length),                                                           //input [3:0]
 
    .read_from_line             (read_from_line),               //output [63:0]
    .read_burst_dword_length    (read_burst_dword_length),      //output [1:0]
    .read_burst_byte_length     (read_burst_byte_length),       //output [11:0]
    .read_from_burst            (read_from_burst)               //output [63:0]
);
 
dcache_write dcache_write_inst(
 
    .line       ((state == STATE_READ_LINE)? readline_line : matched_data_line),    //input [127:0]
    .address    (address),                                                          //input [31:0]
    .length     (length[2:0]),                                                      //input [2:0]
    .write_data (write_data),                                                       //input [31:0]
 
    .write_burst_dword_length   (write_burst_dword_length),     //output [1:0]
    .write_burst_byteenable_0   (write_burst_byteenable_0),     //output [3:0]
    .write_burst_byteenable_1   (write_burst_byteenable_1),     //output [3:0]
    .write_burst_data           (write_burst_data),             //output [55:0]
    .line_merged                (line_merged)                   //output [127:0]
);
 
dcache_control_ram dcache_control_ram_inst(
    .clk        (clk),
    .rst_n      (rst_n),
 
    .address        (control_ram_address),      //input [31:0]
    .data           (control_ram_data),         //input [10:0]
 
    .q              (control_ram_q),            //output [10:0]
 
    .read_do        (control_ram_read_do),
 
 
    .write_do       (control_ram_write_do),
 
    //RESP:
    .invddata_do        (invddata_do && state == STATE_IDLE),   //input
    .invddata_done      (invddata_done),                        //output
    //END
 
    //RESP:
    .wbinvddata_do      (wbinvddata_do && state == STATE_IDLE), //input
    .wbinvddata_done    (wbinvddata_done),                      //output
    //END
 
 
    //REQ:
    .wbinvdread_do      (wbinvdread_do),        //output
    .wbinvdread_address (wbinvdread_address),   //output [7:0]
 
    .wbinvdread_ram0_q      (data_ram0_q),  //input [147:0]
    .wbinvdread_ram1_q      (data_ram1_q),  //input [147:0]
    .wbinvdread_ram2_q      (data_ram2_q),  //input [147:0]
    .wbinvdread_ram3_q      (data_ram3_q),  //input [147:0]
    //END
 
    //REQ: write line
    .writeline_do           (control_ram_writeline_do),         //output
    .writeline_done         (writeline_done),                   //input
 
    .writeline_address      (control_ram_writeline_address),    //output [31:0]
    .writeline_line         (control_ram_writeline_line)        //output [127:0]
    //END
);
 
cache_data_ram cache_data_ram0_inst(
    .clk        (clk),
    .rst_n      (rst_n),
 
    .read_do        (data_ram0_read_do),
    .address        (data_ram0_address),
 
    .write_do       (data_ram0_write_do),
    .data           (data_ram0_data),
    .q              (data_ram0_q)
);
 
 
 
cache_data_ram cache_data_ram1_inst(
    .clk        (clk),
    .rst_n      (rst_n),
 
    .read_do    (data_ram1_read_do),
    .address    (data_ram1_address),
 
    .write_do       (data_ram1_write_do),
    .data           (data_ram1_data),
    .q              (data_ram1_q)
);
 
 
 
cache_data_ram cache_data_ram2_inst(
    .clk        (clk),
    .rst_n      (rst_n),
 
    .read_do        (data_ram2_read_do),
    .address        (data_ram2_address),
 
    .write_do       (data_ram2_write_do),
    .data           (data_ram2_data),
    .q              (data_ram2_q)
);
 
cache_data_ram cache_data_ram3_inst(
    .clk        (clk),
    .rst_n      (rst_n),
 
    .read_do        (data_ram3_read_do),
    .address        (data_ram3_address),
 
    .write_do       (data_ram3_write_do),
    .data           (data_ram3_data),
    .q              (data_ram3_q)
);
 
 
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
 
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_IDLE);
 
    IF(invddata_do);
 
        //wait
 
    ELSE_IF(wbinvddata_do);
 
        SET(data_ram0_read_do, wbinvdread_do);
        SET(data_ram0_address, { 20'd0, wbinvdread_address, 4'd0 });
 
        SET(data_ram1_read_do, wbinvdread_do);
        SET(data_ram1_address, { 20'd0, wbinvdread_address, 4'd0 });
 
        SET(data_ram2_read_do, wbinvdread_do);
        SET(data_ram2_address, { 20'd0, wbinvdread_address, 4'd0 });
 
        SET(data_ram3_read_do, wbinvdread_do);
        SET(data_ram3_address, { 20'd0, wbinvdread_address, 4'd0 });
 
    ELSE_IF(dcachewrite_do);
 
        SAVE(address,        dcachewrite_address);
        SAVE(cache_disable,  dcachewrite_cache_disable);
        SAVE(length,         { 1'b0, dcachewrite_length });
 
        SAVE(write_through,  dcachewrite_write_through);
        SAVE(write_data,     dcachewrite_data);
 
        SAVE(is_write, `TRUE);
 
        SET(control_ram_read_do);
        SET(control_ram_address, dcachewrite_address);
 
        SET(data_ram0_read_do);
        SET(data_ram0_address, dcachewrite_address);
 
        SET(data_ram1_read_do);
        SET(data_ram1_address, dcachewrite_address);
 
        SET(data_ram2_read_do);
        SET(data_ram2_address, dcachewrite_address);
 
        SET(data_ram3_read_do);
        SET(data_ram3_address, dcachewrite_address);
 
        SET(dcachewrite_done);
 
        SAVE(state, STATE_WRITE_CHECK);
 
    ELSE_IF(dcacheread_do);
 
        SAVE(address,        dcacheread_address);
        SAVE(cache_disable,  dcacheread_cache_disable);
        SAVE(length,         dcacheread_length);
 
        SAVE(is_write, `FALSE);
 
        SET(control_ram_read_do);
        SET(control_ram_address,     dcacheread_address);
 
        SET(data_ram0_read_do);
        SET(data_ram0_address, dcacheread_address);
 
        SET(data_ram1_read_do);
        SET(data_ram1_address, dcacheread_address);
 
        SET(data_ram2_read_do);
        SET(data_ram2_address, dcacheread_address);
 
        SET(data_ram3_read_do);
        SET(data_ram3_address, dcacheread_address);
 
        SAVE(state, STATE_READ_CHECK);
 
    ENDIF();
ENDIF();
*/
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_READ_CHECK);
 
    IF(matched);
 
        SET(control_ram_write_do);
        SET(control_ram_address,     address);
        SET(control_ram_data,        control_after_match);
 
        SET(dcacheread_data, read_from_line);
        SET(dcacheread_done);
 
        SAVE(state, STATE_IDLE);
 
    ELSE_IF(cache_disable);
 
        SET(readburst_do);
        SET(readburst_address,      address);
        SET(readburst_dword_length, read_burst_dword_length);
        SET(readburst_byte_length,  read_burst_byte_length);
 
        SAVE(state, STATE_READ_BURST);
 
    ELSE_IF(writeback_needed);
 
        SET(dcache_writeline_do);
        SET(dcache_writeline_address, { plru_data_line[147:128], address[11:4], 4'd0 });
        SET(dcache_writeline_line,    plru_data_line[127:0]);
 
        SAVE(state, STATE_WRITE_BACK);
 
    ELSE();
 
        SET(readline_do);
        SET(readline_address, { address[31:4], 4'd0 });
 
        SAVE(state, STATE_READ_LINE);
    ENDIF();
 
ENDIF();
*/
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_WRITE_CHECK);
 
    IF(matched);
 
        SET(control_ram_write_do);
        SET(control_ram_address,     address);
        SET(control_ram_data,        control_after_write_to_existing);
 
        IF(matched_index == 2'd0);
            SET(data_ram0_write_do);
            SET(data_ram0_address,   address);
            SET(data_ram0_data,      line_merged);
        ENDIF();
 
        IF(matched_index == 2'd1);
            SET(data_ram1_write_do);
            SET(data_ram1_address,   address);
            SET(data_ram1_data,      line_merged);
        ENDIF();
 
        IF(matched_index == 2'd2);
            SET(data_ram2_write_do);
            SET(data_ram2_address,   address);
            SET(data_ram2_data,      line_merged);
        ENDIF();
 
        IF(matched_index == 2'd3);
            SET(data_ram3_write_do);
            SET(data_ram3_address,   address);
            SET(data_ram3_data,      line_merged);
        ENDIF();
 
        IF(write_through);
 
            SET(writeburst_do);
            SET(writeburst_address,      address);
            SET(writeburst_dword_length, write_burst_dword_length);
            SET(writeburst_byteenable_0, write_burst_byteenable_0);
            SET(writeburst_byteenable_1, write_burst_byteenable_1);
            SET(writeburst_data,         write_burst_data);
 
            SAVE(state, STATE_WRITE_THROUGH);
 
        ELSE();
 
            SET(dcachetoicache_write_do);
            SET(dcachetoicache_write_address, address);
 
            SAVE(state, STATE_IDLE);
        ENDIF();
 
    ELSE_IF(cache_disable);
 
        SET(writeburst_do);
        SET(writeburst_address,      address);
        SET(writeburst_dword_length, write_burst_dword_length);
        SET(writeburst_byteenable_0, write_burst_byteenable_0);
        SET(writeburst_byteenable_1, write_burst_byteenable_1);
        SET(writeburst_data,         write_burst_data);
 
        SAVE(state, STATE_WRITE_THROUGH);
 
    ELSE_IF(writeback_needed); // cache enabled and full
 
        SET(dcache_writeline_do);
        SET(dcache_writeline_address, { plru_data_line[147:128], address[11:4], 4'd0 });
        SET(dcache_writeline_line,    plru_data_line[127:0]);
 
        SAVE(state, STATE_WRITE_BACK);
 
    ELSE(); // cache enabled and not full
 
        SET(readline_do);
        SET(readline_address, { address[31:4], 4'd0 });
 
        SAVE(state, STATE_READ_LINE);
 
    ENDIF();
ENDIF();
*/
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_READ_BURST);
 
    IF(readburst_done);
 
        SET(dcacheread_data, read_from_burst);
        SET(dcacheread_done);
 
        SAVE(state, STATE_IDLE);
    ENDIF();
ENDIF();
*/
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_WRITE_BACK);
 
    IF(writeline_done);
 
        SET(readline_do);
        SET(readline_address, { address[31:4], 4'd0 });
 
        SAVE(state, STATE_READ_LINE);
 
    ENDIF();
ENDIF();
*/
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_READ_LINE);
 
    IF(readline_done);
 
        IF(is_write);
 
            SET(control_ram_write_do);
            SET(control_ram_address,     address);
            SET(control_ram_data,        control_after_write_to_new);
 
            IF(plru_index == 2'd0);
                SET(data_ram0_write_do);
                SET(data_ram0_address,   address);
                SET(data_ram0_data,      line_merged);
            ENDIF();
 
            IF(plru_index == 2'd1);
                SET(data_ram1_write_do);
                SET(data_ram1_address,   address);
                SET(data_ram1_data,      line_merged);
            ENDIF();
 
            IF(plru_index == 2'd2);
                SET(data_ram2_write_do);
                SET(data_ram2_address,   address);
                SET(data_ram2_data,      line_merged);
            ENDIF();
 
            IF(plru_index == 2'd3);
                SET(data_ram3_write_do);
                SET(data_ram3_address,   address);
                SET(data_ram3_data,      line_merged);
            ENDIF();
 
            IF(write_through);
 
                SET(writeburst_do);
                SET(writeburst_address,      address);
                SET(writeburst_dword_length, write_burst_dword_length);
                SET(writeburst_byteenable_0, write_burst_byteenable_0);
                SET(writeburst_byteenable_1, write_burst_byteenable_1);
                SET(writeburst_data,         write_burst_data);
 
                SAVE(state, STATE_WRITE_THROUGH);
 
            ELSE();
 
                SET(dcachetoicache_write_do);
                SET(dcachetoicache_write_address, address);
 
                SAVE(state, STATE_IDLE);
            ENDIF();
 
        ELSE();
 
            SET(control_ram_write_do);
            SET(control_ram_address,     address);
            SET(control_ram_data,        control_after_line_read);
 
            IF(plru_index == 2'd0);
                SET(data_ram0_write_do);
                SET(data_ram0_address,   address);
                SET(data_ram0_data,      readline_line);
            ENDIF();
 
            IF(plru_index == 2'd1);
                SET(data_ram1_write_do);
                SET(data_ram1_address,    address);
                SET(data_ram1_data, readline_line);
            ENDIF();
 
            IF(plru_index == 2'd2);
                SET(data_ram2_write_do);
                SET(data_ram2_address,   address);
                SET(data_ram2_data,      readline_line);
            ENDIF();
 
            IF(plru_index == 2'd3);
                SET(data_ram3_write_do);
                SET(data_ram3_address,   address);
                SET(data_ram3_data,      readline_line);
            ENDIF();
 
            SET(dcacheread_data, read_from_line);
            SET(dcacheread_done);
 
            SAVE(state, STATE_IDLE);
        ENDIF();
 
    ENDIF();
ENDIF();
*/
 
/*******************************************************************************SCRIPT
 
IF(state == STATE_WRITE_THROUGH);
 
    IF(writeburst_done);
 
        SET(dcachetoicache_write_do);
        SET(dcachetoicache_write_address, address);
 
        SAVE(state, STATE_IDLE);
    ENDIF();
ENDIF();
*/
 
//------------------------------------------------------------------------------
 
`include "autogen/dcache.v"
 
endmodule

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[/] [ao486/] [trunk/] [rtl/] [ao486/] [memory/] [dcache.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* Copyright (c) 2014, Aleksander Osman`
3			`* All rights reserved.`
4			`*`
5			`* Redistribution and use in source and binary forms, with or without`
6			`* modification, are permitted provided that the following conditions are met:`
7			`*`
8			`* * Redistributions of source code must retain the above copyright notice, this`
9			`* list of conditions and the following disclaimer.`
10			`*`
11			`* * Redistributions in binary form must reproduce the above copyright notice,`
12			`* this list of conditions and the following disclaimer in the documentation`
13			`* and/or other materials provided with the distribution.`
14			`*`
15			`* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
16			`* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
17			`* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
18			`* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
19			`* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
20			`* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
21			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
22			`* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
23			`* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
24			`* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
25			`*/`
26
27			`include "defines.v"
28
29			`//PARSED_COMMENTS: this file contains parsed script comments`
30
31			`module dcache(`
32			`// global`
33			`input clk,`
34			`input rst_n,`
35
36			`//RESP:`
37			`input dcacheread_do,`
38			`output dcacheread_done,`
39
40			`input [3:0] dcacheread_length,`
41			`input dcacheread_cache_disable,`
42			`input [31:0] dcacheread_address,`
43			`output [63:0] dcacheread_data,`
44			`//END`
45
46			`//RESP:`
47			`input dcachewrite_do,`
48			`output dcachewrite_done,`
49
50			`input [2:0] dcachewrite_length,`
51			`input dcachewrite_cache_disable,`
52			`input [31:0] dcachewrite_address,`
53			`input dcachewrite_write_through,`
54			`input [31:0] dcachewrite_data,`
55			`//END`
56
57			`//REQ:`
58			`output readline_do,`
59			`input readline_done,`
60
61			`output [31:0] readline_address,`
62			`input [127:0] readline_line,`
63			`//END`
64
65			`//REQ:`
66			`output readburst_do,`
67			`input readburst_done,`
68
69			`output [31:0] readburst_address,`
70			`output [1:0] readburst_dword_length,`
71			`output [3:0] readburst_byte_length,`
72			`input [95:0] readburst_data,`
73			`//END`
74
75			`//REQ: write line`
76			`output writeline_do,`
77			`input writeline_done,`
78
79			`output [31:0] writeline_address,`
80			`output [127:0] writeline_line,`
81			`//END`
82
83			`//REQ:`
84			`output writeburst_do,`
85			`input writeburst_done,`
86
87			`output [31:0] writeburst_address,`
88			`output [1:0] writeburst_dword_length,`
89			`output [3:0] writeburst_byteenable_0,`
90			`output [3:0] writeburst_byteenable_1,`
91			`output [55:0] writeburst_data,`
92			`//END`
93
94			`output dcachetoicache_write_do,`
95			`output [31:0] dcachetoicache_write_address,`
96
97			`//RESP:`
98			`input invddata_do,`
99			`output invddata_done,`
100			`//END`
101
102			`//RESP:`
103			`input wbinvddata_do,`
104			`output wbinvddata_done,`
105			`//END`
106
107			`output dcache_busy`
108			`);`
109
110			`//------------------------------------------------------------------------------`
111
112			`reg [31:0] address;`
113			`reg cache_disable;`
114			`reg [3:0] length;`
115
116			`reg write_through;`
117			`reg [31:0] write_data;`
118
119			`reg is_write;`
120			`reg [2:0] state;`
121
122			`//------------------------------------------------------------------------------`
123
124			`localparam [2:0] STATE_IDLE = 3'd0;`
125			`localparam [2:0] STATE_READ_CHECK = 3'd1;`
126			`localparam [2:0] STATE_READ_BURST = 3'd2;`
127			`localparam [2:0] STATE_WRITE_BACK = 3'd3;`
128			`localparam [2:0] STATE_READ_LINE = 3'd4;`
129			`localparam [2:0] STATE_WRITE_CHECK = 3'd5;`
130			`localparam [2:0] STATE_WRITE_THROUGH = 3'd6;`
131
132			`//------------------------------------------------------------------------------`
133
134			`wire wbinvdread_do;`
135			`wire [7:0] wbinvdread_address;`
136
137			`wire dcache_writeline_do;`
138			`wire [31:0] dcache_writeline_address;`
139			`wire [127:0] dcache_writeline_line;`
140
141			`//------------------------------------------------------------------------------`
142
143			`assign writeline_do = dcache_writeline_do \|\| control_ram_writeline_do;`
144			`assign writeline_address = (dcache_writeline_do)? dcache_writeline_address : control_ram_writeline_address;`
145			`assign writeline_line = (dcache_writeline_do)? dcache_writeline_line : control_ram_writeline_line;`
146
147			`assign dcache_busy = state != STATE_IDLE;`
148
149			`//------------------------------------------------------------------------------`
150
151			`wire [31:0] control_ram_address;`
152			`wire control_ram_read_do;`
153			`wire control_ram_write_do;`
154			`wire [10:0] control_ram_data;`
155			`wire [10:0] control_ram_q;`
156
157			`wire control_ram_writeline_do;`
158			`wire [31:0] control_ram_writeline_address;`
159			`wire [127:0] control_ram_writeline_line;`
160
161			`//------------------------------------------------------------------------------`
162
163			`wire matched;`
164			`wire [1:0] matched_index;`
165			`wire [127:0] matched_data_line;`
166
167			`wire [1:0] plru_index;`
168			`wire [147:0] plru_data_line;`
169
170			`wire [10:0] control_after_match;`
171			`wire [10:0] control_after_line_read;`
172			`wire [10:0] control_after_write_to_existing;`
173			`wire [10:0] control_after_write_to_new;`
174
175			`wire writeback_needed;`
176
177			`//------------------------------------------------------------------------------`
178
179			`wire [63:0] read_from_line;`
180			`wire [1:0] read_burst_dword_length;`
181			`wire [3:0] read_burst_byte_length;`
182			`wire [63:0] read_from_burst;`
183
184			`//------------------------------------------------------------------------------`
185
186			`wire [127:0] line_merged;`
187			`wire [1:0] write_burst_dword_length;`
188			`wire [3:0] write_burst_byteenable_0;`
189			`wire [3:0] write_burst_byteenable_1;`
190			`wire [55:0] write_burst_data;`
191
192			`//------------------------------------------------------------------------------`
193
194			`wire data_ram0_read_do;`
195			`wire [31:0] data_ram0_address;`
196			`wire data_ram0_write_do;`
197			`wire [127:0] data_ram0_data;`
198			`wire [147:0] data_ram0_q;`
199
200			`wire data_ram1_read_do;`
201			`wire [31:0] data_ram1_address;`
202			`wire data_ram1_write_do;`
203			`wire [127:0] data_ram1_data;`
204			`wire [147:0] data_ram1_q;`
205
206			`wire data_ram2_read_do;`
207			`wire [31:0] data_ram2_address;`
208			`wire data_ram2_write_do;`
209			`wire [127:0] data_ram2_data;`
210			`wire [147:0] data_ram2_q;`
211
212			`wire data_ram3_read_do;`
213			`wire [31:0] data_ram3_address;`
214			`wire data_ram3_write_do;`
215			`wire [127:0] data_ram3_data;`
216			`wire [147:0] data_ram3_q;`
217
218			`//------------------------------------------------------------------------------`
219
220			`dcache_matched dcache_matched_inst(`
221			`.address (address), //input [31:0]`
222
223			`.control (control_ram_q), //input [10:0]`
224
225			`.data_0 (data_ram0_q), //input [147:0]`
226			`.data_1 (data_ram1_q), //input [147:0]`
227			`.data_2 (data_ram2_q), //input [147:0]`
228			`.data_3 (data_ram3_q), //input [147:0]`
229
230			`.matched (matched), //output`
231			`.matched_index (matched_index), //output [2:0]`
232			`.matched_data_line (matched_data_line), //output [127:0]`
233
234			`.plru_index (plru_index), //output [1:0]`
235			`.plru_data_line (plru_data_line), //output [147:0]`
236
237			`.control_after_match (control_after_match), //output [10:0]`
238			`.control_after_line_read (control_after_line_read), //output [10:0]`
239			`.control_after_write_to_existing (control_after_write_to_existing), //output [10:0]`
240			`.control_after_write_to_new (control_after_write_to_new), //output [10:0]`
241
242			`.writeback_needed (writeback_needed) //output`
243			`);`
244
245
246
247			`dcache_read dcache_read_inst(`
248
249			`.line ((state == STATE_READ_LINE)? readline_line : matched_data_line), //input [127:0]`
250			`.read_data (readburst_data), //input [95:0]`
251
252			`.address (address), //input [31:0]`
253			`.length (length), //input [3:0]`
254
255			`.read_from_line (read_from_line), //output [63:0]`
256			`.read_burst_dword_length (read_burst_dword_length), //output [1:0]`
257			`.read_burst_byte_length (read_burst_byte_length), //output [11:0]`
258			`.read_from_burst (read_from_burst) //output [63:0]`
259			`);`
260
261			`dcache_write dcache_write_inst(`
262
263			`.line ((state == STATE_READ_LINE)? readline_line : matched_data_line), //input [127:0]`
264			`.address (address), //input [31:0]`
265			`.length (length[2:0]), //input [2:0]`
266			`.write_data (write_data), //input [31:0]`
267
268			`.write_burst_dword_length (write_burst_dword_length), //output [1:0]`
269			`.write_burst_byteenable_0 (write_burst_byteenable_0), //output [3:0]`
270			`.write_burst_byteenable_1 (write_burst_byteenable_1), //output [3:0]`
271			`.write_burst_data (write_burst_data), //output [55:0]`
272			`.line_merged (line_merged) //output [127:0]`
273			`);`
274
275			`dcache_control_ram dcache_control_ram_inst(`
276			`.clk (clk),`
277			`.rst_n (rst_n),`
278
279			`.address (control_ram_address), //input [31:0]`
280			`.data (control_ram_data), //input [10:0]`
281
282			`.q (control_ram_q), //output [10:0]`
283
284			`.read_do (control_ram_read_do),`
285
286
287			`.write_do (control_ram_write_do),`
288
289			`//RESP:`
290			`.invddata_do (invddata_do && state == STATE_IDLE), //input`
291			`.invddata_done (invddata_done), //output`
292			`//END`
293
294			`//RESP:`
295			`.wbinvddata_do (wbinvddata_do && state == STATE_IDLE), //input`
296			`.wbinvddata_done (wbinvddata_done), //output`
297			`//END`
298
299
300			`//REQ:`
301			`.wbinvdread_do (wbinvdread_do), //output`
302			`.wbinvdread_address (wbinvdread_address), //output [7:0]`
303
304			`.wbinvdread_ram0_q (data_ram0_q), //input [147:0]`
305			`.wbinvdread_ram1_q (data_ram1_q), //input [147:0]`
306			`.wbinvdread_ram2_q (data_ram2_q), //input [147:0]`
307			`.wbinvdread_ram3_q (data_ram3_q), //input [147:0]`
308			`//END`
309
310			`//REQ: write line`
311			`.writeline_do (control_ram_writeline_do), //output`
312			`.writeline_done (writeline_done), //input`
313
314			`.writeline_address (control_ram_writeline_address), //output [31:0]`
315			`.writeline_line (control_ram_writeline_line) //output [127:0]`
316			`//END`
317			`);`
318
319			`cache_data_ram cache_data_ram0_inst(`
320			`.clk (clk),`
321			`.rst_n (rst_n),`
322
323			`.read_do (data_ram0_read_do),`
324			`.address (data_ram0_address),`
325
326			`.write_do (data_ram0_write_do),`
327			`.data (data_ram0_data),`
328			`.q (data_ram0_q)`
329			`);`
330
331
332
333			`cache_data_ram cache_data_ram1_inst(`
334			`.clk (clk),`
335			`.rst_n (rst_n),`
336
337			`.read_do (data_ram1_read_do),`
338			`.address (data_ram1_address),`
339
340			`.write_do (data_ram1_write_do),`
341			`.data (data_ram1_data),`
342			`.q (data_ram1_q)`
343			`);`
344
345
346
347			`cache_data_ram cache_data_ram2_inst(`
348			`.clk (clk),`
349			`.rst_n (rst_n),`
350
351			`.read_do (data_ram2_read_do),`
352			`.address (data_ram2_address),`
353
354			`.write_do (data_ram2_write_do),`
355			`.data (data_ram2_data),`
356			`.q (data_ram2_q)`
357			`);`
358
359			`cache_data_ram cache_data_ram3_inst(`
360			`.clk (clk),`
361			`.rst_n (rst_n),`
362
363			`.read_do (data_ram3_read_do),`
364			`.address (data_ram3_address),`
365
366			`.write_do (data_ram3_write_do),`
367			`.data (data_ram3_data),`
368			`.q (data_ram3_q)`
369			`);`
370
371
372			`//------------------------------------------------------------------------------`
373
374			`//------------------------------------------------------------------------------`
375
376
377			`/*******************************************************************************SCRIPT`
378
379			`IF(state == STATE_IDLE);`
380
381			`IF(invddata_do);`
382
383			`//wait`
384
385			`ELSE_IF(wbinvddata_do);`
386
387			`SET(data_ram0_read_do, wbinvdread_do);`
388			`SET(data_ram0_address, { 20'd0, wbinvdread_address, 4'd0 });`
389
390			`SET(data_ram1_read_do, wbinvdread_do);`
391			`SET(data_ram1_address, { 20'd0, wbinvdread_address, 4'd0 });`
392
393			`SET(data_ram2_read_do, wbinvdread_do);`
394			`SET(data_ram2_address, { 20'd0, wbinvdread_address, 4'd0 });`
395
396			`SET(data_ram3_read_do, wbinvdread_do);`
397			`SET(data_ram3_address, { 20'd0, wbinvdread_address, 4'd0 });`
398
399			`ELSE_IF(dcachewrite_do);`
400
401			`SAVE(address, dcachewrite_address);`
402			`SAVE(cache_disable, dcachewrite_cache_disable);`
403			`SAVE(length, { 1'b0, dcachewrite_length });`
404
405			`SAVE(write_through, dcachewrite_write_through);`
406			`SAVE(write_data, dcachewrite_data);`
407
408			SAVE(is_write, `TRUE);
409
410			`SET(control_ram_read_do);`
411			`SET(control_ram_address, dcachewrite_address);`
412
413			`SET(data_ram0_read_do);`
414			`SET(data_ram0_address, dcachewrite_address);`
415
416			`SET(data_ram1_read_do);`
417			`SET(data_ram1_address, dcachewrite_address);`
418
419			`SET(data_ram2_read_do);`
420			`SET(data_ram2_address, dcachewrite_address);`
421
422			`SET(data_ram3_read_do);`
423			`SET(data_ram3_address, dcachewrite_address);`
424
425			`SET(dcachewrite_done);`
426
427			`SAVE(state, STATE_WRITE_CHECK);`
428
429			`ELSE_IF(dcacheread_do);`
430
431			`SAVE(address, dcacheread_address);`
432			`SAVE(cache_disable, dcacheread_cache_disable);`
433			`SAVE(length, dcacheread_length);`
434
435			SAVE(is_write, `FALSE);
436
437			`SET(control_ram_read_do);`
438			`SET(control_ram_address, dcacheread_address);`
439
440			`SET(data_ram0_read_do);`
441			`SET(data_ram0_address, dcacheread_address);`
442
443			`SET(data_ram1_read_do);`
444			`SET(data_ram1_address, dcacheread_address);`
445
446			`SET(data_ram2_read_do);`
447			`SET(data_ram2_address, dcacheread_address);`
448
449			`SET(data_ram3_read_do);`
450			`SET(data_ram3_address, dcacheread_address);`
451
452			`SAVE(state, STATE_READ_CHECK);`
453
454			`ENDIF();`
455			`ENDIF();`
456			`*/`
457
458			`/*******************************************************************************SCRIPT`
459
460			`IF(state == STATE_READ_CHECK);`
461
462			`IF(matched);`
463
464			`SET(control_ram_write_do);`
465			`SET(control_ram_address, address);`
466			`SET(control_ram_data, control_after_match);`
467
468			`SET(dcacheread_data, read_from_line);`
469			`SET(dcacheread_done);`
470
471			`SAVE(state, STATE_IDLE);`
472
473			`ELSE_IF(cache_disable);`
474
475			`SET(readburst_do);`
476			`SET(readburst_address, address);`
477			`SET(readburst_dword_length, read_burst_dword_length);`
478			`SET(readburst_byte_length, read_burst_byte_length);`
479
480			`SAVE(state, STATE_READ_BURST);`
481
482			`ELSE_IF(writeback_needed);`
483
484			`SET(dcache_writeline_do);`
485			`SET(dcache_writeline_address, { plru_data_line[147:128], address[11:4], 4'd0 });`
486			`SET(dcache_writeline_line, plru_data_line[127:0]);`
487
488			`SAVE(state, STATE_WRITE_BACK);`
489
490			`ELSE();`
491
492			`SET(readline_do);`
493			`SET(readline_address, { address[31:4], 4'd0 });`
494
495			`SAVE(state, STATE_READ_LINE);`
496			`ENDIF();`
497
498			`ENDIF();`
499			`*/`
500
501			`/*******************************************************************************SCRIPT`
502
503			`IF(state == STATE_WRITE_CHECK);`
504
505			`IF(matched);`
506
507			`SET(control_ram_write_do);`
508			`SET(control_ram_address, address);`
509			`SET(control_ram_data, control_after_write_to_existing);`
510
511			`IF(matched_index == 2'd0);`
512			`SET(data_ram0_write_do);`
513			`SET(data_ram0_address, address);`
514			`SET(data_ram0_data, line_merged);`
515			`ENDIF();`
516
517			`IF(matched_index == 2'd1);`
518			`SET(data_ram1_write_do);`
519			`SET(data_ram1_address, address);`
520			`SET(data_ram1_data, line_merged);`
521			`ENDIF();`
522
523			`IF(matched_index == 2'd2);`
524			`SET(data_ram2_write_do);`
525			`SET(data_ram2_address, address);`
526			`SET(data_ram2_data, line_merged);`
527			`ENDIF();`
528
529			`IF(matched_index == 2'd3);`
530			`SET(data_ram3_write_do);`
531			`SET(data_ram3_address, address);`
532			`SET(data_ram3_data, line_merged);`
533			`ENDIF();`
534
535			`IF(write_through);`
536
537			`SET(writeburst_do);`
538			`SET(writeburst_address, address);`
539			`SET(writeburst_dword_length, write_burst_dword_length);`
540			`SET(writeburst_byteenable_0, write_burst_byteenable_0);`
541			`SET(writeburst_byteenable_1, write_burst_byteenable_1);`
542			`SET(writeburst_data, write_burst_data);`
543
544			`SAVE(state, STATE_WRITE_THROUGH);`
545
546			`ELSE();`
547
548			`SET(dcachetoicache_write_do);`
549			`SET(dcachetoicache_write_address, address);`
550
551			`SAVE(state, STATE_IDLE);`
552			`ENDIF();`
553
554			`ELSE_IF(cache_disable);`
555
556			`SET(writeburst_do);`
557			`SET(writeburst_address, address);`
558			`SET(writeburst_dword_length, write_burst_dword_length);`
559			`SET(writeburst_byteenable_0, write_burst_byteenable_0);`
560			`SET(writeburst_byteenable_1, write_burst_byteenable_1);`
561			`SET(writeburst_data, write_burst_data);`
562
563			`SAVE(state, STATE_WRITE_THROUGH);`
564
565			`ELSE_IF(writeback_needed); // cache enabled and full`
566
567			`SET(dcache_writeline_do);`
568			`SET(dcache_writeline_address, { plru_data_line[147:128], address[11:4], 4'd0 });`
569			`SET(dcache_writeline_line, plru_data_line[127:0]);`
570
571			`SAVE(state, STATE_WRITE_BACK);`
572
573			`ELSE(); // cache enabled and not full`
574
575			`SET(readline_do);`
576			`SET(readline_address, { address[31:4], 4'd0 });`
577
578			`SAVE(state, STATE_READ_LINE);`
579
580			`ENDIF();`
581			`ENDIF();`
582			`*/`
583
584			`/*******************************************************************************SCRIPT`
585
586			`IF(state == STATE_READ_BURST);`
587
588			`IF(readburst_done);`
589
590			`SET(dcacheread_data, read_from_burst);`
591			`SET(dcacheread_done);`
592
593			`SAVE(state, STATE_IDLE);`
594			`ENDIF();`
595			`ENDIF();`
596			`*/`
597
598			`/*******************************************************************************SCRIPT`
599
600			`IF(state == STATE_WRITE_BACK);`
601
602			`IF(writeline_done);`
603
604			`SET(readline_do);`
605			`SET(readline_address, { address[31:4], 4'd0 });`
606
607			`SAVE(state, STATE_READ_LINE);`
608
609			`ENDIF();`
610			`ENDIF();`
611			`*/`
612
613			`/*******************************************************************************SCRIPT`
614
615			`IF(state == STATE_READ_LINE);`
616
617			`IF(readline_done);`
618
619			`IF(is_write);`
620
621			`SET(control_ram_write_do);`
622			`SET(control_ram_address, address);`
623			`SET(control_ram_data, control_after_write_to_new);`
624
625			`IF(plru_index == 2'd0);`
626			`SET(data_ram0_write_do);`
627			`SET(data_ram0_address, address);`
628			`SET(data_ram0_data, line_merged);`
629			`ENDIF();`
630
631			`IF(plru_index == 2'd1);`
632			`SET(data_ram1_write_do);`
633			`SET(data_ram1_address, address);`
634			`SET(data_ram1_data, line_merged);`
635			`ENDIF();`
636
637			`IF(plru_index == 2'd2);`
638			`SET(data_ram2_write_do);`
639			`SET(data_ram2_address, address);`
640			`SET(data_ram2_data, line_merged);`
641			`ENDIF();`
642
643			`IF(plru_index == 2'd3);`
644			`SET(data_ram3_write_do);`
645			`SET(data_ram3_address, address);`
646			`SET(data_ram3_data, line_merged);`
647			`ENDIF();`
648
649			`IF(write_through);`
650
651			`SET(writeburst_do);`
652			`SET(writeburst_address, address);`
653			`SET(writeburst_dword_length, write_burst_dword_length);`
654			`SET(writeburst_byteenable_0, write_burst_byteenable_0);`
655			`SET(writeburst_byteenable_1, write_burst_byteenable_1);`
656			`SET(writeburst_data, write_burst_data);`
657
658			`SAVE(state, STATE_WRITE_THROUGH);`
659
660			`ELSE();`
661
662			`SET(dcachetoicache_write_do);`
663			`SET(dcachetoicache_write_address, address);`
664
665			`SAVE(state, STATE_IDLE);`
666			`ENDIF();`
667
668			`ELSE();`
669
670			`SET(control_ram_write_do);`
671			`SET(control_ram_address, address);`
672			`SET(control_ram_data, control_after_line_read);`
673
674			`IF(plru_index == 2'd0);`
675			`SET(data_ram0_write_do);`
676			`SET(data_ram0_address, address);`
677			`SET(data_ram0_data, readline_line);`
678			`ENDIF();`
679
680			`IF(plru_index == 2'd1);`
681			`SET(data_ram1_write_do);`
682			`SET(data_ram1_address, address);`
683			`SET(data_ram1_data, readline_line);`
684			`ENDIF();`
685
686			`IF(plru_index == 2'd2);`
687			`SET(data_ram2_write_do);`
688			`SET(data_ram2_address, address);`
689			`SET(data_ram2_data, readline_line);`
690			`ENDIF();`
691
692			`IF(plru_index == 2'd3);`
693			`SET(data_ram3_write_do);`
694			`SET(data_ram3_address, address);`
695			`SET(data_ram3_data, readline_line);`
696			`ENDIF();`
697
698			`SET(dcacheread_data, read_from_line);`
699			`SET(dcacheread_done);`
700
701			`SAVE(state, STATE_IDLE);`
702			`ENDIF();`
703
704			`ENDIF();`
705			`ENDIF();`
706			`*/`
707
708			`/*******************************************************************************SCRIPT`
709
710			`IF(state == STATE_WRITE_THROUGH);`
711
712			`IF(writeburst_done);`
713
714			`SET(dcachetoicache_write_do);`
715			`SET(dcachetoicache_write_address, address);`
716
717			`SAVE(state, STATE_IDLE);`
718			`ENDIF();`
719			`ENDIF();`
720			`*/`
721
722			`//------------------------------------------------------------------------------`
723
724			`include "autogen/dcache.v"
725
726			`endmodule`