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[/] [ao486/] [trunk/] [rtl/] [ao486/] [pipeline/] [decode_commands.v] - Blame information for rev 2

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1 2 alfik 
/*
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 * Copyright (c) 2014, Aleksander Osman
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * * Redistributions of source code must retain the above copyright notice, this
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 *   list of conditions and the following disclaimer.
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 *
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 * * Redistributions in binary form must reproduce the above copyright notice,
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 *   this list of conditions and the following disclaimer in the documentation
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 *   and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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//PARSED_COMMENTS: this file contains parsed script comments
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module decode_commands(
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    input               protected_mode,
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    input               dec_ready_one,
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    input               dec_ready_one_one,
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    input               dec_ready_one_two,
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    input               dec_ready_one_three,
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    input               dec_ready_2byte_one,
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    input               dec_ready_modregrm_one,
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    input               dec_ready_2byte_modregrm,
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    input               dec_ready_call_jmp_imm,
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    input               dec_ready_one_imm,
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    input               dec_ready_2byte_imm,
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    input               dec_ready_mem_offset,
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    input               dec_ready_modregrm_imm,
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    input               dec_ready_2byte_modregrm_imm,
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    input       [95:0]  decoder,
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    input               prefix_group_1_lock,
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    input       [1:0]   dec_prefix_group_1_rep,
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    input               dec_prefix_2byte,
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    output              consume_one,
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    output              consume_one_one,
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    output              consume_one_two,
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    output              consume_one_three,
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    output              consume_call_jmp_imm,
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    output              consume_modregrm_one,
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    output              consume_one_imm,
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    output              consume_modregrm_imm,
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    output              consume_mem_offset,
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    output              dec_exception_ud,
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    output              dec_is_8bit,
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    output      [6:0]   dec_cmd,
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    output      [3:0]   dec_cmdex,
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    output              dec_is_complex
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);
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//------------------------------------------------------------------------------
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`define DEC_MODREGRM_IS_MOD_11  (decoder[15:14] == 2'b11)
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//------------------------------------------------------------------------------
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wire exception_ud_invalid;
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wire exception_ud;
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//------------------------------------------------------------------------------
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assign exception_ud_invalid =
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    (dec_ready_modregrm_one && (
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        (decoder[7:0] == 8'h8F && decoder[13:11] != 3'd0) ||
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        (decoder[7:0] == 8'hFE && decoder[13:12] != 2'd0) ||
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        (decoder[7:0] == 8'hFF && decoder[13:11] == 3'd7) ||
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        ({ decoder[7:1], 1'b0 } == 8'hC6 && decoder[13:11] != 3'd0) )) ||
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    (dec_ready_2byte_modregrm && (
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        (decoder[7:0] == 8'h00 && { decoder[13:12], 1'b0 } == 3'd6) ||
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        (decoder[7:0] == 8'h01 && decoder[13:11] == 3'd5) ||
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        (decoder[7:0] == 8'hBA && decoder[13] == 1'd0) )) ||
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    (dec_ready_modregrm_imm && (
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        ({ decoder[7:1], 1'b0 } == 8'hC6 && decoder[13:11] != 3'd0) )) ||
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    (dec_ready_2byte_one && (
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        { decoder[7:1], 1'b0 } == 8'hA6 || decoder[7:0] == 8'hAA || decoder[7:0] == 8'hAE ||
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        { decoder[7:1], 1'b0 } == 8'hB8 || (decoder[7:4] == 4'hC && decoder[3] == 1'b0 && decoder[2:1] != 2'b00) ||
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        (decoder[7:4] >= 4'hD) || (decoder[7:4] >= 4'h3 && decoder[7:4] <= 4'h7) || decoder[7:4] == 4'h1 ||
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        (decoder[7:4] == 4'h2 && decoder[3:0] >= 4'h4) || { decoder[7:1], 1'b0 } == 8'h04 || decoder[7:0] == 8'h07 ||
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        (decoder[7:4] == 4'd0 && decoder[3:0] >= 4'hA) ));
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//------------------------------------------------------------------------------
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assign dec_exception_ud = exception_ud_invalid || exception_ud;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, decoder[95:16], decoder[10:8], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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`include "autogen/decode_commands.v"
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endmodule

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