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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module decode_prefix(
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input clk,
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input rst_n,
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input [63:0] cs_cache,
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input dec_is_modregrm,
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input [95:0] decoder,
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input instr_prefix,
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input instr_finished,
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output dec_operand_32bit,
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output dec_address_32bit,
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output reg [1:0] dec_prefix_group_1_rep,
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output dec_prefix_group_1_lock,
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output [2:0] dec_prefix_group_2_seg,
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output reg dec_prefix_2byte,
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output [2:0] dec_modregrm_len,
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output reg [3:0] prefix_count,
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output is_prefix,
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output reg prefix_group_1_lock
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);
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//------------------------------------------------------------------------------
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reg [2:0] prefix_group_2;
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reg prefix_group_3;
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reg prefix_group_4;
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//------------------------------------------------------------------------------
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wire modregrm_ss_selected;
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wire CRx_DRx_condition;
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wire dec_address_16bit;
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//------------------------------------------------------------------------------
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/*
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group 1:
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1: F2H REPNE/REPNZ prefix (used only with string instructions)
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2: F3H REP prefix (used only with string instructions)
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group 1 lock:
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1: F0H LOCK prefix
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group 2:
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0: 26H ES segment override prefix
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1: 2EH CS segment override prefix
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2: 36H SS segment override prefix
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3: 3EH DS segment override prefix
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4: 64H FS segment override prefix
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5: 65H GS segment override prefix
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group 3:
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1: 66H Operand-size override
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group 4:
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1: 67H Address-size override
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*/
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//------------------------------------------------------------------------------
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assign dec_operand_32bit = cs_cache[`DESC_BIT_D_B] ^ prefix_group_3;
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assign dec_address_32bit = cs_cache[`DESC_BIT_D_B] ^ prefix_group_4;
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assign dec_address_16bit = ~dec_address_32bit;
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assign dec_modregrm_len =
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(CRx_DRx_condition)? 3'd2 :
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(dec_address_16bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b110)? 3'd4 :
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(dec_address_16bit && decoder[15:14] == 2'b01)? 3'd3 :
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(dec_address_16bit && decoder[15:14] == 2'b10)? 3'd4 :
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(dec_address_16bit)? 3'd2 :
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(dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b101)? 3'd6 :
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(dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b101)? 3'd7 :
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(dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b100)? 3'd3 :
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(dec_address_32bit && decoder[15:14] == 2'b01 && decoder[10:8] == 3'b100)? 3'd4 :
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(dec_address_32bit && decoder[15:14] == 2'b01)? 3'd3 :
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(dec_address_32bit && decoder[15:14] == 2'b10 && decoder[10:8] == 3'b100)? 3'd7 :
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(dec_address_32bit && decoder[15:14] == 2'b10)? 3'd6 :
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3'd2;
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assign is_prefix =
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decoder[7:0] == 8'hF2 || decoder[7:0] == 8'hF3 || decoder[7:0] == 8'hF0 || decoder[7:0] == 8'h26 ||
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decoder[7:0] == 8'h2E || decoder[7:0] == 8'h36 || decoder[7:0] == 8'h3E || decoder[7:0] == 8'h64 ||
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decoder[7:0] == 8'h65 || decoder[7:0] == 8'h66 || decoder[7:0] == 8'h67 || decoder[7:0] == 8'h0F;
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dec_prefix_group_1_rep <= 2'd0;
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else if(instr_finished) dec_prefix_group_1_rep <= 2'd0;
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else if(instr_prefix && decoder[7:0] == 8'hF2) dec_prefix_group_1_rep <= 2'd1;
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else if(instr_prefix && decoder[7:0] == 8'hF3) dec_prefix_group_1_rep <= 2'd2;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) prefix_group_1_lock <= 1'd0;
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else if(instr_finished) prefix_group_1_lock <= 1'd0;
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else if(instr_prefix && decoder[7:0] == 8'hF0) prefix_group_1_lock <= 1'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) prefix_group_2 <= 3'd7;
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else if(instr_finished) prefix_group_2 <= 3'd7;
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else if(instr_prefix && decoder[7:0] == 8'h26) prefix_group_2 <= 3'd0;
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else if(instr_prefix && decoder[7:0] == 8'h2E) prefix_group_2 <= 3'd1;
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else if(instr_prefix && decoder[7:0] == 8'h36) prefix_group_2 <= 3'd2;
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else if(instr_prefix && decoder[7:0] == 8'h3E) prefix_group_2 <= 3'd3;
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else if(instr_prefix && decoder[7:0] == 8'h64) prefix_group_2 <= 3'd4;
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else if(instr_prefix && decoder[7:0] == 8'h65) prefix_group_2 <= 3'd5;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) prefix_group_3 <= 1'd0;
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else if(instr_finished) prefix_group_3 <= 1'd0;
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else if(instr_prefix && decoder[7:0] == 8'h66) prefix_group_3 <= 1'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) prefix_group_4 <= 1'd0;
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else if(instr_finished) prefix_group_4 <= 1'd0;
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else if(instr_prefix && decoder[7:0] == 8'h67) prefix_group_4 <= 1'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) dec_prefix_2byte <= 1'd0;
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else if(instr_finished) dec_prefix_2byte <= 1'd0;
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else if(instr_prefix && decoder[7:0] == 8'h0F) dec_prefix_2byte <= 1'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) prefix_count <= 4'd0;
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else if(instr_finished) prefix_count <= 4'd0;
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else if(instr_prefix) prefix_count <= prefix_count + 4'd1;
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end
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//------------------------------------------------------------------------------
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// XCHG always has LOCK
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assign dec_prefix_group_1_lock =
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prefix_group_1_lock ||
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(~(dec_prefix_2byte) && { decoder[7:1], 1'b0 } == 8'h86 && decoder[15:14] != 2'b11);
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// mod bits are always 2'b11
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assign CRx_DRx_condition = dec_prefix_2byte && { decoder[7:2], 2'b00 } == 8'h20;
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// modregrm using esp or ebp
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assign modregrm_ss_selected = dec_is_modregrm && ~(CRx_DRx_condition) &&
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( (dec_address_32bit && (decoder[15:14] == 2'b01 || decoder[15:14] == 2'b10) && decoder[10:8] == 3'b101) ||
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(dec_address_32bit && decoder[15:14] != 2'b11 && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b100) ||
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(dec_address_32bit && (decoder[15:14] == 2'b01 || decoder[15:14] == 2'b10) && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b101) ||
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(dec_address_16bit && decoder[15:14] == 2'b00 && decoder[10:9] == 2'b01) ||
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(dec_address_16bit && (decoder[15:14] == 2'b01 || decoder[15:14] == 2'b10) && (decoder[10:9] == 2'b01 || decoder[10:8] == 3'b110))
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);
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assign dec_prefix_group_2_seg =
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(prefix_group_2 == 3'd7 && modregrm_ss_selected)? 3'd2 :
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(prefix_group_2 == 3'd7)? 3'd3 :
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prefix_group_2;
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, cs_cache[63:55], cs_cache[53:0], decoder[95:19], decoder[13:11], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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endmodule
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