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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module decode_regs(
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input clk,
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input rst_n,
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input dec_reset,
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input [3:0] fetch_valid,
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input [63:0] fetch,
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input [3:0] prefix_count,
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input [3:0] consume_count,
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output [3:0] dec_acceptable,
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output reg [95:0] decoder,
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output reg [3:0] decoder_count
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);
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//------------------------------------------------------------------------------
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wire [3:0] after_consume_count;
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wire [4:0] total_count;
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wire [3:0] acceptable_1;
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wire [3:0] acceptable_2;
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wire [3:0] accepted;
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wire [95:0] after_consume;
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wire [95:0] decoder_next;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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assign after_consume_count = decoder_count - consume_count;
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assign total_count = prefix_count + decoder_count;
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//------------------------------------------------------------------------------
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// acceptable by decoder
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assign acceptable_1 = 4'd12 - decoder_count + consume_count;
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// acceptable by total instruction length
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assign acceptable_2 = (total_count < 5'd15)? 4'd15 - total_count[3:0] : 4'd0;
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assign dec_acceptable = (dec_reset)? 4'd0 :
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(acceptable_1 < acceptable_2)? acceptable_1 : acceptable_2;
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assign accepted = (dec_acceptable > fetch_valid)? fetch_valid : dec_acceptable;
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//------------------------------------------------------------------------------
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assign after_consume =
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(consume_count == 4'd0)? decoder :
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(consume_count == 4'd1)? { 8'd0, decoder[95:8] } :
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(consume_count == 4'd2)? { 16'd0, decoder[95:16] } :
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(consume_count == 4'd3)? { 24'd0, decoder[95:24] } :
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(consume_count == 4'd4)? { 32'd0, decoder[95:32] } :
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(consume_count == 4'd5)? { 40'd0, decoder[95:40] } :
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(consume_count == 4'd6)? { 48'd0, decoder[95:48] } :
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(consume_count == 4'd7)? { 56'd0, decoder[95:56] } :
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(consume_count == 4'd8)? { 64'd0, decoder[95:64] } :
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(consume_count == 4'd9)? { 72'd0, decoder[95:72] } :
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(consume_count == 4'd10)? { 80'd0, decoder[95:80] } :
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{ 88'd0, decoder[95:88] };
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assign decoder_next =
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(after_consume_count == 4'd0)? { 32'd0,fetch } :
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(after_consume_count == 4'd1)? { 24'd0,fetch, after_consume[7:0] } :
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(after_consume_count == 4'd2)? { 16'd0,fetch, after_consume[15:0] } :
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(after_consume_count == 4'd3)? { 8'd0, fetch, after_consume[23:0] } :
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(after_consume_count == 4'd4)? { fetch, after_consume[31:0] } :
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(after_consume_count == 4'd5)? { fetch[55:0], after_consume[39:0] } :
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(after_consume_count == 4'd6)? { fetch[47:0], after_consume[47:0] } :
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(after_consume_count == 4'd7)? { fetch[39:0], after_consume[55:0] } :
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(after_consume_count == 4'd8)? { fetch[31:0], after_consume[63:0] } :
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(after_consume_count == 4'd9)? { fetch[23:0], after_consume[71:0] } :
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(after_consume_count == 4'd10)? { fetch[15:0], after_consume[79:0] } :
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(after_consume_count == 4'd11)? { fetch[7:0], after_consume[87:0] } :
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after_consume;
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) decoder <= 96'd0;
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else decoder <= decoder_next;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) decoder_count <= 4'd0;
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else if(dec_reset) decoder_count <= 4'd0;
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else decoder_count <= after_consume_count + accepted;
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end
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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endmodule
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