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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module microcode(
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input clk,
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input rst_n,
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input micro_reset,
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input exc_init,
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input exc_load,
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input [31:0] exc_eip,
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input [31:0] task_eip,
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//command control
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input real_mode,
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input v8086_mode,
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input protected_mode,
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input io_allow_check_needed,
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input exc_push_error,
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input cr0_pg,
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input oflag,
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input ntflag,
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input [1:0] cpl,
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input [31:0] glob_param_1,
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input [31:0] glob_param_3,
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input [63:0] glob_descriptor,
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//decoder
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output micro_busy,
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input dec_ready,
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input [95:0] decoder,
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input [31:0] dec_eip,
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input dec_operand_32bit,
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input dec_address_32bit,
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input [1:0] dec_prefix_group_1_rep,
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input dec_prefix_group_1_lock,
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input [2:0] dec_prefix_group_2_seg,
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input dec_prefix_2byte,
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input [3:0] dec_consumed,
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input [2:0] dec_modregrm_len,
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input dec_is_8bit,
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input [6:0] dec_cmd,
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input [3:0] dec_cmdex,
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input dec_is_complex,
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//micro
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input rd_busy,
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output micro_ready,
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output [87:0] micro_decoder,
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output [31:0] micro_eip,
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output micro_operand_32bit,
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output micro_address_32bit,
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output [1:0] micro_prefix_group_1_rep,
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output micro_prefix_group_1_lock,
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output [2:0] micro_prefix_group_2_seg,
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output micro_prefix_2byte,
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output [3:0] micro_consumed,
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output [2:0] micro_modregrm_len,
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output micro_is_8bit,
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output [6:0] micro_cmd,
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output [3:0] micro_cmdex
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);
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//------------------------------------------------------------------------------
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wire task_start;
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wire m_overlay;
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wire m_load;
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//------------------------------------------------------------------------------
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reg mc_operand_32bit;
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reg mc_address_32bit;
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reg [1:0] mc_prefix_group_1_rep;
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reg mc_prefix_group_1_lock;
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reg [2:0] mc_prefix_group_2_seg;
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reg mc_prefix_2byte;
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reg [87:0] mc_decoder;
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reg [2:0] mc_modregrm_len;
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reg mc_is_8bit;
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reg [6:0] mc_cmd;
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reg [3:0] mc_cmdex;
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reg [3:0] mc_consumed;
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reg [31:0] mc_eip;
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reg [5:0] mc_step;
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reg [3:0] mc_cmdex_last;
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//------------------------------------------------------------------------------
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assign micro_busy = rd_busy || m_overlay;
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assign micro_ready = ~(micro_reset) && ((~(m_overlay) && dec_ready) || (m_overlay && ~(rd_busy)));
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assign m_load = dec_ready && dec_is_complex;
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assign m_overlay = mc_cmd != `CMD_NULL;
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assign task_start = micro_cmd == `CMD_task_switch_4 && micro_cmdex == `CMDEX_task_switch_4_STEP_1 && micro_ready;
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//------------------------------------------------------------------------------
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wire [6:0] mc_cmd_next;
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wire [6:0] mc_cmd_current;
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wire [3:0] mc_cmdex_current;
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microcode_commands microcode_commands_inst(
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.clk (clk),
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.rst_n (rst_n),
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.protected_mode (protected_mode), //input
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.real_mode (real_mode), //input
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.v8086_mode (v8086_mode), //input
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.io_allow_check_needed (io_allow_check_needed), //input
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.exc_push_error (exc_push_error), //input
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.cr0_pg (cr0_pg), //input
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.oflag (oflag), //input
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.ntflag (ntflag), //input
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.cpl (cpl), //input [1:0]
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.glob_param_1 (glob_param_1), //input [31:0]
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.glob_param_3 (glob_param_3), //input [31:0]
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.glob_descriptor (glob_descriptor), //input [63:0]
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.mc_operand_32bit (mc_operand_32bit), //input
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.mc_cmd (mc_cmd), //input [6:0]
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.mc_decoder (mc_decoder), //input [87:0]
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.mc_step (mc_step), //input [5:0]
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.mc_cmdex_last (mc_cmdex_last), //input [3:0]
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.mc_cmd_next (mc_cmd_next), //output [6:0]
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.mc_cmd_current (mc_cmd_current), //output [6:0]
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.mc_cmdex_current (mc_cmdex_current) //output [3:0]
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);
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_operand_32bit <= `FALSE; else if(m_load) mc_operand_32bit <= dec_operand_32bit; else if(exc_init) mc_operand_32bit <= `FALSE; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_address_32bit <= `FALSE; else if(m_load) mc_address_32bit <= dec_address_32bit; else if(exc_init) mc_address_32bit <= `FALSE; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_prefix_group_1_rep <= 2'd0; else if(m_load) mc_prefix_group_1_rep <= dec_prefix_group_1_rep; else if(exc_init) mc_prefix_group_1_rep <= 2'd0; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_prefix_group_1_lock <= `FALSE; else if(m_load) mc_prefix_group_1_lock <= dec_prefix_group_1_lock; else if(exc_init) mc_prefix_group_1_lock <= `FALSE; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_prefix_group_2_seg <= 3'd3; else if(m_load) mc_prefix_group_2_seg <= dec_prefix_group_2_seg; else if(exc_init) mc_prefix_group_2_seg <= 3'd3; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_prefix_2byte <= `FALSE; else if(m_load) mc_prefix_2byte <= dec_prefix_2byte; else if(exc_init) mc_prefix_2byte <= `FALSE; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_decoder <= 88'd0; else if(m_load) mc_decoder <= decoder[87:0]; else if(exc_init) mc_decoder <= 88'd0; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_modregrm_len <= 3'd0; else if(m_load) mc_modregrm_len <= dec_modregrm_len; else if(exc_init) mc_modregrm_len <= 3'd0; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) mc_is_8bit <= `FALSE; else if(m_load) mc_is_8bit <= dec_is_8bit; else if(exc_init) mc_is_8bit <= `FALSE; end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mc_cmd <= `CMD_NULL;
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else if(exc_init) mc_cmd <= `CMD_int;
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else if(micro_reset) mc_cmd <= `CMD_NULL;
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else if(m_load) mc_cmd <= dec_cmd;
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else if(micro_ready) mc_cmd <= mc_cmd_next;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mc_cmdex <= 4'd0;
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else if(m_load) mc_cmdex <= dec_cmdex;
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else if(exc_init) mc_cmdex <= `CMDEX_int_STEP_0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mc_consumed <= 4'd0;
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else if(m_load) mc_consumed <= dec_consumed;
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else if(task_start) mc_consumed <= 4'd0;
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else if(exc_load) mc_consumed <= 4'd0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mc_eip <= 32'd0;
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else if(m_load) mc_eip <= dec_eip;
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else if(task_start) mc_eip <= task_eip;
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else if(exc_load) mc_eip <= exc_eip;
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end
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//------------------------------------------------------------------------------
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assign micro_operand_32bit = (m_overlay)? mc_operand_32bit : dec_operand_32bit;
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assign micro_address_32bit = (m_overlay)? mc_address_32bit : dec_address_32bit;
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assign micro_prefix_group_1_rep = (m_overlay)? mc_prefix_group_1_rep : dec_prefix_group_1_rep;
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assign micro_prefix_group_1_lock = (m_overlay)? mc_prefix_group_1_lock : dec_prefix_group_1_lock;
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assign micro_prefix_group_2_seg = (m_overlay)? mc_prefix_group_2_seg : dec_prefix_group_2_seg;
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assign micro_prefix_2byte = (m_overlay)? mc_prefix_2byte : dec_prefix_2byte;
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assign micro_decoder = (m_overlay)? mc_decoder : decoder[87:0];
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assign micro_modregrm_len = (m_overlay)? mc_modregrm_len : dec_modregrm_len;
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assign micro_is_8bit = (m_overlay)? mc_is_8bit : dec_is_8bit;
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assign micro_cmd =
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(exc_load)? mc_cmd :
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(m_overlay)? mc_cmd_current :
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dec_cmd;
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assign micro_cmdex =
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(exc_load)? mc_cmdex :
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(m_overlay)? mc_cmdex_current :
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dec_cmdex;
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assign micro_consumed =
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(task_start)? 4'd0 :
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(exc_load)? 4'd0 :
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(m_overlay)? mc_consumed :
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dec_consumed;
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assign micro_eip =
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(task_start)? task_eip :
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(exc_load)? exc_eip :
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(m_overlay)? mc_eip :
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dec_eip;
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mc_step <= 6'd0;
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else if(m_load) mc_step <= 6'd1;
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else if(micro_ready) mc_step <= mc_step + 6'd1;
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else if(exc_init) mc_step <= 6'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mc_cmdex_last <= 4'd0;
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else if(micro_ready) mc_cmdex_last <= micro_cmdex;
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else if(exc_init) mc_cmdex_last <= `CMDEX_int_STEP_0;
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end
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, decoder[95:88], 1'b0 };
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// synthesis translate_on
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endmodule
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